From 090c2202751f30e041017fd2df9117877d53d99a Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 4 Aug 2021 11:26:06 +0000 Subject: [PATCH] drm/amd/display: ensure dentist display clock update finished in DCN20 From Dale Zhao 63570e578094b4f0b6b8c6ac4a68195455733e31 in linux 5.10.y/5.10.56 b53e041d8e4308f7324999398aec092dbcb130f5 in mainline linux --- sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index f2114bc910b..6b744edcd75 100644 --- a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -135,7 +135,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); -// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); -- 2.20.1