From 082bf5710cac3aff903f67c7987cca5284b71ec5 Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 23 Apr 2021 04:35:54 +0000 Subject: [PATCH] add missing break ok drahn@ --- sys/arch/riscv64/riscv64/fpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/arch/riscv64/riscv64/fpu.c b/sys/arch/riscv64/riscv64/fpu.c index 076caaf126a..2128dc0f71a 100644 --- a/sys/arch/riscv64/riscv64/fpu.c +++ b/sys/arch/riscv64/riscv64/fpu.c @@ -55,6 +55,7 @@ int fpu_valid_opcode(uint32_t instr) case 0x2002: // C.FLDSP // must verify dest register is float valid = opcode16 & (1 << 11); + break; case 0xa002: // C.FSDSP // must verify dest register is float valid = opcode16 & (1 << 6); -- 2.20.1