From 0504914dbc73b41917177da90e3185196887c761 Mon Sep 17 00:00:00 2001 From: oga Date: Fri, 6 Aug 2010 13:12:20 +0000 Subject: [PATCH] save/restore the *correct* clock gating registers on suspend/resume instead of accidentally writing zeros to ones that may not even exist on the chipset we're running on. problem noted by damien@, fix by me. been in theo's tree a couple of days. ``commit'' deraadt@. --- sys/dev/pci/drm/i915_drv.c | 52 ++++++++++++++++++++++++++++++++++++-- sys/dev/pci/drm/i915_drv.h | 5 ++++ 2 files changed, 55 insertions(+), 2 deletions(-) diff --git a/sys/dev/pci/drm/i915_drv.c b/sys/dev/pci/drm/i915_drv.c index ea88e97fa89..86cc34c6b14 100644 --- a/sys/dev/pci/drm/i915_drv.c +++ b/sys/dev/pci/drm/i915_drv.c @@ -5633,6 +5633,32 @@ inteldrm_save_state(struct inteldrm_softc *dev_priv) dev_priv->saveIMR = I915_READ(IMR); } + /* Clock gating state */ + if (IS_IRONLAKE(dev_priv)) { + dev_priv->saveDSPCLK_GATE_D = I915_READ(PCH_DSPCLK_GATE_D); + dev_priv->saveDSPCLK_GATE = I915_READ(ILK_DSPCLK_GATE); + } else if (IS_G4X(dev_priv)) { + dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1); + dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2); + dev_priv->saveRAMCLK_GATE_D = I915_READ(RAMCLK_GATE_D); + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); + } else if (IS_I965GM(dev_priv)) { + dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1); + dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2); + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); + dev_priv->saveRAMCLK_GATE_D = I915_READ(RAMCLK_GATE_D); + dev_priv->saveDEUC = I915_READ16(DEUC); + } else if (IS_I965G(dev_priv)) { + dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1); + dev_priv->saveRENCLK_GATE_D2 = I915_READ(RENCLK_GATE_D2); + } else if (IS_I9XX(dev_priv)) { + dev_priv->saveD_STATE = I915_READ(D_STATE); + } else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) { + dev_priv->saveRENCLK_GATE_D1 = I915_READ(RENCLK_GATE_D1); + } else if (IS_I830(dev_priv)) { + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); + } + /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -5704,8 +5730,30 @@ inteldrm_restore_state(struct inteldrm_softc *dev_priv) } /* Clock gating state */ - I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + if (IS_IRONLAKE(dev_priv)) { + I915_WRITE(PCH_DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + I915_WRITE(ILK_DSPCLK_GATE, dev_priv->saveDSPCLK_GATE); + } if (IS_G4X(dev_priv)) { + I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1); + I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2); + I915_WRITE(RAMCLK_GATE_D, dev_priv->saveRAMCLK_GATE_D); + I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + } else if (IS_I965GM(dev_priv)) { + I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1); + I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2); + I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + I915_WRITE(RAMCLK_GATE_D, dev_priv->saveRAMCLK_GATE_D); + I915_WRITE16(DEUC, dev_priv->saveDEUC); + } else if (IS_I965G(dev_priv)) { + I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1); + I915_WRITE(RENCLK_GATE_D2, dev_priv->saveRENCLK_GATE_D2); + } else if (IS_I9XX(dev_priv)) { + I915_WRITE(D_STATE, dev_priv->saveD_STATE); + } else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) { + I915_WRITE(RENCLK_GATE_D1, dev_priv->saveRENCLK_GATE_D1); + } else if (IS_I830(dev_priv)) { + I915_WRITE(DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + } /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h index 2063f969788..30ac442f80d 100644 --- a/sys/dev/pci/drm/i915_drv.h +++ b/sys/dev/pci/drm/i915_drv.h @@ -247,6 +247,11 @@ struct inteldrm_softc { u32 saveCACHE_MODE_0; u32 saveD_STATE; u32 saveDSPCLK_GATE_D; + u32 saveDSPCLK_GATE; + u32 saveRENCLK_GATE_D1; + u32 saveRENCLK_GATE_D2; + u32 saveRAMCLK_GATE_D; + u32 saveDEUC; u32 saveMI_ARB_STATE; u32 saveSWF0[16]; u32 saveSWF1[16]; -- 2.20.1