From: jsg Date: Fri, 25 Jun 2021 13:41:09 +0000 (+0000) Subject: add linux style memory barriers for risc-v to drm X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=fee0b6a15f91c60541c2546cf2c7976677b2a9ca;p=openbsd add linux style memory barriers for risc-v to drm based on linux operation to rvwmo mapping table in the rvwmo appendix of the risc-v unprivileged isa spec ok kettenis@ --- diff --git a/sys/dev/pci/drm/include/linux/atomic.h b/sys/dev/pci/drm/include/linux/atomic.h index c94eb4e921d..396e7f4bc05 100644 --- a/sys/dev/pci/drm/include/linux/atomic.h +++ b/sys/dev/pci/drm/include/linux/atomic.h @@ -1,4 +1,4 @@ -/* $OpenBSD: atomic.h,v 1.15 2020/11/09 23:53:30 jsg Exp $ */ +/* $OpenBSD: atomic.h,v 1.16 2021/06/25 13:41:09 jsg Exp $ */ /** * \file drm_atomic.h * Atomic operations used in the DRM which may or may not be provided by the OS. @@ -426,6 +426,13 @@ find_next_bit(volatile void *p, int max, int b) #define wmb() __membar("sync") #define mb() __membar("sync") #define smp_wmb() __membar("eieio") +#elif defined(__riscv) +#define rmb() __membar("fence ir,ir") +#define wmb() __membar("fence ow,ow") +#define mb() __membar("fence iorw,iorw") +#define smp_rmb() __membar("fence r,r") +#define smp_wmb() __membar("fence w,w") +#define smp_mb() __membar("fence rw,rw") #elif defined(__sparc64__) #define rmb() membar_sync() #define wmb() membar_sync()