From: kettenis Date: Sun, 5 Aug 2018 21:05:17 +0000 (+0000) Subject: Fix typo that caused us to misassign parents. X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=fd4119f17d63cbf0e665520de29fc415c4233322;p=openbsd Fix typo that caused us to misassign parents. ok patrick@ --- diff --git a/sys/dev/ofw/ofw_clock.c b/sys/dev/ofw/ofw_clock.c index 4242641a48d..077c515c1fe 100644 --- a/sys/dev/ofw/ofw_clock.c +++ b/sys/dev/ofw/ofw_clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ofw_clock.c,v 1.10 2018/06/03 18:17:27 kettenis Exp $ */ +/* $OpenBSD: ofw_clock.c,v 1.11 2018/08/05 21:05:17 kettenis Exp $ */ /* * Copyright (c) 2016 Mark Kettenis * @@ -311,7 +311,7 @@ clock_set_assigned(int node) } while (clock && clock < clocks + (clen / sizeof(uint32_t))) { - if (parent && parent < parent + (plen / sizeof(uint32_t))) + if (parent && parent < parents + (plen / sizeof(uint32_t))) if (*parent != 0) clock_set_parent_cells(clock, parent);