From: uaa <uaa@openbsd.org>
Date: Fri, 3 Dec 2021 19:22:42 +0000 (+0000)
Subject: add Allwinner H6 support
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=e67d85891b2554bf61cfdcb7fc34ddd7163f2187;p=openbsd

add Allwinner H6 support
ok kettenis@
---

diff --git a/sys/dev/fdt/ehci_fdt.c b/sys/dev/fdt/ehci_fdt.c
index a1bd6522a7c..346d84c7889 100644
--- a/sys/dev/fdt/ehci_fdt.c
+++ b/sys/dev/fdt/ehci_fdt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ehci_fdt.c,v 1.7 2021/10/24 17:52:26 mpi Exp $ */
+/*	$OpenBSD: ehci_fdt.c,v 1.8 2021/12/03 19:22:42 uaa Exp $ */
 
 /*
  * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
@@ -174,6 +174,7 @@ struct ehci_phy ehci_phys[] = {
 	{ "allwinner,sun8i-h3-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun8i-r40-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init },
+	{ "allwinner,sun50i-h6-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun50i-a64-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun9i-a80-usb-phy", sun9i_phy_init },
 };
@@ -274,6 +275,7 @@ sun4i_phy_init(struct ehci_fdt_softc *sc, uint32_t *cells)
 	 */
 	if (OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") ||
 	    OF_is_compatible(node, "allwinner,sun8i-r40-usb-phy") ||
+	    OF_is_compatible(node, "allwinner,sun50i-h6-usb-phy") ||
 	    OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) {
 		val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
 		val &= ~(1 << 1);
diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c
index b27a6408ae9..140473537fa 100644
--- a/sys/dev/fdt/sxiccmu.c
+++ b/sys/dev/fdt/sxiccmu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiccmu.c,v 1.29 2021/10/24 17:52:27 mpi Exp $	*/
+/*	$OpenBSD: sxiccmu.c,v 1.30 2021/12/03 19:22:42 uaa Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -1311,15 +1311,30 @@ sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 	return 0;
 }
 
+/* Allwinner H6 */
+#define H6_AHB3_CFG_REG		0x051c
+#define H6_AHB3_CLK_FACTOR_N(x)	(((x) >> 8) & 0x3)
+#define H6_AHB3_CLK_FACTOR_M(x)	(((x) >> 0) & 0x3)
+
 uint32_t
 sxiccmu_h6_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 {
+	uint32_t reg, m, n;
+	uint32_t freq;
+
 	switch (idx) {
 	case H6_CLK_PLL_PERIPH0:
 		/* Not hardcoded, but recommended. */
 		return 600000000;
 	case H6_CLK_PLL_PERIPH0_2X:
 		return sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0) * 2;
+	case H6_CLK_AHB3:
+		reg = SXIREAD4(sc, H6_AHB3_CFG_REG);
+		/* assume PLL_PERIPH0 source */
+		freq = sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0);
+		m = H6_AHB3_CLK_FACTOR_M(reg) + 1;
+		n = 1 << H6_AHB3_CLK_FACTOR_N(reg);
+		return freq / (m * n);
 	case H6_CLK_APB2:
 		/* XXX Controlled by a MUX. */
 		return 24000000;
diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h
index 0c1774a77eb..017928faafc 100644
--- a/sys/dev/fdt/sxiccmu_clocks.h
+++ b/sys/dev/fdt/sxiccmu_clocks.h
@@ -408,6 +408,7 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
 
 #define H6_CLK_PLL_PERIPH0	3
 #define H6_CLK_PLL_PERIPH0_2X	4
+#define H6_CLK_AHB3		25
 #define H6_CLK_APB1		26
 #define H6_CLK_APB2		27
 #define H6_CLK_MMC0		64
@@ -420,8 +421,12 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
 #define H6_CLK_BUS_UART1	71
 #define H6_CLK_BUS_UART2	72
 #define H6_CLK_BUS_UART3	73
+#define H6_CLK_BUS_EMAC		84
 #define H6_CLK_USB_OHCI0	104
+#define H6_CLK_USB_PHY0		105
+#define H6_CLK_USB_PHY1		106
 #define H6_CLK_USB_OHCI3	107
+#define H6_CLK_USB_PHY3		108
 #define H6_CLK_BUS_OHCI0	111
 #define H6_CLK_BUS_OHCI3	112
 #define H6_CLK_BUS_EHCI0	113
@@ -440,8 +445,12 @@ struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
 	[H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 },
 	[H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 },
 	[H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 },
+	[H6_CLK_BUS_EMAC] = { 0x097c, 0, H6_CLK_AHB3 },
 	[H6_CLK_USB_OHCI0] = { 0x0a70, 31 },
+	[H6_CLK_USB_PHY0] = { 0x0a70, 29 },
+	[H6_CLK_USB_PHY1] = { 0x0a74, 29 },
 	[H6_CLK_USB_OHCI3] = { 0x0a7c, 31 },
+	[H6_CLK_USB_PHY3] = { 0x0a7c, 29 },
 	[H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
 	[H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 },
 	[H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
@@ -451,10 +460,12 @@ struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
 #define H6_R_CLK_APB1		2
 #define H6_R_CLK_APB2		3
 #define H6_R_CLK_APB2_I2C	8
+#define H6_R_CLK_APB2_RSB	13
 
 struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = {
 	[H6_R_CLK_APB1] = { 0xffff, 0xff },
-	[H6_R_CLK_APB2_I2C] = { 0x019c, 1, H6_R_CLK_APB2 },
+	[H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 },
+	[H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 },
 };
 
 /* R40 */
@@ -833,6 +844,10 @@ struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
 #define H6_RST_BUS_UART1	22
 #define H6_RST_BUS_UART2	23
 #define H6_RST_BUS_UART3	24
+#define H6_RST_BUS_EMAC		33
+#define H6_RST_USB_PHY0		44
+#define H6_RST_USB_PHY1		45
+#define H6_RST_USB_PHY3		46
 #define H6_RST_BUS_OHCI0	48
 #define H6_RST_BUS_OHCI3	49
 #define H6_RST_BUS_EHCI0	50
@@ -846,6 +861,10 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
 	[H6_RST_BUS_UART1] = { 0x090c, 17 },
 	[H6_RST_BUS_UART2] = { 0x090c, 18 },
 	[H6_RST_BUS_UART3] = { 0x090c, 19 },
+	[H6_RST_BUS_EMAC] = { 0x097c, 16 },
+	[H6_RST_USB_PHY0] = { 0x0a70, 30 },
+	[H6_RST_USB_PHY1] = { 0x0a74, 30 },
+	[H6_RST_USB_PHY3] = { 0x0a7c, 30 },
 	[H6_RST_BUS_OHCI0] = { 0x0a8c, 16 },
 	[H6_RST_BUS_OHCI3] = { 0x0a8c, 19 },
 	[H6_RST_BUS_EHCI0] = { 0x0a8c, 20 },
@@ -853,9 +872,11 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
 };
 
 #define H6_R_RST_APB2_I2C	4
+#define H6_R_RST_APB2_RSB	7
 
 struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
 	[H6_R_RST_APB2_I2C] = { 0x019c, 16 },
+	[H6_R_RST_APB2_RSB] = { 0x01bc, 16 },
 };
 
 /* R40 */