From: jsg <jsg@openbsd.org>
Date: Tue, 11 Sep 2018 07:13:23 +0000 (+0000)
Subject: Add defines for amd microcode msrs which appear to be present since k8
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=e352df4c1c1d0ed1e78200e7440a13d0347b6dc5;p=openbsd

Add defines for amd microcode msrs which appear to be present since k8
though amd only provides public redistributable updates for >= family 10h.
---

diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index b276a53a939..b181afa1e19 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.80 2018/09/05 04:23:18 guenther Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.81 2018/09/11 07:13:23 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -504,6 +504,7 @@
 /*
  * AMD K8 (Opteron) MSRs.
  */
+#define	MSR_PATCH_LEVEL	0x0000008b
 #define	MSR_SYSCFG	0xc0000010
 
 #define MSR_EFER	0xc0000080	/* Extended feature enable */
@@ -521,6 +522,7 @@
 #define MSR_FSBASE	0xc0000100	/* 64bit offset for fs: */
 #define MSR_GSBASE	0xc0000101	/* 64bit offset for gs: */
 #define MSR_KERNELGSBASE 0xc0000102	/* storage for swapgs ins */
+#define MSR_PATCH_LOADER	0xc0010020
 #define MSR_INT_PEN_MSG	0xc0010055	/* Interrupt pending message */
 
 #define MSR_DE_CFG	0xc0011029	/* Decode Configuration */
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index edef12caf3d..81c9ef2240c 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.71 2018/08/23 14:47:52 jsg Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.72 2018/09/11 07:13:23 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -494,6 +494,7 @@
 /*
  * AMD K8 (Opteron) MSRs.
  */
+#define	MSR_PATCH_LEVEL	0x0000008b
 #define	MSR_SYSCFG	0xc0000010
 
 #define MSR_EFER	0xc0000080		/* Extended feature enable */
@@ -511,6 +512,7 @@
 #define MSR_FSBASE	0xc0000100		/* 64bit offset for fs: */
 #define MSR_GSBASE	0xc0000101		/* 64bit offset for gs: */
 #define MSR_KERNELGSBASE 0xc0000102		/* storage for swapgs ins */
+#define MSR_PATCH_LOADER 0xc0010020
 #define MSR_INT_PEN_MSG	0xc0010055		/* Interrupt pending message */
 
 #define MSR_DE_CFG	0xc0011029		/* Decode Configuration */