From: jsg Date: Mon, 11 Dec 2023 05:02:38 +0000 (+0000) Subject: drm/amdgpu: Force order between a read and write to the same address X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=d6cb9adac26e19ee7100ef91e9aceaf603b19d78;p=openbsd drm/amdgpu: Force order between a read and write to the same address From Alex Sierra c5cf436c8969516c92aaceb87582ff19bd187756 in linux-6.1.y/6.1.66 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 in mainline linux --- diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c index 3ebb51ca985..9f18ba9f5ff 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c @@ -82,6 +82,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); +static const struct soc15_reg_golden golden_settings_gc_11_0[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) +}; + static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), @@ -274,6 +278,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) default: break; } + soc15_program_register_sequence(adev, + golden_settings_gc_11_0, + (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); + } static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, diff --git a/sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h index c92c4b83253..4bff1ef8a9a 100644 --- a/sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h +++ b/sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h @@ -6369,6 +6369,8 @@ #define regTCP_INVALIDATE_BASE_IDX 1 #define regTCP_STATUS 0x19a1 #define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL 0x19a2 +#define regTCP_CNTL_BASE_IDX 1 #define regTCP_CNTL2 0x19a3 #define regTCP_CNTL2_BASE_IDX 1 #define regTCP_DEBUG_INDEX 0x19a5