From: brad Date: Mon, 1 Sep 2008 14:38:31 +0000 (+0000) Subject: Finish the rest... ATL2 -> LII X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=d0defdc392984983eb1580b60b9863e8769dcb7b;p=openbsd Finish the rest... ATL2 -> LII ok jsing@ --- diff --git a/sys/dev/pci/if_lii.c b/sys/dev/pci/if_lii.c index f0e9d59a04a..aab797a6840 100644 --- a/sys/dev/pci/if_lii.c +++ b/sys/dev/pci/if_lii.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_lii.c,v 1.16 2008/07/17 13:50:49 jsing Exp $ */ +/* $OpenBSD: if_lii.c,v 1.17 2008/09/01 14:38:31 brad Exp $ */ /* * Copyright (c) 2007 The NetBSD Foundation. @@ -67,8 +67,8 @@ #include -/*#define ATL2_DEBUG*/ -#ifdef ATL2_DEBUG +/*#define LII_DEBUG*/ +#ifdef LII_DEBUG #define DPRINTF(x) printf x #else #define DPRINTF(x) @@ -291,11 +291,11 @@ lii_reset(struct lii_softc *sc) DPRINTF(("lii_reset\n")); - LII_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); + LII_WRITE_4(sc, LII_SMC, SMC_SOFT_RST); DELAY(1000); for (i = 0; i < 10; ++i) { - if (LII_READ_4(sc, ATL2_BIS) == 0) + if (LII_READ_4(sc, LII_BIS) == 0) break; DELAY(1000); } @@ -305,7 +305,7 @@ lii_reset(struct lii_softc *sc) return 1; } - LII_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); + LII_WRITE_4(sc, LII_PHYC, PHYC_ENABLE); DELAY(10); /* Init PCI-Express module */ @@ -322,9 +322,9 @@ lii_eeprom_present(struct lii_softc *sc) { uint32_t val; - val = LII_READ_4(sc, ATL2_SFC); + val = LII_READ_4(sc, LII_SFC); if (val & SFC_EN_VPD) - LII_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); + LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD)); return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, NULL, NULL) == 1; @@ -368,21 +368,21 @@ lii_spi_configure(struct lii_softc *sc) * Why isn't WRDI used? Heck if I know. */ - LII_WRITE_1(sc, ATL2_SFOP_WRSR, + LII_WRITE_1(sc, LII_SFOP_WRSR, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); - LII_WRITE_1(sc, ATL2_SFOP_READ, + LII_WRITE_1(sc, LII_SFOP_READ, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); - LII_WRITE_1(sc, ATL2_SFOP_PROGRAM, + LII_WRITE_1(sc, LII_SFOP_PROGRAM, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); - LII_WRITE_1(sc, ATL2_SFOP_WREN, + LII_WRITE_1(sc, LII_SFOP_WREN, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); - LII_WRITE_1(sc, ATL2_SFOP_RDSR, + LII_WRITE_1(sc, LII_SFOP_RDSR, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); - LII_WRITE_1(sc, ATL2_SFOP_RDID, + LII_WRITE_1(sc, LII_SFOP_RDID, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); - LII_WRITE_1(sc, ATL2_SFOP_SC_ERASE, + LII_WRITE_1(sc, LII_SFOP_SC_ERASE, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); - LII_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, + LII_WRITE_1(sc, LII_SFOP_CHIP_ERASE, lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); } @@ -412,26 +412,26 @@ lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) uint32_t v; int i; - LII_WRITE_4(sc, ATL2_SF_DATA, 0); - LII_WRITE_4(sc, ATL2_SF_ADDR, reg); + LII_WRITE_4(sc, LII_SF_DATA, 0); + LII_WRITE_4(sc, LII_SF_ADDR, reg); v = SFC_WAIT_READY | MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); - LII_WRITE_4(sc, ATL2_SFC, v); + LII_WRITE_4(sc, LII_SFC, v); v |= SFC_START; - LII_WRITE_4(sc, ATL2_SFC, v); + LII_WRITE_4(sc, LII_SFC, v); for (i = 0; i < 10; ++i) { DELAY(1000); - if (!(LII_READ_4(sc, ATL2_SFC) & SFC_START)) + if (!(LII_READ_4(sc, LII_SFC) & SFC_START)) break; } if (i == 10) return EBUSY; - *val = LII_READ_4(sc, ATL2_SF_DATA); + *val = LII_READ_4(sc, LII_SF_DATA); return 0; } @@ -455,11 +455,11 @@ lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) val >>= 16; switch (val) { - case ATL2_MAC_ADDR_0: + case LII_MAC_ADDR_0: addr0 = val1; ++found; break; - case ATL2_MAC_ADDR_1: + case LII_MAC_ADDR_1: addr1 = val1; ++found; break; @@ -478,8 +478,8 @@ lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || (addr0 == 0 && (addr1 & 0xffff) == 0)) { - addr0 = htole32(LII_READ_4(sc, ATL2_MAC_ADDR_0)); - addr1 = htole32(LII_READ_4(sc, ATL2_MAC_ADDR_1)); + addr0 = htole32(LII_READ_4(sc, LII_MAC_ADDR_0)); + addr1 = htole32(LII_READ_4(sc, LII_MAC_ADDR_1)); } ea[0] = (addr1 & 0x0000ff00) >> 8; @@ -506,11 +506,11 @@ lii_mii_readreg(struct device *dev, int phy, int reg) val |= MDIOC_READ; - LII_WRITE_4(sc, ATL2_MDIOC, val); + LII_WRITE_4(sc, LII_MDIOC, val); for (i = 0; i < MDIO_WAIT_TIMES; ++i) { DELAY(2); - val = LII_READ_4(sc, ATL2_MDIOC); + val = LII_READ_4(sc, LII_MDIOC); if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) break; } @@ -538,11 +538,11 @@ lii_mii_writereg(struct device *dev, int phy, int reg, int data) /* val |= MDIOC_WRITE; */ - LII_WRITE_4(sc, ATL2_MDIOC, val); + LII_WRITE_4(sc, LII_MDIOC, val); for (i = 0; i < MDIO_WAIT_TIMES; ++i) { DELAY(2); - val = LII_READ_4(sc, ATL2_MDIOC); + val = LII_READ_4(sc, LII_MDIOC); if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) break; } @@ -561,14 +561,14 @@ lii_mii_statchg(struct device *dev) DPRINTF(("lii_mii_statchg\n")); - val = LII_READ_4(sc, ATL2_MACC); + val = LII_READ_4(sc, LII_MACC); if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) val |= MACC_FDX; else val &= ~MACC_FDX; - LII_WRITE_4(sc, ATL2_MACC, val); + LII_WRITE_4(sc, LII_MACC, val); } int @@ -609,23 +609,23 @@ lii_init(struct ifnet *ifp) memset(sc->sc_ring, 0, sc->sc_ringsize); /* Disable all interrupts */ - LII_WRITE_4(sc, ATL2_ISR, 0xffffffff); + LII_WRITE_4(sc, LII_ISR, 0xffffffff); - LII_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); + LII_WRITE_4(sc, LII_DESC_BASE_ADDR_HI, 0); /* XXX sc->sc_ringmap->dm_segs[0].ds_addr >> 32); */ - LII_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, + LII_WRITE_4(sc, LII_RXD_BASE_ADDR_LO, (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) + AT_RXD_PADDING); - LII_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, + LII_WRITE_4(sc, LII_TXS_BASE_ADDR_LO, sc->sc_txsp & 0xffffffff); - LII_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, + LII_WRITE_4(sc, LII_TXD_BASE_ADDR_LO, sc->sc_txdp & 0xffffffff); - LII_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); - LII_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); - LII_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); + LII_WRITE_2(sc, LII_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); + LII_WRITE_2(sc, LII_TXS_NUM_ENTRIES, AT_TXD_NUM); + LII_WRITE_2(sc, LII_RXD_NUM_ENTRIES, AT_RXD_NUM); /* * Inter Paket Gap Time = 0x60 (IPGT) @@ -633,7 +633,7 @@ lii_init(struct ifnet *ifp) * 64-bit Carrier-Sense window = 0x40 (IPGR1) * 96-bit IPG window = 0x60 (IPGR2) */ - LII_WRITE_4(sc, ATL2_MIPFG, 0x60405060); + LII_WRITE_4(sc, LII_MIPFG, 0x60405060); /* * Collision window = 0x37 (LCOL) @@ -641,40 +641,40 @@ lii_init(struct ifnet *ifp) * Maximum binary expansion # = 0xa (ABEBT) * IPG to start jam = 0x7 (JAMIPG) */ - LII_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | + LII_WRITE_4(sc, LII_MHDC, 0x07a0f037 | MHDC_EXC_DEF_EN); /* 100 means 200us */ - LII_WRITE_2(sc, ATL2_IMTIV, 100); - LII_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); + LII_WRITE_2(sc, LII_IMTIV, 100); + LII_WRITE_2(sc, LII_SMC, SMC_ITIMER_EN); /* 500000 means 100ms */ - LII_WRITE_2(sc, ATL2_IALTIV, 50000); + LII_WRITE_2(sc, LII_IALTIV, 50000); - LII_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN + LII_WRITE_4(sc, LII_MTU, ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); /* unit unknown for TX cur-through threshold */ - LII_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); + LII_WRITE_4(sc, LII_TX_CUT_THRESH, 0x177); - LII_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); - LII_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); + LII_WRITE_2(sc, LII_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); + LII_WRITE_2(sc, LII_PAUSE_OFF_TH, AT_RXD_NUM / 12); sc->sc_rxcur = 0; sc->sc_txs_cur = sc->sc_txs_ack = 0; sc->sc_txd_cur = sc->sc_txd_ack = 0; sc->sc_free_tx_slots = 1; - LII_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); - LII_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); + LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur); + LII_WRITE_2(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); - LII_WRITE_1(sc, ATL2_DMAR, DMAR_EN); - LII_WRITE_1(sc, ATL2_DMAW, DMAW_EN); + LII_WRITE_1(sc, LII_DMAR, DMAR_EN); + LII_WRITE_1(sc, LII_DMAW, DMAW_EN); - LII_WRITE_4(sc, ATL2_SMC, LII_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); + LII_WRITE_4(sc, LII_SMC, LII_READ_4(sc, LII_SMC) | SMC_MANUAL_INT); - error = ((LII_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); - LII_WRITE_4(sc, ATL2_ISR, 0x3fffffff); - LII_WRITE_4(sc, ATL2_ISR, 0); + error = ((LII_READ_4(sc, LII_ISR) & ISR_PHY_LINKDOWN) != 0); + LII_WRITE_4(sc, LII_ISR, 0x3fffffff); + LII_WRITE_4(sc, LII_ISR, 0); if (error) { printf("%s: init failed\n", DEVNAME(sc)); goto out; @@ -683,7 +683,7 @@ lii_init(struct ifnet *ifp) /* * Initialise MAC. */ - val = LII_READ_4(sc, ATL2_MACC) & MACC_FDX; + val = LII_READ_4(sc, LII_MACC) & MACC_FDX; val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | @@ -692,14 +692,14 @@ lii_init(struct ifnet *ifp) val |= 7 << MACC_PREAMBLE_LEN_SHIFT; val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; - LII_WRITE_4(sc, ATL2_MACC, val); + LII_WRITE_4(sc, LII_MACC, val); /* Program promiscuous mode and multicast filters. */ lii_iff(sc); mii_mediachg(&sc->sc_mii); - LII_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); + LII_WRITE_4(sc, LII_IMR, IMR_NORMAL_MASK); timeout_add(&sc->sc_tick, hz); @@ -791,7 +791,7 @@ lii_start(struct ifnet *ifp) if (sc->sc_txs_cur == sc->sc_txs_ack) sc->sc_free_tx_slots = 0; - LII_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); + LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur/4); IFQ_DEQUEUE(&ifp->if_snd, m0); @@ -817,7 +817,7 @@ lii_stop(struct ifnet *ifp) lii_reset(sc); - LII_WRITE_4(sc, ATL2_IMR, 0); + LII_WRITE_4(sc, LII_IMR, 0); } int @@ -826,14 +826,14 @@ lii_intr(void *v) struct lii_softc *sc = v; uint32_t status; - status = LII_READ_4(sc, ATL2_ISR); + status = LII_READ_4(sc, LII_ISR); if (status == 0) return 0; DPRINTF(("lii_intr (%x)\n", status)); /* Clear the interrupt and disable them */ - LII_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); + LII_WRITE_4(sc, LII_ISR, status | ISR_DIS_INT); if (status & (ISR_PHY | ISR_MANUAL)) { /* Ack PHY interrupt. Magic register */ @@ -848,7 +848,7 @@ lii_intr(void *v) } if (status & ISR_RX_EVENT) { -#ifdef ATL2_DEBUG +#ifdef LII_DEBUG if (!(status & ISR_RS_UPDATE)) printf("rxintr %08x\n", status); #endif @@ -859,7 +859,7 @@ lii_intr(void *v) lii_txintr(sc); /* Re-enable interrupts */ - LII_WRITE_4(sc, ATL2_ISR, 0); + LII_WRITE_4(sc, LII_ISR, 0); return 1; } @@ -883,7 +883,7 @@ lii_rxintr(struct lii_softc *sc) rxp->rxp_size, rxp->rxp_flags)); sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; rxp->rxp_update = 0; - if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { + if (!(rxp->rxp_flags & LII_RXF_SUCCESS)) { ++ifp->if_ierrors; continue; } @@ -917,7 +917,7 @@ lii_rxintr(struct lii_softc *sc) ether_input_mbuf(ifp, m); } - LII_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); + LII_WRITE_4(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); } void @@ -955,7 +955,7 @@ lii_txintr(struct lii_softc *sc) sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; - if (txs->txps_flags & ATL2_TXF_SUCCESS) + if (txs->txps_flags & LII_TXF_SUCCESS) ++ifp->if_opackets; else ++ifp->if_oerrors; @@ -1115,7 +1115,7 @@ lii_iff(struct lii_softc *sc) uint32_t hashes[2] = { 0, 0 }; uint32_t crc, val; - val = LII_READ_4(sc, ATL2_MACC); + val = LII_READ_4(sc, LII_MACC); val &= ~(MACC_PROMISC_EN | MACC_ALLMULTI_EN); ifp->if_flags &= ~IFF_ALLMULTI; @@ -1127,8 +1127,8 @@ lii_iff(struct lii_softc *sc) val |= MACC_ALLMULTI_EN; } else { /* Clear multicast hash table. */ - LII_WRITE_4(sc, ATL2_MHT, 0); - LII_WRITE_4(sc, ATL2_MHT + 4, 0); + LII_WRITE_4(sc, LII_MHT, 0); + LII_WRITE_4(sc, LII_MHT + 4, 0); /* Calculate multicast hashes. */ ETHER_FIRST_MULTI(step, ac, enm); @@ -1143,10 +1143,10 @@ lii_iff(struct lii_softc *sc) } /* Write new hashes to multicast hash table. */ - LII_WRITE_4(sc, ATL2_MHT, hashes[0]); - LII_WRITE_4(sc, ATL2_MHT + 4, hashes[1]); + LII_WRITE_4(sc, LII_MHT, hashes[0]); + LII_WRITE_4(sc, LII_MHT + 4, hashes[1]); - LII_WRITE_4(sc, ATL2_MACC, val); + LII_WRITE_4(sc, LII_MACC, val); } void diff --git a/sys/dev/pci/if_liireg.h b/sys/dev/pci/if_liireg.h index 4759307fe33..bca8b156a8f 100644 --- a/sys/dev/pci/if_liireg.h +++ b/sys/dev/pci/if_liireg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_liireg.h,v 1.3 2008/07/17 13:50:49 jsing Exp $ */ +/* $OpenBSD: if_liireg.h,v 1.4 2008/09/01 14:38:31 brad Exp $ */ /* * Copyright (c) 2007 The NetBSD Foundation. @@ -32,7 +32,7 @@ */ /* SPI Flash Control register */ -#define ATL2_SFC 0x0200 +#define LII_SFC 0x0200 #define SFC_STS_NON_RDY 0x00000001 #define SFC_STS_WEN 0x00000002 #define SFC_STS_WPEN 0x00000080 @@ -58,13 +58,13 @@ #define SFC_WAIT_READY 0x10000000 /* SPI Flash Address register */ -#define ATL2_SF_ADDR 0x0204 +#define LII_SF_ADDR 0x0204 /* SPI Flash Data register */ -#define ATL2_SF_DATA 0x0208 +#define LII_SF_DATA 0x0208 /* SPI Flash Configuration register */ -#define ATL2_SFCF 0x020c +#define LII_SFCF 0x020c #define SFCF_LD_ADDR_MASK 0x00ffffff #define SFCF_LD_ADDR_SHIFT 0 #define SFCF_VPD_ADDR_MASK 0x03 @@ -72,17 +72,17 @@ #define SFCF_LD_EXISTS 0x04000000 /* SPI Flash op codes programmation registers */ -#define ATL2_SFOP_PROGRAM 0x0210 -#define ATL2_SFOP_SC_ERASE 0x0211 -#define ATL2_SFOP_CHIP_ERASE 0x0212 -#define ATL2_SFOP_RDID 0x0213 -#define ATL2_SFOP_WREN 0x0214 -#define ATL2_SFOP_RDSR 0x0215 -#define ATL2_SFOP_WRSR 0x0216 -#define ATL2_SFOP_READ 0x0217 +#define LII_SFOP_PROGRAM 0x0210 +#define LII_SFOP_SC_ERASE 0x0211 +#define LII_SFOP_CHIP_ERASE 0x0212 +#define LII_SFOP_RDID 0x0213 +#define LII_SFOP_WREN 0x0214 +#define LII_SFOP_RDSR 0x0215 +#define LII_SFOP_WRSR 0x0216 +#define LII_SFOP_READ 0x0217 /* TWSI Control register, whatever that is */ -#define ATL2_TWSIC 0x0218 +#define LII_TWSIC 0x0218 #define TWSIC_LD_OFFSET_MASK 0x000000ff #define TWSIC_LD_OFFSET_SHIFT 0 #define TWSIC_LD_SLV_ADDR_MASK 0x07 @@ -102,7 +102,7 @@ #define TWSIC_WRITE_FREQ_SEL_SHIFT 24 /* PCI-Express Device Misc. Control register? (size unknown) */ -#define ATL2_PCEDMC 0x021c +#define LII_PCEDMC 0x021c #define PCEDMC_RETRY_BUFDIS 0x01 #define PCEDMC_EXT_PIPE 0x02 #define PCEDMC_SPIROM_EXISTS 0x04 @@ -110,11 +110,11 @@ #define PCEDMC_SERDES_SEL_DIN 0x10 /* PCI-Express PHY Miscellaneous register (size unknown) */ -#define ATL2_PCEPM 0x1000 +#define LII_PCEPM 0x1000 #define PCEPM_FORCE_RCV_DET 0x04 /* Selene Master Control register */ -#define ATL2_SMC 0x1400 +#define LII_SMC 0x1400 #define SMC_SOFT_RST 0x00000001 #define SMC_MTIMER_EN 0x00000002 #define SMC_ITIMER_EN 0x00000004 @@ -125,29 +125,29 @@ #define SMC_DEV_ID_SHIFT 24 /* Timer Initial Value register */ -#define ATL2_TIV 0x1404 +#define LII_TIV 0x1404 /* IRQ Moderator Timer Initial Value register */ -#define ATL2_IMTIV 0x1408 +#define LII_IMTIV 0x1408 /* PHY Control register */ -#define ATL2_PHYC 0x140c +#define LII_PHYC 0x140c #define PHYC_ENABLE 0x0001 /* IRQ Anti-Lost Timer Initial Value register --> Time allowed for software to clear the interrupt */ -#define ATL2_IALTIV 0x140e +#define LII_IALTIV 0x140e /* Block Idle Status register --> Bit set if matching state machine is not idle */ -#define ATL2_BIS 0x1410 +#define LII_BIS 0x1410 #define BIS_RXMAC 0x00000001 #define BIS_TXMAC 0x00000002 #define BIS_DMAR 0x00000004 #define BIS_DMAW 0x00000008 /* MDIO Control register */ -#define ATL2_MDIOC 0x1414 +#define LII_MDIOC 0x1414 #define MDIOC_DATA_MASK 0x0000ffff #define MDIOC_DATA_SHIFT 0 #define MDIOC_REG_MASK 0x1f @@ -170,12 +170,12 @@ #define MDIO_WAIT_TIMES 10 /* SerDes Lock Detect Control and Status register */ -#define ATL2_SERDES 0x1424 +#define LII_SERDES 0x1424 #define SERDES_LOCK_DETECT 0x01 #define SERDES_LOCK_DETECT_EN 0x02 /* MAC Control register */ -#define ATL2_MACC 0x1480 +#define LII_MACC 0x1480 #define MACC_TX_EN 0x00000001 #define MACC_RX_EN 0x00000002 #define MACC_TX_FLOW_EN 0x00000004 @@ -196,7 +196,7 @@ #define MACC_HDX_LEFT_BUF_SHIFT 28 /* MAC IPG/IFG Control register */ -#define ATL2_MIPFG 0x1484 +#define LII_MIPFG 0x1484 #define MIPFG_IPGT_MASK 0x0000007f #define MIPFG_IPGT_SHIFT 0 #define MIPFG_MIFG_MASK 0xff @@ -207,14 +207,14 @@ #define MIPFG_IPGR2_SHIFT 24 /* MAC Address registers */ -#define ATL2_MAC_ADDR_0 0x1488 -#define ATL2_MAC_ADDR_1 0x148c +#define LII_MAC_ADDR_0 0x1488 +#define LII_MAC_ADDR_1 0x148c /* Multicast Hash Table register */ -#define ATL2_MHT 0x1490 +#define LII_MHT 0x1490 /* MAC Half-Duplex Control register */ -#define ATL2_MHDC 0x1498 +#define LII_MHDC 0x1498 #define MHDC_LCOL_MASK 0x000003ff #define MHDC_LCOL_SHIFT 0 #define MHDC_RETRY_MASK 0x0f @@ -229,10 +229,10 @@ #define MHDC_JAMIPG_SHIFT 24 /* MTU Control register */ -#define ATL2_MTU 0x149c +#define LII_MTU 0x149c /* WOL Control register */ -#define ATL2_WOLC +#define LII_WOLC #define WOLC_PATTERN_EN 0x00000001 #define WOLC_PATTERN_PME_EN 0x00000002 #define WOLC_MAGIC_EN 0x00000004 @@ -254,39 +254,39 @@ #define WOLC_PT4_MATCH 0x10000000 /* Internal SRAM Partition register */ -#define ATL2_SRAM_TXRAM_END 0x1500 -#define ATL2_SRAM_RXRAM_END 0x1502 +#define LII_SRAM_TXRAM_END 0x1500 +#define LII_SRAM_RXRAM_END 0x1502 /* Descriptor Control registers */ -#define ATL2_DESC_BASE_ADDR_HI 0x1540 -#define ATL2_TXD_BASE_ADDR_LO 0x1544 -#define ATL2_TXD_BUFFER_SIZE 0x1548 -#define ATL2_TXS_BASE_ADDR_LO 0x154c -#define ATL2_TXS_NUM_ENTRIES 0x1550 -#define ATL2_RXD_BASE_ADDR_LO 0x1554 -#define ATL2_RXD_NUM_ENTRIES 0x1558 +#define LII_DESC_BASE_ADDR_HI 0x1540 +#define LII_TXD_BASE_ADDR_LO 0x1544 +#define LII_TXD_BUFFER_SIZE 0x1548 +#define LII_TXS_BASE_ADDR_LO 0x154c +#define LII_TXS_NUM_ENTRIES 0x1550 +#define LII_RXD_BASE_ADDR_LO 0x1554 +#define LII_RXD_NUM_ENTRIES 0x1558 /* DMAR Control register */ -#define ATL2_DMAR 0x1580 +#define LII_DMAR 0x1580 #define DMAR_EN 0x01 /* TX Cur-Through Control register */ -#define ATL2_TX_CUT_THRESH 0x1590 +#define LII_TX_CUT_THRESH 0x1590 /* DMAW Control register */ -#define ATL2_DMAW 0x15a0 +#define LII_DMAW 0x15a0 #define DMAW_EN 0x01 /* Flow Control registers */ -#define ATL2_PAUSE_ON_TH 0x15a8 -#define ATL2_PAUSE_OFF_TH 0x15aa +#define LII_PAUSE_ON_TH 0x15a8 +#define LII_PAUSE_OFF_TH 0x15aa /* Mailbox registers */ -#define ATL2_MB_TXD_WR_IDX 0x15f0 -#define ATL2_MB_RXD_RD_IDX 0x15f4 +#define LII_MB_TXD_WR_IDX 0x15f0 +#define LII_MB_RXD_RD_IDX 0x15f4 /* Interrupt Status register */ -#define ATL2_ISR 0x1600 +#define LII_ISR 0x1600 #define ISR_TIMER 0x00000001 #define ISR_MANUAL 0x00000002 #define ISR_RXF_OV 0x00000004 @@ -316,56 +316,56 @@ ISR_HOST_RXD_OV | ISR_RS_UPDATE) /* Interrupt Mask register */ -#define ATL2_IMR 0x1604 +#define LII_IMR 0x1604 #define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \ ISR_PHY | ISR_PHY_LINKDOWN | \ ISR_TS_UPDATE | ISR_RS_UPDATE) /* MAC RX Statistics registers */ -#define ATL2_STS_RX_PAUSE 0x1700 -#define ATL2_STS_RXD_OV 0x1704 -#define ATL2_STS_RXS_OV 0x1708 -#define ATL2_STS_RX_FILTER 0x170c +#define LII_STS_RX_PAUSE 0x1700 +#define LII_STS_RXD_OV 0x1704 +#define LII_STS_RXS_OV 0x1708 +#define LII_STS_RX_FILTER 0x170c struct tx_pkt_header { uint16_t txph_size; -#define ATL2_TXH_ADD_VLAN_TAG 0x8000 +#define LII_TXH_ADD_VLAN_TAG 0x8000 uint16_t txph_vlan; } __packed; struct tx_pkt_status { uint16_t txps_size; uint16_t txps_flags :15; -#define ATL2_TXF_SUCCESS 0x0001 -#define ATL2_TXF_BCAST 0x0002 -#define ATL2_TXF_MCAST 0x0004 -#define ATL2_TXF_PAUSE 0x0008 -#define ATL2_TXF_CTRL 0x0010 -#define ATL2_TXF_DEFER 0x0020 -#define ATL2_TXF_EXC_DEFER 0x0040 -#define ATL2_TXF_SINGLE_COL 0x0080 -#define ATL2_TXF_MULTI_COL 0x0100 -#define ATL2_TXF_LATE_COL 0x0200 -#define ATL2_TXF_ABORT_COL 0x0400 -#define ATL2_TXF_UNDERRUN 0x0800 +#define LII_TXF_SUCCESS 0x0001 +#define LII_TXF_BCAST 0x0002 +#define LII_TXF_MCAST 0x0004 +#define LII_TXF_PAUSE 0x0008 +#define LII_TXF_CTRL 0x0010 +#define LII_TXF_DEFER 0x0020 +#define LII_TXF_EXC_DEFER 0x0040 +#define LII_TXF_SINGLE_COL 0x0080 +#define LII_TXF_MULTI_COL 0x0100 +#define LII_TXF_LATE_COL 0x0200 +#define LII_TXF_ABORT_COL 0x0400 +#define LII_TXF_UNDERRUN 0x0800 uint16_t txps_update:1; } __packed; struct rx_pkt { uint16_t rxp_size; uint16_t rxp_flags :15; -#define ATL2_RXF_SUCCESS 0x0001 -#define ATL2_RXF_BCAST 0x0002 -#define ATL2_RXF_MCAST 0x0004 -#define ATL2_RXF_PAUSE 0x0008 -#define ATL2_RXF_CTRL 0x0010 -#define ATL2_RXF_CRC 0x0020 -#define ATL2_RXF_CODE 0x0040 -#define ATL2_RXF_RUNT 0x0080 -#define ATL2_RXF_FRAG 0x0100 -#define ATL2_RXF_TRUNC 0x0200 -#define ATL2_RXF_ALIGN 0x0400 -#define ATL2_RXF_VLAN 0x0800 +#define LII_RXF_SUCCESS 0x0001 +#define LII_RXF_BCAST 0x0002 +#define LII_RXF_MCAST 0x0004 +#define LII_RXF_PAUSE 0x0008 +#define LII_RXF_CTRL 0x0010 +#define LII_RXF_CRC 0x0020 +#define LII_RXF_CODE 0x0040 +#define LII_RXF_RUNT 0x0080 +#define LII_RXF_FRAG 0x0100 +#define LII_RXF_TRUNC 0x0200 +#define LII_RXF_ALIGN 0x0400 +#define LII_RXF_VLAN 0x0800 uint16_t rxp_update:1; uint16_t rxp_vlan; uint16_t __pad;