From: jsg <jsg@openbsd.org>
Date: Tue, 21 Aug 2018 12:44:13 +0000 (+0000)
Subject: print rdtscp and xsave_ext cpuid bits on i386 as well
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=d050ae834cf213ab8caaef9b4572b2f6f18c85b8;p=openbsd

print rdtscp and xsave_ext cpuid bits on i386 as well
move printing of ecxfeatures bits to match amd64
---

diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index cbd2bfd68d7..57dfb38289f 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.624 2018/08/21 06:03:34 jsg Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.625 2018/08/21 12:44:13 jsg Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -989,6 +989,7 @@ const struct cpu_cpuid_feature i386_ecpuid_features[] = {
 	{ CPUID_MMXX,		"MMXX" },
 	{ CPUID_FFXSR,		"FFXSR" },
 	{ CPUID_PAGE1GB,	"PAGE1GB" },
+	{ CPUID_RDTSCP,		"RDTSCP" },
 	{ CPUID_LONG,		"LONG" },
 	{ CPUID_3DNOW2,		"3DNOW2" },
 	{ CPUID_3DNOW,		"3DNOW" }
@@ -1117,6 +1118,13 @@ const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = {
 	{ CPUIDEDX_ITSC,	"ITSC" },
 };
 
+const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = {
+	{ XSAVE_XSAVEOPT,	"XSAVEOPT" },
+	{ XSAVE_XSAVEC,		"XSAVEC" },
+	{ XSAVE_XGETBV1,	"XGETBV1" },
+	{ XSAVE_XSAVES,		"XSAVES" },
+};
+
 void
 winchip_cpu_setup(struct cpu_info *ci)
 {
@@ -1950,14 +1958,6 @@ identifycpu(struct cpu_info *ci)
 				numbits++;
 			}
 		}
-		for (i = 0; i < nitems(i386_ecpuid_features); i++) {
-			if (ecpu_feature &
-			    i386_ecpuid_features[i].feature_bit) {
-				printf("%s%s", (numbits == 0 ? "" : ","),
-				    i386_ecpuid_features[i].feature_name);
-				numbits++;
-			}
-		}
 		max = sizeof(i386_cpuid_ecxfeatures)
 			/ sizeof(i386_cpuid_ecxfeatures[0]);
 		for (i = 0; i < max; i++) {
@@ -1968,6 +1968,14 @@ identifycpu(struct cpu_info *ci)
 				numbits++;
 			}
 		}
+		for (i = 0; i < nitems(i386_ecpuid_features); i++) {
+			if (ecpu_feature &
+			    i386_ecpuid_features[i].feature_bit) {
+				printf("%s%s", (numbits == 0 ? "" : ","),
+				    i386_ecpuid_features[i].feature_name);
+				numbits++;
+			}
+		}
 		for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) {
 			if (ecpu_ecxfeature &
 			    i386_ecpuid_ecxfeatures[i].feature_bit) {
@@ -2034,6 +2042,17 @@ identifycpu(struct cpu_info *ci)
 					printf(",%s", cpu_tpm_eaxfeatures[i].feature_name);
 		}
 
+		/* xsave subfeatures */
+		if (cpuid_level >= 0xd) {
+			uint32_t dummy, val;
+
+			CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy);
+			for (i = 0; i < nitems(cpu_xsave_extfeatures); i++)
+				if (val & cpu_xsave_extfeatures[i].feature_bit)
+					printf(",%s",
+					    cpu_xsave_extfeatures[i].feature_name);
+		}
+
 		if (cpu_meltdown)
 			printf(",MELTDOWN");
 
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 04fbecd3d62..d9d61910933 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.69 2018/08/15 02:07:35 jsg Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.70 2018/08/21 12:44:13 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -252,6 +252,7 @@
 #define	CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
 #define	CPUID_FFXSR	0x02000000	/* fast FP/MMX save/restore */
 #define	CPUID_PAGE1GB	0x04000000	/* 1-GByte pages */
+#define	CPUID_RDTSCP	0x08000000	/* RDTSCP / IA32_TSC_AUX available */
 #define	CPUID_LONG	0x20000000	/* long mode */
 #define	CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
 #define	CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
@@ -292,6 +293,19 @@
 
 #define CPUIDEDX_ITSC		(1 << 8)	/* Invariant TSC */
 
+/*
+ * AMD CPUID function 0x80000008 EBX bits
+ */
+#define CPUIDEBX_IBPB		(1ULL << 12)	/* Speculation Control IBPB */
+#define CPUIDEBX_IBRS		(1ULL << 14)	/* Speculation Control IBRS */
+#define CPUIDEBX_STIBP		(1ULL << 15)	/* Speculation Control STIBP */
+#define CPUIDEBX_IBRS_ALWAYSON	(1ULL << 16)	/* IBRS always on mode */
+#define CPUIDEBX_STIBP_ALWAYSON	(1ULL << 17)	/* STIBP always on mode */
+#define CPUIDEBX_IBRS_PREF	(1ULL << 18)	/* IBRS preferred */
+#define CPUIDEBX_SSBD		(1ULL << 24)	/* Speculation Control SSBD */
+#define CPUIDEBX_VIRT_SSBD	(1ULL << 25)	/* Virt Spec Control SSBD */
+#define CPUIDEBX_SSBD_NOTREQ	(1ULL << 26)	/* SSBD not required */
+
 #define	CPUID2FAMILY(cpuid)	(((cpuid) >> 8) & 15)
 #define	CPUID2MODEL(cpuid)	(((cpuid) >> 4) & 15)
 #define	CPUID2STEPPING(cpuid)	((cpuid) & 15)
@@ -1225,3 +1239,10 @@
 #define PAT_WB          0x6UL
 #define PAT_UCMINUS     0x7UL
 
+/*
+ * XSAVE subfeatures (cpuid 0xd, leaf 1)
+ */
+#define XSAVE_XSAVEOPT		0x1UL
+#define XSAVE_XSAVEC		0x2UL
+#define XSAVE_XGETBV1		0x4UL
+#define XSAVE_XSAVES		0x8UL