From: jsg Date: Fri, 7 Jul 2023 03:50:46 +0000 (+0000) Subject: regen X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=cbd2bc799b68390eb5d67e9f91ca9cd9602130b4;p=openbsd regen --- diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h index 3a14e52774c..86e15ada95e 100644 --- a/sys/dev/pci/pcidevs.h +++ b/sys/dev/pci/pcidevs.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.2041 2023/06/29 07:58:15 jsg Exp + * OpenBSD: pcidevs,v 1.2042 2023/07/07 03:50:02 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -6954,6 +6954,7 @@ #define PCI_PRODUCT_INTEL_RPL_U_HB_3 0xa71c /* Core 13G Host */ #define PCI_PRODUCT_INTEL_RPL_DTT 0xa71d /* Core 13G DTT */ #define PCI_PRODUCT_INTEL_RPL_XHCI 0xa71e /* Core 13G xHCI */ +#define PCI_PRODUCT_INTEL_RPL_TBT_PCIE3 0xa71f /* Core 13G PCIE */ #define PCI_PRODUCT_INTEL_RPL_P_GT_1 0xa720 /* Graphics */ #define PCI_PRODUCT_INTEL_RPL_P_GT_2 0xa721 /* Graphics */ #define PCI_PRODUCT_INTEL_RPL_HX_HB_4 0xa728 /* Core 13G Host */ @@ -6962,6 +6963,7 @@ #define PCI_PRODUCT_INTEL_RPL_PCIE_2 0xa72d /* Core 13G PCIE */ #define PCI_PRODUCT_INTEL_RPL_TBT_PCIE2 0xa72f /* Core 13G PCIE */ #define PCI_PRODUCT_INTEL_RPL_TBT_DMA0 0xa73e /* Core 13G TBT */ +#define PCI_PRODUCT_INTEL_RPL_TBT_PCIE1 0xa73f /* Core 13G PCIE */ #define PCI_PRODUCT_INTEL_RPL_PCIE_3 0xa74d /* Core 13G PCIE */ #define PCI_PRODUCT_INTEL_RPL_GNA 0xa74f /* Core 13G GNA */ #define PCI_PRODUCT_INTEL_RPL_IPU 0xa75d /* Core 13G IPU */ diff --git a/sys/dev/pci/pcidevs_data.h b/sys/dev/pci/pcidevs_data.h index 88740c36a83..a8beb1ea57a 100644 --- a/sys/dev/pci/pcidevs_data.h +++ b/sys/dev/pci/pcidevs_data.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.2041 2023/06/29 07:58:15 jsg Exp + * OpenBSD: pcidevs,v 1.2042 2023/07/07 03:50:02 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -25171,6 +25171,10 @@ static const struct pci_known_product pci_known_products[] = { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_XHCI, "Core 13G xHCI", }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_TBT_PCIE3, + "Core 13G PCIE", + }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_P_GT_1, "Graphics", @@ -25203,6 +25207,10 @@ static const struct pci_known_product pci_known_products[] = { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_TBT_DMA0, "Core 13G TBT", }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_TBT_PCIE1, + "Core 13G PCIE", + }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_PCIE_3, "Core 13G PCIE",