From: visa <visa@openbsd.org>
Date: Sat, 24 Feb 2018 11:42:30 +0000 (+0000)
Subject: Declare ci_ipl volatile to prevent the compiler from optimizing
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=cb5217fba3727742f326b0c20baed47113c0e1ef;p=openbsd

Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
removal of the explicit noreorder/reorder toggles from the C code.

With ci_ipl being volatile, drop mips_sync() calls that follow
the accesses of the variable. The sync is redundant as a compiler
barrier. In addition, the MIPS64 CPU designs should not need the
sync for pipeline or write buffer control. According to miod@,
the use of the instruction is a carryover from code targeting
early MIPS designs that lack tight integration with the cache
and write buffer.

Discussed with and testing help from miod@.
Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000,
R4400, R8000, R10000 and R16000.
---

diff --git a/sys/arch/loongson/dev/bonito.c b/sys/arch/loongson/dev/bonito.c
index 70aa60ff798..c0107540eef 100644
--- a/sys/arch/loongson/dev/bonito.c
+++ b/sys/arch/loongson/dev/bonito.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bonito.c,v 1.33 2017/05/17 11:52:25 visa Exp $	*/
+/*	$OpenBSD: bonito.c,v 1.34 2018/02/24 11:42:30 visa Exp $	*/
 /*	$NetBSD: bonito_mainbus.c,v 1.11 2008/04/28 20:23:10 martin Exp $	*/
 /*	$NetBSD: bonito_pci.c,v 1.5 2008/04/28 20:23:28 martin Exp $	*/
 
@@ -483,10 +483,7 @@ bonito_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 
 	/* Update masks to new ipl. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 	bonito_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
@@ -704,10 +701,7 @@ bonito_intr_dispatch(uint64_t isr, int startbit, struct trapframe *frame)
 					rc = 1;
 					ih->ih_count.ec_count++;
 				}
-				__asm__ (".set noreorder\n");
 				curcpu()->ci_ipl = frame->ipl;
-				mips_sync();
-				__asm__ (".set reorder\n");
 			}
 			if (rc == 0) {
 				printf("spurious interrupt %d\n", bitno);
diff --git a/sys/arch/loongson/loongson/generic2e_machdep.c b/sys/arch/loongson/loongson/generic2e_machdep.c
index aa16917f7d9..cd22d5b5cce 100644
--- a/sys/arch/loongson/loongson/generic2e_machdep.c
+++ b/sys/arch/loongson/loongson/generic2e_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: generic2e_machdep.c,v 1.9 2017/04/30 16:45:45 mpi Exp $	*/
+/*	$OpenBSD: generic2e_machdep.c,v 1.10 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2010 Miodrag Vallat.
@@ -290,10 +290,8 @@ generic2e_isa_intr(uint32_t hwpend, struct trapframe *frame)
 				ih->ih_count.ec_count++;
 			}
 
-			__asm__ (".set noreorder\n");
 			curcpu()->ci_ipl = frame->ipl;
-			mips_sync();
-			__asm__ (".set reorder\n");
+
 			if (ret == 1)
 				break;
 		}
diff --git a/sys/arch/loongson/loongson/isa_machdep.c b/sys/arch/loongson/loongson/isa_machdep.c
index 18bd4dd37c3..b43bc06a184 100644
--- a/sys/arch/loongson/loongson/isa_machdep.c
+++ b/sys/arch/loongson/loongson/isa_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: isa_machdep.c,v 1.3 2012/09/29 19:24:31 miod Exp $	*/
+/*	$OpenBSD: isa_machdep.c,v 1.4 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -86,10 +86,7 @@ loongson_isa_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 
 	/* Update masks to new ipl. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 	loongson_isa_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
diff --git a/sys/arch/loongson/loongson/loongson3_intr.c b/sys/arch/loongson/loongson/loongson3_intr.c
index a94dd425a69..8d07fe4beab 100644
--- a/sys/arch/loongson/loongson/loongson3_intr.c
+++ b/sys/arch/loongson/loongson/loongson3_intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: loongson3_intr.c,v 1.6 2018/01/23 14:47:21 visa Exp $	*/
+/*	$OpenBSD: loongson3_intr.c,v 1.7 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2016 Visa Hankala
@@ -73,18 +73,6 @@ next_irq(uint32_t *isr)
 	return irq;
 }
 
-static inline void
-setipl(struct cpu_info *ci, int newipl)
-{
-	asm volatile (
-	"	.set push\n"
-	"	.set noreorder\n");
-	ci->ci_ipl = newipl;
-	mips_sync();
-	asm volatile (
-	"	.set pop\n");
-}
-
 void
 loongson3_intr_init(void)
 {
@@ -361,7 +349,7 @@ loongson3_splx(int newipl)
 {
 	struct cpu_info *ci = curcpu();
 
-	setipl(ci, newipl);
+	ci->ci_ipl = newipl;
 
 	if (CPU_IS_PRIMARY(ci))
 		REGVAL(LS3_IRT_INTENSET(0)) =
@@ -436,7 +424,7 @@ loongson3_intr(uint32_t pending, struct trapframe *frame)
 			printf("spurious interrupt %d\n", irq);
 	}
 
-	setipl(ci, ipl);
+	ci->ci_ipl = ipl;
 
 	/* Re-enable processed interrupts. */
 	REGVAL(LS3_IRT_INTENSET(0)) = imr;
@@ -516,7 +504,7 @@ loongson3_ht_intr(uint32_t pending, struct trapframe *frame)
 		loongson3_ht_pic->pic_eoi(irq);
 	}
 
-	setipl(ci, ipl);
+	ci->ci_ipl = ipl;
 
 	/* Re-enable HT interrupts. */
 	REGVAL(LS3_IRT_INTENSET(0)) = 1u << LS3_IRQ_HT1(0);
diff --git a/sys/arch/loongson/loongson/yeeloong_machdep.c b/sys/arch/loongson/loongson/yeeloong_machdep.c
index 5dab0e02181..aadbf41ca1f 100644
--- a/sys/arch/loongson/loongson/yeeloong_machdep.c
+++ b/sys/arch/loongson/loongson/yeeloong_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: yeeloong_machdep.c,v 1.26 2017/05/23 16:53:15 visa Exp $	*/
+/*	$OpenBSD: yeeloong_machdep.c,v 1.27 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -409,10 +409,7 @@ lemote_isa_intr(uint32_t hwpend, struct trapframe *frame)
 						rc = 1;
 						ih->ih_count.ec_count++;
 					}
-					__asm__ (".set noreorder\n");
 					curcpu()->ci_ipl = frame->ipl;
-					mips_sync();
-					__asm__ (".set reorder\n");
 					if (ret == 1)
 						break;
 				}
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index e0ba146a4c9..28d81151a4d 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.123 2018/01/29 14:53:01 visa Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.124 2018/02/24 11:42:31 visa Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -188,7 +188,7 @@ struct cpu_info {
 	int		ci_want_resched;	/* need_resched() invoked */
 	cpuid_t		ci_cpuid;		/* our CPU ID */
 	uint32_t	ci_randseed;		/* per cpu random seed */
-	int		ci_ipl;			/* software IPL */
+	volatile int	ci_ipl;			/* software IPL */
 	uint32_t	ci_softpending;		/* pending soft interrupts */
 	int		ci_clock_started;
 	u_int32_t	ci_cpu_counter_last;	/* last compare value loaded */
diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c
index ca5d709626b..1c8ab786044 100644
--- a/sys/arch/mips64/mips64/interrupt.c
+++ b/sys/arch/mips64/mips64/interrupt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: interrupt.c,v 1.68 2017/06/11 10:01:23 visa Exp $ */
+/*	$OpenBSD: interrupt.c,v 1.69 2018/02/24 11:42:31 visa Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -140,10 +140,7 @@ interrupt(struct trapframe *trapframe)
 	if (ci->ci_ipl < IPL_SOFTINT && ci->ci_softpending != 0) {
 		s = splsoft();
 		dosoftint();
-		__asm__ (".set noreorder\n");
 		ci->ci_ipl = s;	/* no-overhead splx */
-		mips_sync();
-		__asm__ (".set reorder\n");
 	}
 
 	ci->ci_intrdepth--;
@@ -233,15 +230,9 @@ splraise(int newipl)
 	struct cpu_info *ci = curcpu();
         int oldipl;
 
-	__asm__ (".set noreorder\n");
 	oldipl = ci->ci_ipl;
-	if (oldipl < newipl) {
-		/* XXX to kill warning about dla being used in a delay slot */
-		__asm__("nop");
+	if (oldipl < newipl)
 		ci->ci_ipl = newipl;
-	}
-	mips_sync();
-	__asm__ (".set reorder\n");
 	return oldipl;
 }
 
diff --git a/sys/arch/octeon/dev/octcit.c b/sys/arch/octeon/dev/octcit.c
index 785cafa4019..06b79b1b2b4 100644
--- a/sys/arch/octeon/dev/octcit.c
+++ b/sys/arch/octeon/dev/octcit.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octcit.c,v 1.5 2018/01/23 14:47:21 visa Exp $	*/
+/*	$OpenBSD: octcit.c,v 1.6 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2017 Visa Hankala
@@ -404,10 +404,7 @@ octcit_intr(uint32_t hwpend, struct trapframe *frame)
 	if (!ISSET(destpp, CIU3_DEST_PP_INT_INTR))
 		goto spurious;
 
-	__asm__ (".set noreorder\n");
 	ipl = ci->ci_ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	intsn = (destpp & CIU3_DEST_PP_INT_INTSN) >>
 	    CIU3_DEST_PP_INT_INTSN_SHIFT;
@@ -458,10 +455,7 @@ octcit_intr(uint32_t hwpend, struct trapframe *frame)
 			break;
 	}
 
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 spurious:
 	if (handled == 0)
@@ -478,11 +472,7 @@ octcit_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 	unsigned int core = ci->ci_cpuid;
 
-	/* Update IPL. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	if (newipl < sc->sc_minipl[ci->ci_cpuid])
 		CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 1ul << core);
diff --git a/sys/arch/octeon/dev/octciu.c b/sys/arch/octeon/dev/octciu.c
index 6014d069cd1..c26c4005c48 100644
--- a/sys/arch/octeon/dev/octciu.c
+++ b/sys/arch/octeon/dev/octciu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octciu.c,v 1.9 2018/01/23 14:47:21 visa Exp $	*/
+/*	$OpenBSD: octciu.c,v 1.10 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2000-2004 Opsycon AB  (www.opsycon.se)
@@ -462,10 +462,7 @@ octciu_intr_bank(struct octciu_softc *sc, struct intrbank *bank,
 	 * Now process allowed interrupts.
 	 */
 
-	__asm__ (".set noreorder\n");
 	ipl = ci->ci_ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	while ((irq = octciu_next_irq(&isr)) >= 0) {
 		irq += bank->id * BANK_SIZE;
@@ -500,10 +497,7 @@ octciu_intr_bank(struct octciu_softc *sc, struct intrbank *bank,
 			printf("spurious interrupt %d\n", irq);
 	}
 
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	/*
 	 * Reenable interrupts which have been serviced.
@@ -543,11 +537,7 @@ octciu_splx(int newipl)
 	struct octciu_softc *sc = octciu_sc;
 	struct octciu_cpu *scpu = &sc->sc_cpu[ci->ci_cpuid];
 
-	/* Update IPL. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	/* Set hardware masks. */
 	bus_space_write_8(sc->sc_iot, sc->sc_ioh, scpu->scpu_ibank[0].en,
diff --git a/sys/arch/sgi/localbus/int.c b/sys/arch/sgi/localbus/int.c
index ef251db20b0..69c4653625d 100644
--- a/sys/arch/sgi/localbus/int.c
+++ b/sys/arch/sgi/localbus/int.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: int.c,v 1.14 2017/02/11 03:44:22 visa Exp $	*/
+/*	$OpenBSD: int.c,v 1.15 2018/02/24 11:42:31 visa Exp $	*/
 /*	$NetBSD: int.c,v 1.24 2011/07/01 18:53:46 dyoung Exp $	*/
 
 /*
@@ -248,10 +248,7 @@ int2_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 	register_t sr;
 
-	__asm__ (".set noreorder");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	sr = disableintr();	/* XXX overkill? */
 	int2_write(INT2_LOCAL1_MASK, (int2_intem >> 8) & ~int2_l1imask[newipl]);
diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c
index 7d5a1650db9..4c25bc74374 100644
--- a/sys/arch/sgi/localbus/macebus.c
+++ b/sys/arch/sgi/localbus/macebus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: macebus.c,v 1.66 2017/05/11 15:47:45 visa Exp $ */
+/*	$OpenBSD: macebus.c,v 1.67 2018/02/24 11:42:31 visa Exp $ */
 
 /*
  * Copyright (c) 2000-2004 Opsycon AB  (www.opsycon.se)
@@ -540,10 +540,7 @@ macebus_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 
 	/* Update masks to new ipl. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 	crime_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
diff --git a/sys/arch/sgi/sgi/intr_template.c b/sys/arch/sgi/sgi/intr_template.c
index 177199babf8..80aa04772cf 100644
--- a/sys/arch/sgi/sgi/intr_template.c
+++ b/sys/arch/sgi/sgi/intr_template.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr_template.c,v 1.18 2017/02/11 03:44:22 visa Exp $	*/
+/*	$OpenBSD: intr_template.c,v 1.19 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -138,10 +138,7 @@ INTR_FUNCTIONNAME(uint32_t hwpend, struct trapframe *frame)
 		int lvl, bitno;
 		uint64_t tmpisr;
 
-		__asm__ (".set noreorder\n");
 		ipl = ci->ci_ipl;
-		mips_sync();
-		__asm__ (".set reorder\n");
 
 		/* Service higher level interrupts first */
 		for (lvl = NIPLS - 1; lvl != IPL_NONE; lvl--) {
@@ -190,10 +187,7 @@ INTR_FUNCTIONNAME(uint32_t hwpend, struct trapframe *frame)
 					if (ih->ih_level < IPL_IPI)
 						setsr(sr);
 #endif
-					__asm__ (".set noreorder\n");
 					ci->ci_ipl = ipl;
-					mips_sync();
-					__asm__ (".set reorder\n");
 					if (ret == 1)
 						break;
 				}
diff --git a/sys/arch/sgi/sgi/ip27_machdep.c b/sys/arch/sgi/sgi/ip27_machdep.c
index f4bffbb5fb9..15674e2abc1 100644
--- a/sys/arch/sgi/sgi/ip27_machdep.c
+++ b/sys/arch/sgi/sgi/ip27_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip27_machdep.c,v 1.78 2018/01/29 14:51:57 visa Exp $	*/
+/*	$OpenBSD: ip27_machdep.c,v 1.79 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -900,10 +900,7 @@ ip27_hub_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 
 	/* Update masks to new ipl. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 	ip27_hub_setintrmask(newipl);
 
 	/* If we still have softints pending trigger processing. */
diff --git a/sys/arch/sgi/xbow/xheart.c b/sys/arch/sgi/xbow/xheart.c
index babbf7d67ea..56b29915c70 100644
--- a/sys/arch/sgi/xbow/xheart.c
+++ b/sys/arch/sgi/xbow/xheart.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xheart.c,v 1.31 2017/02/11 03:44:22 visa Exp $	*/
+/*	$OpenBSD: xheart.c,v 1.32 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2008 Miodrag Vallat.
@@ -400,10 +400,7 @@ xheart_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 
 	/* Update masks to new ipl. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 	xheart_setintrmask(newipl);
 
 	/* If we still have softints pending trigger processing. */