From: jsg <jsg@openbsd.org>
Date: Mon, 19 Jul 2021 10:17:06 +0000 (+0000)
Subject: drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=c543d394c858ae75330dbb07bc713b783b21e901;p=openbsd

drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7

From Wesley Chalmers
afa06442d23d32e95e3336cf8ff366bdd8d590ee in linux 5.10.y/5.10.51
3577e1678772ce3ede92af3a75b44a4b76f9b4ad in mainline linux
---

diff --git a/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f1e9b3b06b9..9d3ccdd3558 100644
--- a/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -243,7 +243,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
 	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 
 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
-	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 }
 
 void dcn20_disable_vga(