From: jsg Date: Tue, 12 Jul 2022 05:45:49 +0000 (+0000) Subject: remove cache parts of struct cpu_info which were used by vmm X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=bf955257b2e4f9965070506534c35deae28135e8;p=openbsd remove cache parts of struct cpu_info which were used by vmm --- diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index a4a207118a2..2bfddd664f9 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.649 2022/07/07 00:56:46 daniel Exp $ */ +/* $OpenBSD: machdep.c,v 1.650 2022/07/12 05:45:49 jsg Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -1838,12 +1838,9 @@ identifycpu(struct cpu_info *ci) u_int regs[4]; cpuid(0x80000000, regs); - if (regs[0] >= 0x80000005) - cpuid(0x80000005, ci->ci_amdcacheinfo); - if (regs[0] >= 0x80000006) { - cpuid(0x80000006, ci->ci_extcacheinfo); - cachesize = (ci->ci_extcacheinfo[2] >> 16); + cpuid(0x80000006, regs); + cachesize = (regs[2] >> 16); } } @@ -1859,7 +1856,6 @@ identifycpu(struct cpu_info *ci) } if (vendor == CPUVENDOR_INTEL) { - u_int regs[4]; /* * PIII, Core Solo and Core Duo CPUs have known * errata stating: @@ -1870,12 +1866,6 @@ identifycpu(struct cpu_info *ci) */ if (ci->ci_family == 6 && ci->ci_model < 15) ci->ci_feature_flags &= ~CPUID_PAT; - - if (cpuid_level >= 0x1) { - cpuid(0x80000000, regs); - if (regs[0] >= 0x80000006) - cpuid(0x80000006, ci->ci_extcacheinfo); - } } /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ diff --git a/sys/arch/i386/include/cpu.h b/sys/arch/i386/include/cpu.h index 34f9b2afca4..5f300710562 100644 --- a/sys/arch/i386/include/cpu.h +++ b/sys/arch/i386/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.175 2021/07/06 09:34:06 kettenis Exp $ */ +/* $OpenBSD: cpu.h,v 1.176 2022/07/12 05:45:49 jsg Exp $ */ /* $NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $ */ /*- @@ -137,8 +137,6 @@ struct cpu_info { u_int32_t ci_feature_tpmflags; /* thermal & power bits */ u_int32_t cpu_class; /* CPU class */ u_int32_t ci_cflushsz; /* clflush cache-line size */ - u_int32_t ci_amdcacheinfo[4]; /* AMD cache info */ - u_int32_t ci_extcacheinfo[4]; /* Intel cache info */ int ci_inatomic;