From: jsg <jsg@openbsd.org>
Date: Sat, 10 Feb 2018 09:46:58 +0000 (+0000)
Subject: Additional AMD CPUID bits documented in
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=bf6012b655399114427e9da1882a5d271f48ccc7;p=openbsd

Additional AMD CPUID bits documented in
"Processor Programming Reference (PPR) for AMD Family 17h
Model 01h, Revision B1 Processors"

ok mlarkin@ deraadt@
---

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 554b0a55625..046fde6855a 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: identcpu.c,v 1.93 2018/01/15 06:53:02 mlarkin Exp $	*/
+/*	$OpenBSD: identcpu.c,v 1.94 2018/02/10 09:46:58 jsg Exp $	*/
 /*	$NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $	*/
 
 /*
@@ -160,9 +160,15 @@ const struct {
 	{ CPUIDECX_SKINIT,	"SKINIT" },
 	{ CPUIDECX_LWP,		"WDT" },
 	{ CPUIDECX_FMA4,	"FMA4" },
+	{ CPUIDECX_TCE,		"TCE" },
 	{ CPUIDECX_NODEID,	"NODEID" },
 	{ CPUIDECX_TBM,		"TBM" },
 	{ CPUIDECX_TOPEXT,	"TOPEXT" },
+	{ CPUIDECX_CPCTR,	"CPCTR" },
+	{ CPUIDECX_DBKP,	"DBKP" },
+	{ CPUIDECX_PERFTSC,	"PERFTSC" },
+	{ CPUIDECX_PCTRL3,	"PCTRL3" },
+	{ CPUIDECX_MWAITX,	"MWAITX" },
 }, cpu_seff0_ebxfeatures[] = {
 	{ SEFF0EBX_FSGSBASE,	"FSGSBASE" },
 	{ SEFF0EBX_SGX,		"SGX" },
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index a4e8f27cba2..ae81a593f9a 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.66 2018/01/15 18:57:59 mlarkin Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.67 2018/02/10 09:46:58 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -279,12 +279,17 @@
 /* Reserved			0x00004000 */
 #define	CPUIDECX_LWP		0x00008000 /* Lightweight profiling support */
 #define	CPUIDECX_FMA4		0x00010000 /* 4-operand FMA instructions */
-/* Reserved			0x00020000 */
+#define	CPUIDECX_TCE		0x00020000 /* Translation Cache Extension */
 /* Reserved			0x00040000 */
 #define	CPUIDECX_NODEID		0x00080000 /* Support for MSRC001C */
 /* Reserved			0x00100000 */
 #define	CPUIDECX_TBM		0x00200000 /* Trailing bit manipulation instruction */
 #define	CPUIDECX_TOPEXT		0x00400000 /* Topology extensions support */
+#define	CPUIDECX_CPCTR		0x00800000 /* core performance counter ext */
+#define	CPUIDECX_DBKP		0x04000000 /* DataBreakpointExtension */
+#define	CPUIDECX_PERFTSC	0x08000000 /* performance time-stamp counter */
+#define	CPUIDECX_PCTRL3		0x10000000 /* L3 performance counter ext */
+#define	CPUIDECX_MWAITX		0x20000000 /* MWAITX/MONITORX */
 
 /*
  * "Advanced Power Management Information" bits (CPUID function 0x80000007):
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 4da7cb4e67f..b3c7aabcd69 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.609 2018/01/22 09:08:43 mpi Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.610 2018/02/10 09:46:58 jsg Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -1017,9 +1017,15 @@ const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = {
 	{ CPUIDECX_WDT,		"WDT" },
 	{ CPUIDECX_LWP,		"LWP" },
 	{ CPUIDECX_FMA4,	"FMA4" },
+	{ CPUIDECX_TCE,		"TCE" },
 	{ CPUIDECX_NODEID,	"NODEID" },
 	{ CPUIDECX_TBM,		"TBM" },
 	{ CPUIDECX_TOPEXT,	"TOPEXT" },
+	{ CPUIDECX_CPCTR,	"CPCTR" },
+	{ CPUIDECX_DBKP,	"DBKP" },
+	{ CPUIDECX_PERFTSC,	"PERFTSC" },
+	{ CPUIDECX_PCTRL3,	"PCTRL3" },
+	{ CPUIDECX_MWAITX,	"MWAITX" },
 };
 
 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = {
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 558abf057ce..a21292b7088 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.64 2017/08/12 19:53:37 mlarkin Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.65 2018/02/10 09:46:58 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -265,12 +265,17 @@
 /* Reserved			0x00004000 */
 #define	CPUIDECX_LWP		0x00008000 /* Lightweight profiling support */
 #define	CPUIDECX_FMA4		0x00010000 /* 4-operand FMA instructions */
-/* Reserved			0x00020000 */
+#define	CPUIDECX_TCE		0x00020000 /* Translation Cache Extension */
 /* Reserved			0x00040000 */
 #define	CPUIDECX_NODEID		0x00080000 /* Support for MSRC001C */
 /* Reserved			0x00100000 */
 #define	CPUIDECX_TBM		0x00200000 /* Trailing bit manipulation instruction */
 #define	CPUIDECX_TOPEXT		0x00400000 /* Topology extensions support */
+#define	CPUIDECX_CPCTR		0x00800000 /* core performance counter ext */
+#define	CPUIDECX_DBKP		0x04000000 /* DataBreakpointExtension */
+#define	CPUIDECX_PERFTSC	0x08000000 /* performance time-stamp counter */
+#define	CPUIDECX_PCTRL3		0x10000000 /* L3 performance counter ext */
+#define	CPUIDECX_MWAITX		0x20000000 /* MWAITX/MONITORX */
 
 /*
  * "Advanced Power Management Information" bits (CPUID function 0x80000007):