From: deraadt Date: Thu, 9 Apr 2015 18:58:22 +0000 (+0000) Subject: Send lmc(4) and san(4) to the HDLC framed bit bucket in the sky. X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=ba2b6ec25b9740b67d6f21dd4908a9a461c697c6;p=openbsd Send lmc(4) and san(4) to the HDLC framed bit bucket in the sky. --- diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index ab494fd36e6..33391cc0002 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.313 2015/03/18 12:04:26 dlg Exp $ +# $OpenBSD: files.pci,v 1.314 2015/04/09 18:58:22 deraadt Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -291,14 +291,6 @@ file dev/pci/ppb.c ppb attach cy at pci with cy_pci file dev/pci/cy_pci.c cy_pci -# Lan Media Corporation T1/HSSI/DS3 adapter -device lmc: ifnet, sppp, ifmedia -attach lmc at pci -file dev/pci/if_lmc.c lmc -file dev/pci/if_lmc_common.c lmc -file dev/pci/if_lmc_media.c lmc -file dev/pci/if_lmc_obsd.c lmc - # Myson Century MTD800/MTD803/MTD891 attach mtd at pci with mtd_pci file dev/pci/if_mtd_pci.c mtd_pci @@ -724,15 +716,6 @@ file dev/pci/if_malo_pci.c malo_pci attach bwi at pci with bwi_pci file dev/pci/if_bwi_pci.c bwi_pci -# Sangoma PCI card -device san: ifnet, ifmedia, sppp -attach san at pci -file dev/pci/if_sandrv.c san -file dev/pci/if_san_common.c san -file dev/pci/if_san_obsd.c san -file dev/pci/if_san_te1.c san -file dev/pci/if_san_xilinx.c san - # PIIX4 power management controller device piixpm: i2cbus attach piixpm at pci diff --git a/sys/dev/pci/if_lmc.c b/sys/dev/pci/if_lmc.c deleted file mode 100644 index 791e67dd54b..00000000000 --- a/sys/dev/pci/if_lmc.c +++ /dev/null @@ -1,1377 +0,0 @@ -/* $OpenBSD: if_lmc.c,v 1.29 2015/03/14 03:38:48 jsg Exp $ */ -/* $NetBSD: if_lmc.c,v 1.1 1999/03/25 03:32:43 explorer Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * LMC1200 (DS1) & LMC5245 (DS3) LED definitions - * led0 yellow = far-end link is in Red alarm condition - * led1 blue = received an Alarm Indication signal (upstream failure) - * led2 Green = power to adapter, Gate Array loaded & driver attached - * led3 red = Loss of Signal (LOS) or out of frame (OOF) conditions - * detected on T3 receive signal - * - * LMC1000 (SSI) & LMC5200 (HSSI) LED definitions - * led0 Green = power to adapter, Gate Array loaded & driver attached - * led1 Green = DSR and DTR and RTS and CTS are set (CA, TA for LMC5200) - * led2 Green = Cable detected (Green indicates non-loopback mode for LMC5200) - * led3 red = No timing is available from the cable or the on-board - * frequency generator. (ST not available for LMC5200) - */ - -#include "bpfilter.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#if NBPFILTER > 0 -#include -#endif - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -/* - * This module supports - * the DEC 21140A pass 2.2 PCI Fast Ethernet Controller. - */ -static ifnet_ret_t lmc_ifstart_one(struct ifnet *ifp); -static ifnet_ret_t lmc_ifstart(struct ifnet *ifp); -static struct mbuf *lmc_txput(lmc_softc_t * const sc, struct mbuf *m); -static void lmc_rx_intr(lmc_softc_t * const sc); - -static void lmc_watchdog(struct ifnet *ifp); -static void lmc_ifup(lmc_softc_t * const sc); -static void lmc_ifdown(lmc_softc_t * const sc); - -/* - * Code the read the SROM and MII bit streams (I2C) - */ -static inline void -lmc_delay_300ns(lmc_softc_t * const sc) -{ - int idx; - for (idx = (300 / 33) + 1; idx > 0; idx--) - (void)LMC_CSR_READ(sc, csr_busmode); -} - -#define EMIT \ -do { \ - LMC_CSR_WRITE(sc, csr_srom_mii, csr); \ - lmc_delay_300ns(sc); \ -} while (0) - -static inline void -lmc_srom_idle(lmc_softc_t * const sc) -{ - unsigned bit, csr; - - csr = SROMSEL ; EMIT; - csr = SROMSEL | SROMRD; EMIT; - csr ^= SROMCS; EMIT; - csr ^= SROMCLKON; EMIT; - - /* - * Write 25 cycles of 0 which will force the SROM to be idle. - */ - for (bit = 3 + SROM_BITWIDTH + 16; bit > 0; bit--) { - csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */ - csr ^= SROMCLKON; EMIT; /* clock high; data valid */ - } - csr ^= SROMCLKOFF; EMIT; - csr ^= SROMCS; EMIT; - csr = 0; EMIT; -} - - -static void -lmc_srom_read(lmc_softc_t * const sc) -{ - unsigned idx; - const unsigned bitwidth = SROM_BITWIDTH; - const unsigned cmdmask = (SROMCMD_RD << bitwidth); - const unsigned msb = 1 << (bitwidth + 3 - 1); - unsigned lastidx = (1 << bitwidth) - 1; - - lmc_srom_idle(sc); - - for (idx = 0; idx <= lastidx; idx++) { - unsigned lastbit, data, bits, bit, csr; - csr = SROMSEL ; EMIT; - csr = SROMSEL | SROMRD; EMIT; - csr ^= SROMCSON; EMIT; - csr ^= SROMCLKON; EMIT; - - lastbit = 0; - for (bits = idx|cmdmask, bit = bitwidth + 3 - ; bit > 0 - ; bit--, bits <<= 1) { - const unsigned thisbit = bits & msb; - csr ^= SROMCLKOFF; EMIT; /* clock L data invalid */ - if (thisbit != lastbit) { - csr ^= SROMDOUT; EMIT;/* clock L invert data */ - } else { - EMIT; - } - csr ^= SROMCLKON; EMIT; /* clock H data valid */ - lastbit = thisbit; - } - csr ^= SROMCLKOFF; EMIT; - - for (data = 0, bits = 0; bits < 16; bits++) { - data <<= 1; - csr ^= SROMCLKON; EMIT; /* clock H data valid */ - data |= LMC_CSR_READ(sc, csr_srom_mii) & SROMDIN ? 1 : 0; - csr ^= SROMCLKOFF; EMIT; /* clock L data invalid */ - } - sc->lmc_rombuf[idx*2] = data & 0xFF; - sc->lmc_rombuf[idx*2+1] = data >> 8; - csr = SROMSEL | SROMRD; EMIT; - csr = 0; EMIT; - } - lmc_srom_idle(sc); -} - -#define MII_EMIT do { LMC_CSR_WRITE(sc, csr_srom_mii, csr); lmc_delay_300ns(sc); } while (0) - -static inline void -lmc_mii_writebits(lmc_softc_t * const sc, unsigned data, unsigned bits) -{ - unsigned msb = 1 << (bits - 1); - unsigned csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK); - unsigned lastbit = (csr & MII_DOUT) ? msb : 0; - - csr |= MII_WR; MII_EMIT; /* clock low; assert write */ - - for (; bits > 0; bits--, data <<= 1) { - const unsigned thisbit = data & msb; - if (thisbit != lastbit) { - csr ^= MII_DOUT; MII_EMIT; /* clock low; invert data */ - } - csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */ - lastbit = thisbit; - csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */ - } -} - -static void -lmc_mii_turnaround(lmc_softc_t * const sc, u_int32_t cmd) -{ - u_int32_t csr; - - csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK); - if (cmd == MII_WRCMD) { - csr |= MII_DOUT; MII_EMIT; /* clock low; change data */ - csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */ - csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */ - csr ^= MII_DOUT; MII_EMIT; /* clock low; change data */ - } else { - csr |= MII_RD; MII_EMIT; /* clock low; switch to read */ - } - csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */ - csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */ -} - -static u_int32_t -lmc_mii_readbits(lmc_softc_t * const sc) -{ - u_int32_t data; - u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK); - int idx; - - for (idx = 0, data = 0; idx < 16; idx++) { - data <<= 1; /* this is NOOP on the first pass through */ - csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */ - if (LMC_CSR_READ(sc, csr_srom_mii) & MII_DIN) - data |= 1; - csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */ - } - csr ^= MII_RD; MII_EMIT; /* clock low; turn off read */ - - return data; -} - -u_int32_t -lmc_mii_readreg(lmc_softc_t * const sc, u_int32_t devaddr, u_int32_t regno) -{ - u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK); - u_int32_t data; - - csr &= ~(MII_RD|MII_CLK); MII_EMIT; - lmc_mii_writebits(sc, MII_PREAMBLE, 32); - lmc_mii_writebits(sc, MII_RDCMD, 8); - lmc_mii_writebits(sc, devaddr, 5); - lmc_mii_writebits(sc, regno, 5); - lmc_mii_turnaround(sc, MII_RDCMD); - - data = lmc_mii_readbits(sc); - return (data); -} - -void -lmc_mii_writereg(lmc_softc_t * const sc, u_int32_t devaddr, - u_int32_t regno, u_int32_t data) -{ - u_int32_t csr; - - csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK); - csr &= ~(MII_RD|MII_CLK); MII_EMIT; - lmc_mii_writebits(sc, MII_PREAMBLE, 32); - lmc_mii_writebits(sc, MII_WRCMD, 8); - lmc_mii_writebits(sc, devaddr, 5); - lmc_mii_writebits(sc, regno, 5); - lmc_mii_turnaround(sc, MII_WRCMD); - lmc_mii_writebits(sc, data, 16); -} - -int -lmc_read_macaddr(lmc_softc_t * const sc) -{ - lmc_srom_read(sc); - - bcopy(sc->lmc_rombuf + 20, sc->lmc_enaddr, 6); - - return 0; -} - -/* - * Check to make certain there is a signal from the modem, and flicker - * lights as needed. - */ -static void -lmc_watchdog(struct ifnet *ifp) -{ - lmc_softc_t * const sc = LMC_IFP_TO_SOFTC(ifp); - u_int32_t ostatus; - u_int32_t link_status; - u_int32_t ticks; - - /* - * Make sure the tx jabber and rx watchdog are off, - * and the transmit and receive processes are running. - */ - LMC_CSR_WRITE (sc, csr_15, 0x00000011); - sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN; - LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode); - - /* Is the transmit clock still available? */ - ticks = LMC_CSR_READ (sc, csr_gp_timer); - ticks = 0x0000ffff - (ticks & 0x0000ffff); - if (ticks == 0) - { - /* no clock found ? */ - if (sc->tx_clockState != 0) - { - sc->tx_clockState = 0; - if (sc->lmc_cardtype == LMC_CARDTYPE_SSI) - lmc_led_on (sc, LMC_MII16_LED3); /* ON red */ - } - else - if (sc->tx_clockState == 0) - { - sc->tx_clockState = 1; - if (sc->lmc_cardtype == LMC_CARDTYPE_SSI) - lmc_led_off (sc, LMC_MII16_LED3); /* OFF red */ - } - } - - link_status = sc->lmc_media->get_link_status(sc); - ostatus = ((sc->lmc_flags & LMC_MODEMOK) == LMC_MODEMOK); - - /* - * hardware level link lost, but the interface is marked as up. - * Mark it as down. - */ - if (link_status == LMC_LINK_DOWN && ostatus) { - printf(LMC_PRINTF_FMT ": physical link down\n", - LMC_PRINTF_ARGS); - sc->lmc_flags &= ~LMC_MODEMOK; - if (sc->lmc_cardtype == LMC_CARDTYPE_DS3 || - sc->lmc_cardtype == LMC_CARDTYPE_T1) - lmc_led_on (sc, LMC_DS3_LED3 | LMC_DS3_LED2); - /* turn on red LED */ - else { - lmc_led_off (sc, LMC_MII16_LED1); - lmc_led_on (sc, LMC_MII16_LED0); - if (sc->lmc_timing == LMC_CTL_CLOCK_SOURCE_EXT) - lmc_led_on (sc, LMC_MII16_LED3); - } - - } - - /* - * hardware link is up, but the interface is marked as down. - * Bring it back up again. - */ - if (link_status != LMC_LINK_DOWN && !ostatus) { - printf(LMC_PRINTF_FMT ": physical link up\n", - LMC_PRINTF_ARGS); - if (sc->lmc_flags & LMC_IFUP) - lmc_ifup(sc); - sc->lmc_flags |= LMC_MODEMOK; - if (sc->lmc_cardtype == LMC_CARDTYPE_DS3 || - sc->lmc_cardtype == LMC_CARDTYPE_T1) - { - sc->lmc_miireg16 |= LMC_DS3_LED3; - lmc_led_off (sc, LMC_DS3_LED3); - /* turn off red LED */ - lmc_led_on (sc, LMC_DS3_LED2); - } else { - lmc_led_on (sc, LMC_MII16_LED0 | LMC_MII16_LED1 - | LMC_MII16_LED2); - if (sc->lmc_timing != LMC_CTL_CLOCK_SOURCE_EXT) - lmc_led_off (sc, LMC_MII16_LED3); - } - - return; - } - - /* Call media specific watchdog functions */ - sc->lmc_media->watchdog(sc); - - /* - * remember the timer value - */ - ticks = LMC_CSR_READ(sc, csr_gp_timer); - LMC_CSR_WRITE(sc, csr_gp_timer, 0xffffffffUL); - sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff); - - ifp->if_timer = 1; -} - -/* - * Mark the interface as "up" and enable TX/RX and TX/RX interrupts. - * This also does a full software reset. - */ -static void -lmc_ifup(lmc_softc_t * const sc) -{ - sc->lmc_if.if_timer = 0; - - lmc_dec_reset(sc); - lmc_reset(sc); - - sc->lmc_media->set_link_status(sc, LMC_LINK_UP); - sc->lmc_media->set_status(sc, NULL); - - sc->lmc_flags |= LMC_IFUP; - - /* - * for DS3 & DS1 adapters light the green light, led2 - */ - if (sc->lmc_cardtype == LMC_CARDTYPE_DS3 || - sc->lmc_cardtype == LMC_CARDTYPE_T1) - lmc_led_on (sc, LMC_MII16_LED2); - else - lmc_led_on (sc, LMC_MII16_LED0 | LMC_MII16_LED2); - - /* - * select what interrupts we want to get - */ - sc->lmc_intrmask |= (TULIP_STS_NORMALINTR - | TULIP_STS_RXINTR - | TULIP_STS_RXNOBUF - | TULIP_STS_TXINTR - | TULIP_STS_ABNRMLINTR - | TULIP_STS_SYSERROR - | TULIP_STS_TXSTOPPED - | TULIP_STS_TXUNDERFLOW - | TULIP_STS_RXSTOPPED - ); - LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask); - - sc->lmc_cmdmode |= TULIP_CMD_TXRUN; - sc->lmc_cmdmode |= TULIP_CMD_RXRUN; - LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode); - - sc->lmc_if.if_timer = 1; -} - -/* - * Mark the interface as "down" and disable TX/RX and TX/RX interrupts. - * This is done by performing a full reset on the interface. - */ -static void -lmc_ifdown(lmc_softc_t * const sc) -{ - sc->lmc_if.if_timer = 0; - sc->lmc_flags &= ~LMC_IFUP; - - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); - lmc_led_off(sc, LMC_MII16_LED_ALL); - - lmc_dec_reset(sc); - lmc_reset(sc); - sc->lmc_media->set_status(sc, NULL); -} - -static void -lmc_rx_intr(lmc_softc_t * const sc) -{ - lmc_ringinfo_t * const ri = &sc->lmc_rxinfo; - struct ifnet * const ifp = &sc->lmc_if; - u_int32_t status; - int fillok = 1; - - sc->lmc_rxtick++; - - for (;;) { - lmc_desc_t *eop = ri->ri_nextin; - int total_len = 0, last_offset = 0; - struct mbuf *ms = NULL, *me = NULL; - int accept = 0; - bus_dmamap_t map; - int error; - - if (fillok && IF_LEN(&sc->lmc_rxq) < LMC_RXQ_TARGET) - goto queue_mbuf; - - /* - * If the TULIP has no descriptors, there can't be any receive - * descriptors to process. - */ - if (eop == ri->ri_nextout) - break; - - /* - * 90% of the packets will fit in one descriptor. So we - * optimize for that case. - */ - LMC_RXDESC_POSTSYNC(sc, eop, sizeof(*eop)); - status = letoh32(((volatile lmc_desc_t *) eop)->d_status); - if ((status & - (TULIP_DSTS_OWNER|TULIP_DSTS_RxFIRSTDESC|TULIP_DSTS_RxLASTDESC)) == - (TULIP_DSTS_RxFIRSTDESC|TULIP_DSTS_RxLASTDESC)) { - IF_DEQUEUE(&sc->lmc_rxq, ms); - me = ms; - } else { - /* - * If still owned by the TULIP, don't touch it. - */ - if (status & TULIP_DSTS_OWNER) - break; - - /* - * It is possible (though improbable unless the - * BIG_PACKET support is enabled or MCLBYTES < 1518) - * for a received packet to cross more than one - * receive descriptor. - */ - while ((status & TULIP_DSTS_RxLASTDESC) == 0) { - if (++eop == ri->ri_last) - eop = ri->ri_first; - LMC_RXDESC_POSTSYNC(sc, eop, sizeof(*eop)); - status = letoh32(((volatile lmc_desc_t *) - eop)->d_status); - if (eop == ri->ri_nextout || - (status & TULIP_DSTS_OWNER)) { - return; - } - total_len++; - } - - /* - * Dequeue the first buffer for the start of the - * packet. Hopefully this will be the only one we - * need to dequeue. However, if the packet consumed - * multiple descriptors, then we need to dequeue - * those buffers and chain to the starting mbuf. - * All buffers but the last buffer have the same - * length so we can set that now. (we add to - * last_offset instead of multiplying since we - * normally won't go into the loop and thereby - * saving a ourselves from doing a multiplication - * by 0 in the normal case). - */ - IF_DEQUEUE(&sc->lmc_rxq, ms); - for (me = ms; total_len > 0; total_len--) { - map = LMC_GETCTX(me, bus_dmamap_t); - LMC_RXMAP_POSTSYNC(sc, map); - bus_dmamap_unload(sc->lmc_dmatag, map); - sc->lmc_rxmaps[sc->lmc_rxmaps_free++] = map; -#if defined(DIAGNOSTIC) - LMC_SETCTX(me, NULL); -#endif - me->m_len = LMC_RX_BUFLEN; - last_offset += LMC_RX_BUFLEN; - IF_DEQUEUE(&sc->lmc_rxq, me->m_next); - me = me->m_next; - } - } - - /* - * Now get the size of received packet (minus the CRC). - */ - total_len = ((status >> 16) & 0x7FFF); - if (sc->ictl.crc_length == 16) - total_len -= 2; - else - total_len -= 4; - - if ((sc->lmc_flags & LMC_RXIGNORE) == 0 - && ((status & LMC_DSTS_ERRSUM) == 0 -#ifdef BIG_PACKET - || (total_len <= sc->lmc_if.if_mtu + PPP_HEADER_LEN - && (status & TULIP_DSTS_RxOVERFLOW) == 0) -#endif - )) { - - map = LMC_GETCTX(me, bus_dmamap_t); - bus_dmamap_sync(sc->lmc_dmatag, map, 0, me->m_len, - BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->lmc_dmatag, map); - sc->lmc_rxmaps[sc->lmc_rxmaps_free++] = map; -#if defined(DIAGNOSTIC) - LMC_SETCTX(me, NULL); -#endif - - me->m_len = total_len - last_offset; -#if NBPFILTER > 0 - if (sc->lmc_bpf != NULL) { - if (me == ms) - LMC_BPF_TAP(sc, mtod(ms, caddr_t), - total_len, BPF_DIRECTION_IN); - else - LMC_BPF_MTAP(sc, ms, BPF_DIRECTION_IN); - } -#endif - sc->lmc_flags |= LMC_RXACT; - accept = 1; - } else { - ifp->if_ierrors++; - if (status & TULIP_DSTS_RxOVERFLOW) { - sc->lmc_dot3stats.dot3StatsInternalMacReceiveErrors++; - } - map = LMC_GETCTX(me, bus_dmamap_t); - bus_dmamap_unload(sc->lmc_dmatag, map); - sc->lmc_rxmaps[sc->lmc_rxmaps_free++] = map; -#if defined(DIAGNOSTIC) - LMC_SETCTX(me, NULL); -#endif - } - - ifp->if_ipackets++; - if (++eop == ri->ri_last) - eop = ri->ri_first; - ri->ri_nextin = eop; - - queue_mbuf: - /* - * Either we are priming the TULIP with mbufs (m == NULL) - * or we are about to accept an mbuf for the upper layers - * so we need to allocate an mbuf to replace it. If we - * can't replace it, send up it anyways. This may cause - * us to drop packets in the future but that's better than - * being caught in livelock. - * - * Note that if this packet crossed multiple descriptors - * we don't even try to reallocate all the mbufs here. - * Instead we rely on the test of the beginning of - * the loop to refill for the extra consumed mbufs. - */ - if (accept || ms == NULL) { - struct mbuf *m0; - MGETHDR(m0, M_DONTWAIT, MT_DATA); - if (m0 != NULL) { - MCLGET(m0, M_DONTWAIT); - if ((m0->m_flags & M_EXT) == 0) { - m_freem(m0); - m0 = NULL; - } - } - if (accept) { - ms->m_pkthdr.len = total_len; - ms->m_pkthdr.rcvif = ifp; - sppp_input(ifp, ms); - } - ms = m0; - } - if (ms == NULL) { - /* - * Couldn't allocate a new buffer. Don't bother - * trying to replenish the receive queue. - */ - fillok = 0; - sc->lmc_flags |= LMC_RXBUFSLOW; - continue; - } - /* - * Now give the buffer(s) to the TULIP and save in our - * receive queue. - */ - do { - u_int32_t ctl; - lmc_desc_t * const nextout = ri->ri_nextout; - - if (sc->lmc_rxmaps_free > 0) { - map = sc->lmc_rxmaps[--sc->lmc_rxmaps_free]; - } else { - m_freem(ms); - sc->lmc_flags |= LMC_RXBUFSLOW; -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_rxlowbufs++; -#endif - break; - } - LMC_SETCTX(ms, map); - error = bus_dmamap_load(sc->lmc_dmatag, map, - mtod(ms, void *), LMC_RX_BUFLEN, - NULL, BUS_DMA_NOWAIT); - if (error) { - printf(LMC_PRINTF_FMT - ": unable to load rx map, " - "error = %d\n", - LMC_PRINTF_ARGS, error); - panic("lmc_rx_intr"); /* XXX */ - } - - ctl = letoh32(nextout->d_ctl); - /* For some weird reason we lose TULIP_DFLAG_ENDRING */ - if ((nextout+1) == ri->ri_last) - ctl = LMC_CTL(LMC_CTL_FLGS(ctl)| - TULIP_DFLAG_ENDRING, 0, 0); - nextout->d_addr1 = htole32(map->dm_segs[0].ds_addr); - if (map->dm_nsegs == 2) { - nextout->d_addr2 = htole32(map->dm_segs[1].ds_addr); - nextout->d_ctl = - htole32(LMC_CTL(LMC_CTL_FLGS(ctl), - map->dm_segs[0].ds_len, - map->dm_segs[1].ds_len)); - } else { - nextout->d_addr2 = 0; - nextout->d_ctl = - htole32(LMC_CTL(LMC_CTL_FLGS(ctl), - map->dm_segs[0].ds_len, 0)); - } - LMC_RXDESC_POSTSYNC(sc, nextout, sizeof(*nextout)); - ri->ri_nextout->d_status = htole32(TULIP_DSTS_OWNER); - LMC_RXDESC_POSTSYNC(sc, nextout, sizeof(u_int32_t)); - if (++ri->ri_nextout == ri->ri_last) - ri->ri_nextout = ri->ri_first; - me = ms->m_next; - ms->m_next = NULL; - IF_ENQUEUE(&sc->lmc_rxq, ms); - } while ((ms = me) != NULL); - - if (IF_LEN(&sc->lmc_rxq) >= LMC_RXQ_TARGET) - sc->lmc_flags &= ~LMC_RXBUFSLOW; - } -} - -static int -lmc_tx_intr(lmc_softc_t * const sc) -{ - lmc_ringinfo_t * const ri = &sc->lmc_txinfo; - struct mbuf *m; - int xmits = 0; - int descs = 0; - u_int32_t d_status; - - sc->lmc_txtick++; - - while (ri->ri_free < ri->ri_max) { - u_int32_t flag; - - LMC_TXDESC_POSTSYNC(sc, ri->ri_nextin, sizeof(*ri->ri_nextin)); - d_status = letoh32(((volatile lmc_desc_t *) ri->ri_nextin)->d_status); - if (d_status & TULIP_DSTS_OWNER) - break; - - flag = LMC_CTL_FLGS(letoh32(ri->ri_nextin->d_ctl)); - if (flag & TULIP_DFLAG_TxLASTSEG) { - IF_DEQUEUE(&sc->lmc_txq, m); - if (m != NULL) { - bus_dmamap_t map = LMC_GETCTX(m, bus_dmamap_t); - LMC_TXMAP_POSTSYNC(sc, map); - sc->lmc_txmaps[sc->lmc_txmaps_free++] = map; -#if NBPFILTER > 0 - if (sc->lmc_bpf != NULL) - LMC_BPF_MTAP(sc, m, BPF_DIRECTION_OUT); -#endif - m_freem(m); -#if defined(LMC_DEBUG) - } else { - printf(LMC_PRINTF_FMT ": tx_intr: failed to dequeue mbuf?!?\n", LMC_PRINTF_ARGS); -#endif - } - xmits++; - if (d_status & LMC_DSTS_ERRSUM) { - sc->lmc_if.if_oerrors++; - if (d_status & TULIP_DSTS_TxUNDERFLOW) { - sc->lmc_dot3stats.dot3StatsInternalTransmitUnderflows++; - } - } else { - if (d_status & TULIP_DSTS_TxDEFERRED) { - sc->lmc_dot3stats.dot3StatsDeferredTransmissions++; - } - } - } - - if (++ri->ri_nextin == ri->ri_last) - ri->ri_nextin = ri->ri_first; - - ri->ri_free++; - descs++; - sc->lmc_if.if_flags &= ~IFF_OACTIVE; - } - /* - * If nothing left to transmit, disable the timer. - * Else if progress, reset the timer back to 2 ticks. - */ - sc->lmc_if.if_opackets += xmits; - - return descs; -} - -static void -lmc_print_abnormal_interrupt (lmc_softc_t * const sc, u_int32_t csr) -{ - printf(LMC_PRINTF_FMT ": Abnormal interrupt\n", LMC_PRINTF_ARGS); -} - -static const char * const lmc_system_errors[] = { - "parity error", - "master abort", - "target abort", - "reserved #3", - "reserved #4", - "reserved #5", - "reserved #6", - "reserved #7", -}; - -static void -lmc_intr_handler(lmc_softc_t * const sc, int *progress_p) -{ - u_int32_t csr; - - while ((csr = LMC_CSR_READ(sc, csr_status)) & sc->lmc_intrmask) { - - *progress_p = 1; - LMC_CSR_WRITE(sc, csr_status, csr); - - if (csr & TULIP_STS_SYSERROR) { - sc->lmc_last_system_error = (csr & TULIP_STS_ERRORMASK) >> TULIP_STS_ERR_SHIFT; - if (sc->lmc_flags & LMC_NOMESSAGES) { - sc->lmc_flags |= LMC_SYSTEMERROR; - } else { - printf(LMC_PRINTF_FMT ": system error: %s\n", - LMC_PRINTF_ARGS, - lmc_system_errors[sc->lmc_last_system_error]); - } - sc->lmc_flags |= LMC_NEEDRESET; - sc->lmc_system_errors++; - break; - } - if (csr & (TULIP_STS_RXINTR | TULIP_STS_RXNOBUF)) { - u_int32_t misses = LMC_CSR_READ(sc, csr_missed_frames); - if (csr & TULIP_STS_RXNOBUF) - sc->lmc_dot3stats.dot3StatsMissedFrames += misses & 0xFFFF; - /* - * Pass 2.[012] of the 21140A-A[CDE] may hang and/or corrupt data - * on receive overflows. - */ - if ((misses & 0x0FFE0000) && (sc->lmc_features & LMC_HAVE_RXBADOVRFLW)) { - sc->lmc_dot3stats.dot3StatsInternalMacReceiveErrors++; - /* - * Stop the receiver process and spin until it's stopped. - * Tell rx_intr to drop the packets it dequeues. - */ - LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode & ~TULIP_CMD_RXRUN); - while ((LMC_CSR_READ(sc, csr_status) & TULIP_STS_RXSTOPPED) == 0) - ; - LMC_CSR_WRITE(sc, csr_status, TULIP_STS_RXSTOPPED); - sc->lmc_flags |= LMC_RXIGNORE; - } - lmc_rx_intr(sc); - if (sc->lmc_flags & LMC_RXIGNORE) { - /* - * Restart the receiver. - */ - sc->lmc_flags &= ~LMC_RXIGNORE; - LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode); - } - } - if (csr & TULIP_STS_ABNRMLINTR) { - u_int32_t tmp = csr & sc->lmc_intrmask - & ~(TULIP_STS_NORMALINTR|TULIP_STS_ABNRMLINTR); - if (csr & TULIP_STS_TXUNDERFLOW) { - if ((sc->lmc_cmdmode & TULIP_CMD_THRESHOLDCTL) != TULIP_CMD_THRSHLD160) { - sc->lmc_cmdmode += TULIP_CMD_THRSHLD96; - sc->lmc_flags |= LMC_NEWTXTHRESH; - } else if (sc->lmc_features & LMC_HAVE_STOREFWD) { - sc->lmc_cmdmode |= TULIP_CMD_STOREFWD; - sc->lmc_flags |= LMC_NEWTXTHRESH; - } - } - if (sc->lmc_flags & LMC_NOMESSAGES) { - sc->lmc_statusbits |= tmp; - } else { - lmc_print_abnormal_interrupt(sc, tmp); - sc->lmc_flags |= LMC_NOMESSAGES; - } - LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode); - } - - if (csr & TULIP_STS_TXINTR) - lmc_tx_intr(sc); - - if (sc->lmc_flags & LMC_WANTTXSTART) - lmc_ifstart(&sc->lmc_if); - } -} - -lmc_intrfunc_t -lmc_intr_normal(void *arg) -{ - lmc_softc_t * sc = (lmc_softc_t *) arg; - int progress = 0; - - lmc_intr_handler(sc, &progress); - -#if !defined(LMC_VOID_INTRFUNC) - return progress; -#endif -} - -static struct mbuf * -lmc_mbuf_compress(struct mbuf *m) -{ - struct mbuf *m0; -#if MCLBYTES >= LMC_MTU + PPP_HEADER_LEN && !defined(BIG_PACKET) - MGETHDR(m0, M_DONTWAIT, MT_DATA); - if (m0 != NULL) { - if (m->m_pkthdr.len > MHLEN) { - MCLGET(m0, M_DONTWAIT); - if ((m0->m_flags & M_EXT) == 0) { - m_freem(m); - m_freem(m0); - return NULL; - } - } - m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t)); - m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len; - } -#else - int mlen = MHLEN; - int len = m->m_pkthdr.len; - struct mbuf **mp = &m0; - - while (len > 0) { - if (mlen == MHLEN) { - MGETHDR(*mp, M_DONTWAIT, MT_DATA); - } else { - MGET(*mp, M_DONTWAIT, MT_DATA); - } - if (*mp == NULL) { - m_freem(m0); - m0 = NULL; - break; - } - if (len > MLEN) { - MCLGET(*mp, M_DONTWAIT); - if (((*mp)->m_flags & M_EXT) == 0) { - m_freem(m0); - m0 = NULL; - break; - } - (*mp)->m_len = (len <= MCLBYTES ? len : MCLBYTES); - } else { - (*mp)->m_len = (len <= mlen ? len : mlen); - } - m_copydata(m, m->m_pkthdr.len - len, - (*mp)->m_len, mtod((*mp), caddr_t)); - len -= (*mp)->m_len; - mp = &(*mp)->m_next; - mlen = MLEN; - } -#endif - m_freem(m); - return m0; -} - -/* - * queue the mbuf handed to us for the interface. If we cannot - * queue it, return the mbuf. Return NULL if the mbuf was queued. - */ -static struct mbuf * -lmc_txput(lmc_softc_t * const sc, struct mbuf *m) -{ - lmc_ringinfo_t * const ri = &sc->lmc_txinfo; - lmc_desc_t *eop, *nextout; - int segcnt, free; - u_int32_t d_status, ctl; - bus_dmamap_t map; - int error; - -#if defined(LMC_DEBUG) - if ((sc->lmc_cmdmode & TULIP_CMD_TXRUN) == 0) { - printf(LMC_PRINTF_FMT ": txput: tx not running\n", - LMC_PRINTF_ARGS); - sc->lmc_flags |= LMC_WANTTXSTART; - goto finish; - } -#endif - - /* - * Now we try to fill in our transmit descriptors. This is - * a bit reminiscent of going on the Ark two by two - * since each descriptor for the TULIP can describe - * two buffers. So we advance through packet filling - * each of the two entries at a time to fill each - * descriptor. Clear the first and last segment bits - * in each descriptor (actually just clear everything - * but the end-of-ring or chain bits) to make sure - * we don't get messed up by previously sent packets. - * - * We may fail to put the entire packet on the ring if - * there is either not enough ring entries free or if the - * packet has more than MAX_TXSEG segments. In the former - * case we will just wait for the ring to empty. In the - * latter case we have to recopy. - */ - d_status = 0; - eop = nextout = ri->ri_nextout; - segcnt = 0; - free = ri->ri_free; - /* - * Reclaim some DMA maps from if we are out. - */ - if (sc->lmc_txmaps_free == 0) { -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_no_txmaps++; -#endif - free += lmc_tx_intr(sc); - } - if (sc->lmc_txmaps_free > 0) { - map = sc->lmc_txmaps[sc->lmc_txmaps_free-1]; - } else { - sc->lmc_flags |= LMC_WANTTXSTART; -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_txput_finishes[1]++; -#endif - goto finish; - } - error = bus_dmamap_load_mbuf(sc->lmc_dmatag, map, m, BUS_DMA_NOWAIT); - if (error != 0) { - if (error == EFBIG) { - /* - * The packet exceeds the number of transmit buffer - * entries that we can use for one packet, so we have - * to recopy it into one mbuf and then try again. - */ - m = lmc_mbuf_compress(m); - if (m == NULL) { -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_txput_finishes[2]++; -#endif - goto finish; - } - error = bus_dmamap_load_mbuf(sc->lmc_dmatag, map, m, - BUS_DMA_NOWAIT); - } - if (error != 0) { - printf(LMC_PRINTF_FMT ": unable to load tx map, " - "error = %d\n", LMC_PRINTF_ARGS, error); -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_txput_finishes[3]++; -#endif - goto finish; - } - } - if ((free -= (map->dm_nsegs + 1) / 2) <= 0 - /* - * See if there's any unclaimed space in the transmit ring. - */ - && (free += lmc_tx_intr(sc)) <= 0) { - /* - * There's no more room but since nothing - * has been committed at this point, just - * show output is active, put back the - * mbuf and return. - */ - sc->lmc_flags |= LMC_WANTTXSTART; -#if defined(LMC_DEBUG) - sc->lmc_dbg.dbg_txput_finishes[4]++; -#endif - bus_dmamap_unload(sc->lmc_dmatag, map); - goto finish; - } - for (; map->dm_nsegs - segcnt > 1; segcnt += 2) { - int flg; - - eop = nextout; - flg = LMC_CTL_FLGS(letoh32(eop->d_ctl)); - flg &= TULIP_DFLAG_ENDRING; - flg |= TULIP_DFLAG_TxNOPADDING; - if (sc->ictl.crc_length == 16) - flg |= TULIP_DFLAG_TxHASCRC; - eop->d_status = htole32(d_status); - eop->d_addr1 = htole32(map->dm_segs[segcnt].ds_addr); - eop->d_addr2 = htole32(map->dm_segs[segcnt+1].ds_addr); - eop->d_ctl = htole32(LMC_CTL(flg, - map->dm_segs[segcnt].ds_len, - map->dm_segs[segcnt+1].ds_len)); - d_status = TULIP_DSTS_OWNER; - if (++nextout == ri->ri_last) - nextout = ri->ri_first; - } - if (segcnt < map->dm_nsegs) { - int flg; - - eop = nextout; - flg = LMC_CTL_FLGS(letoh32(eop->d_ctl)); - flg &= TULIP_DFLAG_ENDRING; - flg |= TULIP_DFLAG_TxNOPADDING; - if (sc->ictl.crc_length == 16) - flg |= TULIP_DFLAG_TxHASCRC; - eop->d_status = htole32(d_status); - eop->d_addr1 = htole32(map->dm_segs[segcnt].ds_addr); - eop->d_addr2 = 0; - eop->d_ctl = htole32(LMC_CTL(flg, - map->dm_segs[segcnt].ds_len, 0)); - if (++nextout == ri->ri_last) - nextout = ri->ri_first; - } - LMC_TXMAP_PRESYNC(sc, map); - LMC_SETCTX(m, map); - map = NULL; - --sc->lmc_txmaps_free; /* commit to using the dmamap */ - - /* - * The descriptors have been filled in. Now get ready - * to transmit. - */ - IF_ENQUEUE(&sc->lmc_txq, m); - m = NULL; - - /* - * Make sure the next descriptor after this packet is owned - * by us since it may have been set up above if we ran out - * of room in the ring. - */ - nextout->d_status = 0; - LMC_TXDESC_PRESYNC(sc, nextout, sizeof(u_int32_t)); - - /* - * Mark the last and first segments, indicate we want a transmit - * complete interrupt, and tell it to transmit! - */ - ctl = letoh32(eop->d_ctl); - eop->d_ctl = htole32(LMC_CTL( - LMC_CTL_FLGS(ctl)|TULIP_DFLAG_TxLASTSEG|TULIP_DFLAG_TxWANTINTR, - LMC_CTL_LEN1(ctl), - LMC_CTL_LEN2(ctl))); - - /* - * Note that ri->ri_nextout is still the start of the packet - * and until we set the OWNER bit, we can still back out of - * everything we have done. - */ - ctl = letoh32(ri->ri_nextout->d_ctl); - ri->ri_nextout->d_ctl = htole32(LMC_CTL( - LMC_CTL_FLGS(ctl)|TULIP_DFLAG_TxFIRSTSEG, - LMC_CTL_LEN1(ctl), - LMC_CTL_LEN2(ctl))); - if (eop < ri->ri_nextout) { - LMC_TXDESC_PRESYNC(sc, ri->ri_nextout, - (caddr_t) ri->ri_last - (caddr_t) ri->ri_nextout); - LMC_TXDESC_PRESYNC(sc, ri->ri_first, - (caddr_t) (eop + 1) - (caddr_t) ri->ri_first); - } else { - LMC_TXDESC_PRESYNC(sc, ri->ri_nextout, - (caddr_t) (eop + 1) - (caddr_t) ri->ri_nextout); - } - ri->ri_nextout->d_status = htole32(TULIP_DSTS_OWNER); - LMC_TXDESC_PRESYNC(sc, ri->ri_nextout, sizeof(u_int32_t)); - - LMC_CSR_WRITE(sc, csr_txpoll, 1); - - /* - * This advances the ring for us. - */ - ri->ri_nextout = nextout; - ri->ri_free = free; - - /* - * switch back to the single queueing ifstart. - */ - sc->lmc_flags &= ~LMC_WANTTXSTART; - sc->lmc_if.if_start = lmc_ifstart_one; - - /* - * If we want a txstart, there must be not enough space in the - * transmit ring. So we want to enable transmit done interrupts - * so we can immediately reclaim some space. When the transmit - * interrupt is posted, the interrupt handler will call tx_intr - * to reclaim space and then txstart (since WANTTXSTART is set). - * txstart will move the packet into the transmit ring and clear - * WANTTXSTART thereby causing TXINTR to be cleared. - */ - finish: - if (sc->lmc_flags & LMC_WANTTXSTART) { - sc->lmc_if.if_flags |= IFF_OACTIVE; - sc->lmc_if.if_start = lmc_ifstart; - } - - return m; -} - - -/* - * This routine is entered at splnet() - */ -static int -lmc_ifioctl(struct ifnet * ifp, ioctl_cmd_t cmd, caddr_t data) -{ - lmc_softc_t * const sc = LMC_IFP_TO_SOFTC(ifp); - int s; - struct proc *p = curproc; - int error = 0; - struct ifreq *ifr = (struct ifreq *)data; - u_int32_t new_state; - u_int32_t old_state; - lmc_ctl_t ctl; - - s = LMC_RAISESPL(); - - switch (cmd) { - case LMCIOCGINFO: - error = copyout(&sc->ictl, ifr->ifr_data, sizeof(lmc_ctl_t)); - - goto out; - break; - - case LMCIOCSINFO: - error = suser(p, 0); - if (error) - goto out; - - error = copyin(ifr->ifr_data, &ctl, sizeof(lmc_ctl_t)); - if (error != 0) - goto out; - - sc->lmc_media->set_status(sc, &ctl); - - goto out; - break; - - case SIOCSIFMTU: - /* - * Don't allow the MTU to get larger than we can handle - */ - if (ifr->ifr_mtu > LMC_MTU) { - error = EINVAL; - goto out; - } else { - ifp->if_mtu = ifr->ifr_mtu; - } - break; - } - - /* - * call the sppp ioctl layer - */ - error = sppp_ioctl(ifp, cmd, data); - if (error != 0) - goto out; - - /* - * If we are transitioning from up to down or down to up, call - * our init routine. - */ - new_state = ifp->if_flags & IFF_UP; - old_state = sc->lmc_flags & LMC_IFUP; - - if (new_state && !old_state) - lmc_ifup(sc); - else if (!new_state && old_state) - lmc_ifdown(sc); - - out: - LMC_RESTORESPL(s); - - return error; -} - -/* - * These routines gets called at device spl (from sppp_output). - */ - -static ifnet_ret_t -lmc_ifstart(struct ifnet * const ifp) -{ - lmc_softc_t * const sc = LMC_IFP_TO_SOFTC(ifp); - struct mbuf *m, *m0; - - if (sc->lmc_flags & LMC_IFUP) { - while (sppp_isempty(ifp) == 0) { - m = sppp_pick(ifp); - if (m == NULL) - break; - if ((m = lmc_txput(sc, m)) != NULL) - break; - m0 = sppp_dequeue(ifp); -#if defined(LMC_DEBUG) - if (m0 != m) - printf("lmc_ifstart: mbuf mismatch!\n"); -#endif - } - LMC_CSR_WRITE(sc, csr_txpoll, 1); - } -} - -static ifnet_ret_t -lmc_ifstart_one(struct ifnet * const ifp) -{ - lmc_softc_t * const sc = LMC_IFP_TO_SOFTC(ifp); - struct mbuf *m, *m0; - - if ((sc->lmc_flags & LMC_IFUP) && (sppp_isempty(ifp) == 0)) { - m = sppp_pick(ifp); - if ((m = lmc_txput(sc, m)) != NULL) - return; - m0 = sppp_dequeue(ifp); -#if defined(LMC_DEBUG) - if (m0 != m) - printf("lmc_ifstart: mbuf mismatch!\n"); -#endif - LMC_CSR_WRITE(sc, csr_txpoll, 1); - } -} - -/* - * Set up the OS interface magic and attach to the operating system - * network services. - */ -void -lmc_attach(lmc_softc_t * const sc) -{ - struct ifnet * const ifp = &sc->lmc_if; - - ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; - ifp->if_ioctl = lmc_ifioctl; - ifp->if_start = lmc_ifstart; - ifp->if_watchdog = lmc_watchdog; - ifp->if_timer = 1; - ifp->if_mtu = LMC_MTU; - IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); - IFQ_SET_READY(&ifp->if_snd); - - if_attach(ifp); - if_alloc_sadl(ifp); - - sppp_attach((struct ifnet *)&sc->lmc_sppp); - sc->lmc_sppp.pp_flags = PP_CISCO | PP_KEEPALIVE; - sc->lmc_sppp.pp_framebytes = 3; - -#if NBPFILTER > 0 - LMC_BPF_ATTACH(sc); -#endif - - /* - * turn off those LEDs... - */ - sc->lmc_miireg16 |= LMC_MII16_LED_ALL; - /* - * for DS3 & DS1 adapters light the green light, led2 - */ - if (sc->lmc_cardtype == LMC_CARDTYPE_DS3 || - sc->lmc_cardtype == LMC_CARDTYPE_T1) - lmc_led_on (sc, LMC_MII16_LED2); - else - lmc_led_on (sc, LMC_MII16_LED0 | LMC_MII16_LED2); -} - -void -lmc_initring(lmc_softc_t * const sc, lmc_ringinfo_t * const ri, - lmc_desc_t *descs, int ndescs) -{ - ri->ri_max = ndescs; - ri->ri_first = descs; - ri->ri_last = ri->ri_first + ri->ri_max; - bzero((caddr_t) ri->ri_first, sizeof(ri->ri_first[0]) * ri->ri_max); - ri->ri_last[-1].d_ctl = htole32(LMC_CTL(TULIP_DFLAG_ENDRING, 0, 0)); -} diff --git a/sys/dev/pci/if_lmc_common.c b/sys/dev/pci/if_lmc_common.c deleted file mode 100644 index 46680b3b26f..00000000000 --- a/sys/dev/pci/if_lmc_common.c +++ /dev/null @@ -1,346 +0,0 @@ -/* $OpenBSD: if_lmc_common.c,v 1.15 2015/03/14 03:38:48 jsg Exp $ */ -/* $NetBSD: if_lmc_common.c,v 1.1 1999/03/25 03:32:43 explorer Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "bpfilter.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#if NBPFILTER > 0 -#include -#endif - -#include - -#include - -#include -#include -#include - -#define d_length1 u.bd_length1 -#define d_length2 u.bd_length2 -#define d_flag u.bd_flag - -#include -#include -#include - -void -lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits) -{ - sc->lmc_gpio_io &= ~bits; - LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io)); -} - -void -lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits) -{ - sc->lmc_gpio_io |= bits; - LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io)); -} - -void -lmc_led_on(lmc_softc_t * const sc, u_int32_t led) -{ - sc->lmc_miireg16 &= ~led; - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -void -lmc_led_off(lmc_softc_t * const sc, u_int32_t led) -{ - sc->lmc_miireg16 |= led; - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -void -lmc_reset(lmc_softc_t * const sc) -{ - sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET; - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); - - sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET; - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); - - /* - * make some of the GPIO pins be outputs - */ - lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET); - - /* - * drive DP and RESET low to force configuration. This also forces - * the transmitter clock to be internal, but we expect to reset - * that later anyway. - */ - sc->lmc_gpio &= ~(LMC_GEP_DP | LMC_GEP_RESET); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - - /* - * hold for more than 10 microseconds - */ - DELAY(50); - - /* - * stop driving Xilinx-related signals - */ - lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET); - - /* - * busy wait for the chip to reset - */ - while ((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0); - - /* - * Call media specific init routine - */ - sc->lmc_media->init(sc); -} - -void -lmc_dec_reset(lmc_softc_t * const sc) -{ -#ifndef __linux__ - lmc_ringinfo_t *ri; - lmc_desc_t *di; -#endif - u_int32_t val; - - /* - * disable all interrupts - */ - sc->lmc_intrmask = 0; - LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask); - - /* - * we are, obviously, down. - */ -#ifndef __linux__ - sc->lmc_flags &= ~(LMC_IFUP | LMC_MODEMOK); - - DP(("lmc_dec_reset\n")); -#endif - - /* - * Reset the chip with a software reset command. - * Wait 10 microseconds (actually 50 PCI cycles but at - * 33MHz that comes to two microseconds but wait a - * bit longer anyways) - */ - LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET); - DELAY(10); - sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command); - - /* - * We want: - * no ethernet address in frames we write - * disable padding (txdesc, padding disable) - * ignore runt frames (rdes0 bit 15) - * no receiver watchdog or transmitter jabber timer - * (csr15 bit 0,14 == 1) - * if using 16-bit CRC, turn off CRC (trans desc, crc disable) - */ - -#ifndef TULIP_CMD_RECEIVEALL -#define TULIP_CMD_RECEIVEALL 0x40000000L -#endif - - sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS - | TULIP_CMD_FULLDUPLEX - | TULIP_CMD_PASSBADPKT - | TULIP_CMD_NOHEARTBEAT - | TULIP_CMD_PORTSELECT - | TULIP_CMD_RECEIVEALL - | TULIP_CMD_MUSTBEONE - ); - sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE - | TULIP_CMD_THRESHOLDCTL - | TULIP_CMD_STOREFWD - | TULIP_CMD_TXTHRSHLDCTL - ); - - LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode); - - /* - * disable receiver watchdog and transmit jabber - */ - val = LMC_CSR_READ(sc, csr_sia_general); - val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE); - LMC_CSR_WRITE(sc, csr_sia_general, val); - - /* - * turn off those LEDs... - */ - sc->lmc_miireg16 |= LMC_MII16_LED_ALL; - lmc_led_on(sc, LMC_MII16_LED0); - -#ifndef __linux__ - /* - * reprogram the tx desc, rx desc, and PCI bus options - */ - LMC_CSR_WRITE(sc, csr_txlist, sc->lmc_txdescmap->dm_segs[0].ds_addr); - LMC_CSR_WRITE(sc, csr_rxlist, sc->lmc_rxdescmap->dm_segs[0].ds_addr); - LMC_CSR_WRITE(sc, csr_busmode, - (1 << (LMC_BURSTSIZE(sc->lmc_unit) + 8)) - |TULIP_BUSMODE_CACHE_ALIGN8 - |TULIP_BUSMODE_READMULTIPLE); - - IFQ_SET_MAXLEN(&sc->lmc_txq, LMC_TXDESCS); - - /* - * Free all the mbufs that were on the transmit ring. - */ - for (;;) { - bus_dmamap_t map; - struct mbuf *m; - - IF_DEQUEUE(&sc->lmc_txq, m); - if (m == NULL) - break; - map = LMC_GETCTX(m, bus_dmamap_t); - bus_dmamap_unload(sc->lmc_dmatag, map); - sc->lmc_txmaps[sc->lmc_txmaps_free++] = map; - m_freem(m); - } - - /* - * reset descriptor state and reclaim all descriptors. - */ - ri = &sc->lmc_txinfo; - ri->ri_nextin = ri->ri_nextout = ri->ri_first; - ri->ri_free = ri->ri_max; - for (di = ri->ri_first; di < ri->ri_last; di++) - di->d_status = 0; - bus_dmamap_sync(sc->lmc_dmatag, sc->lmc_txdescmap, - 0, sc->lmc_txdescmap->dm_mapsize, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - - /* - * We need to collect all the mbufs were on the - * receive ring before we reinit it either to put - * them back on or to know if we have to allocate - * more. - */ - ri = &sc->lmc_rxinfo; - ri->ri_nextin = ri->ri_nextout = ri->ri_first; - ri->ri_free = ri->ri_max; - for (di = ri->ri_first; di < ri->ri_last; di++) { - u_int32_t ctl = di->d_ctl; - di->d_status = 0; - di->d_ctl = LMC_CTL(LMC_CTL_FLGS(ctl),0,0); - di->d_addr1 = 0; - di->d_addr2 = 0; - } - bus_dmamap_sync(sc->lmc_dmatag, sc->lmc_rxdescmap, - 0, sc->lmc_rxdescmap->dm_mapsize, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - for (;;) { - bus_dmamap_t map; - struct mbuf *m; - IF_DEQUEUE(&sc->lmc_rxq, m); - if (m == NULL) - break; - map = LMC_GETCTX(m, bus_dmamap_t); - bus_dmamap_unload(sc->lmc_dmatag, map); - sc->lmc_rxmaps[sc->lmc_rxmaps_free++] = map; - m_freem(m); - } -#endif -} - -void -lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, - size_t csr_size) -{ - sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size; - sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size; - sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size; - sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size; - sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size; - sc->lmc_csrs.csr_status = csr_base + 5 * csr_size; - sc->lmc_csrs.csr_command = csr_base + 6 * csr_size; - sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size; - sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size; - sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size; - sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size; - sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size; - sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size; - sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size; - sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size; - sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size; -} diff --git a/sys/dev/pci/if_lmc_media.c b/sys/dev/pci/if_lmc_media.c deleted file mode 100644 index c091f0381fa..00000000000 --- a/sys/dev/pci/if_lmc_media.c +++ /dev/null @@ -1,1129 +0,0 @@ -/* $OpenBSD: if_lmc_media.c,v 1.19 2015/03/14 03:38:48 jsg Exp $ */ -/* $Id: if_lmc_media.c,v 1.19 2015/03/14 03:38:48 jsg Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "bpfilter.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#if NBPFILTER > 0 -#include -#endif - -#include - -#include - -#include -#include - -#include -#include -#include - -/* - * For lack of a better place, put the T1 cable stuff here. - */ -char *lmc_t1_cables[] = { - "V.10/RS423", "EIA530A", "reserved", "X.21", "V.35", - "EIA449/EIA530/V.36", "V.28/EIA232", "none", NULL -}; - -/* - * protocol independent method. - */ -static void lmc_set_protocol(lmc_softc_t * const, lmc_ctl_t *); - -/* - * media independent methods to check on media status, link, light LEDs, - * etc. - */ -static void lmc_ds3_init(lmc_softc_t * const); -static void lmc_ds3_default(lmc_softc_t * const); -static void lmc_ds3_set_status(lmc_softc_t * const, lmc_ctl_t *); -static void lmc_ds3_set_100ft(lmc_softc_t * const, int); -static int lmc_ds3_get_link_status(lmc_softc_t * const); -static void lmc_ds3_set_crc_length(lmc_softc_t * const, int); -static void lmc_ds3_set_scram(lmc_softc_t * const, int); -static void lmc_ds3_watchdog(lmc_softc_t * const); - -static void lmc_hssi_init(lmc_softc_t * const); -static void lmc_hssi_default(lmc_softc_t * const); -static void lmc_hssi_set_status(lmc_softc_t * const, lmc_ctl_t *); -static void lmc_hssi_set_clock(lmc_softc_t * const, int); -static int lmc_hssi_get_link_status(lmc_softc_t * const); -static void lmc_hssi_set_link_status(lmc_softc_t * const, int); -static void lmc_hssi_set_crc_length(lmc_softc_t * const, int); -static void lmc_hssi_watchdog(lmc_softc_t * const); - -static void lmc_ssi_init(lmc_softc_t * const); -static void lmc_ssi_default(lmc_softc_t * const); -static void lmc_ssi_set_status(lmc_softc_t * const, lmc_ctl_t *); -static void lmc_ssi_set_clock(lmc_softc_t * const, int); -static void lmc_ssi_set_speed(lmc_softc_t * const, lmc_ctl_t *); -static int lmc_ssi_get_link_status(lmc_softc_t * const); -static void lmc_ssi_set_link_status(lmc_softc_t * const, int); -static void lmc_ssi_set_crc_length(lmc_softc_t * const, int); -static void lmc_ssi_watchdog(lmc_softc_t * const); - -static void lmc_t1_init(lmc_softc_t * const); -static void lmc_t1_default(lmc_softc_t * const); -static void lmc_t1_set_status(lmc_softc_t * const, lmc_ctl_t *); -static int lmc_t1_get_link_status(lmc_softc_t * const); -static void lmc_t1_set_circuit_type(lmc_softc_t * const, int); -static void lmc_t1_set_crc_length(lmc_softc_t * const, int); -static void lmc_t1_set_clock(lmc_softc_t * const, int); -static void lmc_t1_watchdog(lmc_softc_t * const); - -static void lmc_dummy_set_1(lmc_softc_t * const, int); -static void lmc_dummy_set2_1(lmc_softc_t * const, lmc_ctl_t *); - -static inline void write_av9110_bit(lmc_softc_t *, int); -static void write_av9110(lmc_softc_t *, u_int32_t, u_int32_t, u_int32_t, - u_int32_t, u_int32_t); - -lmc_media_t lmc_ds3_media = { - lmc_ds3_init, /* special media init stuff */ - lmc_ds3_default, /* reset to default state */ - lmc_ds3_set_status, /* reset status to state provided */ - lmc_dummy_set_1, /* set clock source */ - lmc_dummy_set2_1, /* set line speed */ - lmc_ds3_set_100ft, /* set cable length */ - lmc_ds3_set_scram, /* set scrambler */ - lmc_ds3_get_link_status, /* get link status */ - lmc_dummy_set_1, /* set link status */ - lmc_ds3_set_crc_length, /* set CRC length */ - lmc_dummy_set_1, /* set T1 or E1 circuit type */ - lmc_ds3_watchdog -}; - -lmc_media_t lmc_hssi_media = { - lmc_hssi_init, /* special media init stuff */ - lmc_hssi_default, /* reset to default state */ - lmc_hssi_set_status, /* reset status to state provided */ - lmc_hssi_set_clock, /* set clock source */ - lmc_dummy_set2_1, /* set line speed */ - lmc_dummy_set_1, /* set cable length */ - lmc_dummy_set_1, /* set scrambler */ - lmc_hssi_get_link_status, /* get link status */ - lmc_hssi_set_link_status, /* set link status */ - lmc_hssi_set_crc_length, /* set CRC length */ - lmc_dummy_set_1, /* set T1 or E1 circuit type */ - lmc_hssi_watchdog -}; - -lmc_media_t lmc_ssi_media = { - lmc_ssi_init, /* special media init stuff */ - lmc_ssi_default, /* reset to default state */ - lmc_ssi_set_status, /* reset status to state provided */ - lmc_ssi_set_clock, /* set clock source */ - lmc_ssi_set_speed, /* set line speed */ - lmc_dummy_set_1, /* set cable length */ - lmc_dummy_set_1, /* set scrambler */ - lmc_ssi_get_link_status, /* get link status */ - lmc_ssi_set_link_status, /* set link status */ - lmc_ssi_set_crc_length, /* set CRC length */ - lmc_dummy_set_1, /* set T1 or E1 circuit type */ - lmc_ssi_watchdog -}; - -lmc_media_t lmc_t1_media = { - lmc_t1_init, /* special media init stuff */ - lmc_t1_default, /* reset to default state */ - lmc_t1_set_status, /* reset status to state provided */ - lmc_t1_set_clock, /* set clock source */ - lmc_dummy_set2_1, /* set line speed */ - lmc_dummy_set_1, /* set cable length */ - lmc_dummy_set_1, /* set scrambler */ - lmc_t1_get_link_status, /* get link status */ - lmc_dummy_set_1, /* set link status */ - lmc_t1_set_crc_length, /* set CRC length */ - lmc_t1_set_circuit_type, /* set T1 or E1 circuit type */ - lmc_t1_watchdog -}; - -static void -lmc_dummy_set_1(lmc_softc_t * const sc, int a) -{ -} - -static void -lmc_dummy_set2_1(lmc_softc_t * const sc, lmc_ctl_t *a) -{ -} - -/* - * HSSI methods - */ - -static void -lmc_hssi_init(lmc_softc_t * const sc) -{ - sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5200; - - lmc_gpio_mkoutput(sc, LMC_GEP_HSSI_CLOCK); -} - -static void -lmc_hssi_default(lmc_softc_t * const sc) -{ - sc->lmc_miireg16 = LMC_MII16_LED_ALL; - - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_EXT); - sc->lmc_media->set_crc_length(sc, LMC_CTL_CRC_LENGTH_16); -} - -/* - * Given a user provided state, set ourselves up to match it. This will - * always reset the card if needed. - */ -static void -lmc_hssi_set_status(lmc_softc_t * const sc, lmc_ctl_t *ctl) -{ - if (ctl == NULL) { - sc->lmc_media->set_clock_source(sc, sc->ictl.clock_source); - lmc_set_protocol(sc, NULL); - - return; - } - - /* - * check for change in clock source - */ - if (ctl->clock_source && !sc->ictl.clock_source) { - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_INT); - sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT; - } else if (!ctl->clock_source && sc->ictl.clock_source) { - sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT; - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_EXT); - } - - lmc_set_protocol(sc, ctl); -} - -/* - * 1 == internal, 0 == external - */ -static void -lmc_hssi_set_clock(lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_CLOCK_SOURCE_EXT) { - sc->lmc_gpio |= LMC_GEP_HSSI_CLOCK; - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT; - printf(LMC_PRINTF_FMT ": clock external\n", - LMC_PRINTF_ARGS); - } else { - sc->lmc_gpio &= ~(LMC_GEP_HSSI_CLOCK); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT; - printf(LMC_PRINTF_FMT ": clock internal\n", - LMC_PRINTF_ARGS); - } -} - -/* - * return hardware link status. - * 0 == link is down, 1 == link is up. - */ -static int -lmc_hssi_get_link_status(lmc_softc_t * const sc) -{ - u_int16_t link_status; - - link_status = lmc_mii_readreg(sc, 0, 16); - - if ((link_status & LMC_MII16_HSSI_CA) == LMC_MII16_HSSI_CA) - return 1; - else - return 0; -} - -static void -lmc_hssi_set_link_status(lmc_softc_t * const sc, int state) -{ - if (state == LMC_LINK_UP) - sc->lmc_miireg16 |= LMC_MII16_HSSI_TA; - else - sc->lmc_miireg16 &= ~LMC_MII16_HSSI_TA; - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -/* - * 0 == 16bit, 1 == 32bit - */ -static void -lmc_hssi_set_crc_length(lmc_softc_t * const sc, int state) -{ - if (state == LMC_CTL_CRC_LENGTH_32) { - /* 32 bit */ - sc->lmc_miireg16 |= LMC_MII16_HSSI_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32; - } else { - /* 16 bit */ - sc->lmc_miireg16 &= ~LMC_MII16_HSSI_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16; - } - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -static void -lmc_hssi_watchdog (lmc_softc_t * const sc) -{ - /* HSSI is blank */ -} - -static void -lmc_ds3_watchdog (lmc_softc_t * const sc) -{ - sc->lmc_miireg16 = lmc_mii_readreg (sc, 0, 16); - if (sc->lmc_miireg16 & 0x0018) - { - printf("%s: AIS Received\n", sc->lmc_xname); - lmc_led_on (sc, LMC_DS3_LED1 | LMC_DS3_LED2); - } -} - -/* - * DS3 methods - */ - -/* - * Set cable length - */ -static void -lmc_ds3_set_100ft(lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_CABLE_LENGTH_GT_100FT) { - sc->lmc_miireg16 &= ~LMC_MII16_DS3_ZERO; - sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_GT_100FT; - } else if (ie == LMC_CTL_CABLE_LENGTH_LT_100FT) { - sc->lmc_miireg16 |= LMC_MII16_DS3_ZERO; - sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_LT_100FT; - } - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -static void -lmc_ds3_default(lmc_softc_t * const sc) -{ - sc->lmc_miireg16 = LMC_MII16_LED_ALL; - - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); - sc->lmc_media->set_cable_length(sc, LMC_CTL_CABLE_LENGTH_LT_100FT); - sc->lmc_media->set_scrambler(sc, LMC_CTL_OFF); - sc->lmc_media->set_crc_length(sc, LMC_CTL_CRC_LENGTH_16); -} - -/* - * Given a user provided state, set ourselves up to match it. This will - * always reset the card if needed. - */ -static void -lmc_ds3_set_status(lmc_softc_t * const sc, lmc_ctl_t *ctl) -{ - if (ctl == NULL) { - sc->lmc_media->set_cable_length(sc, sc->ictl.cable_length); - sc->lmc_media->set_scrambler(sc, sc->ictl.scrambler_onoff); - lmc_set_protocol(sc, NULL); - - return; - } - - /* - * check for change in cable length setting - */ - if (ctl->cable_length && !sc->ictl.cable_length) - lmc_ds3_set_100ft(sc, LMC_CTL_CABLE_LENGTH_GT_100FT); - else if (!ctl->cable_length && sc->ictl.cable_length) - lmc_ds3_set_100ft(sc, LMC_CTL_CABLE_LENGTH_LT_100FT); - - /* - * Check for change in scrambler setting (requires reset) - */ - if (ctl->scrambler_onoff && !sc->ictl.scrambler_onoff) - lmc_ds3_set_scram(sc, LMC_CTL_ON); - else if (!ctl->scrambler_onoff && sc->ictl.scrambler_onoff) - lmc_ds3_set_scram(sc, LMC_CTL_OFF); - - lmc_set_protocol(sc, ctl); -} - -static void -lmc_ds3_init(lmc_softc_t * const sc) -{ - int i; - - sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5245; - - /* writes zeros everywhere */ - for (i = 0 ; i < 21 ; i++) { - lmc_mii_writereg(sc, 0, 17, i); - lmc_mii_writereg(sc, 0, 18, 0); - } - - /* set some essential bits */ - lmc_mii_writereg(sc, 0, 17, 1); - lmc_mii_writereg(sc, 0, 18, 0x05); /* ser, xtx */ - - lmc_mii_writereg(sc, 0, 17, 5); - lmc_mii_writereg(sc, 0, 18, 0x80); /* emode */ - - lmc_mii_writereg(sc, 0, 17, 14); - lmc_mii_writereg(sc, 0, 18, 0x30); /* rcgen, tcgen */ - - /* clear counters and latched bits */ - for (i = 0 ; i < 21 ; i++) { - lmc_mii_writereg(sc, 0, 17, i); - lmc_mii_readreg(sc, 0, 18); - } -} - -/* - * 1 == DS3 payload scrambled, 0 == not scrambled - */ -static void -lmc_ds3_set_scram(lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_ON) { - sc->lmc_miireg16 |= LMC_MII16_DS3_SCRAM; - sc->ictl.scrambler_onoff = LMC_CTL_ON; - } else { - sc->lmc_miireg16 &= ~LMC_MII16_DS3_SCRAM; - sc->ictl.scrambler_onoff = LMC_CTL_OFF; - } - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -/* - * return hardware link status. - * 0 == link is down, 1 == link is up. - */ -static int -lmc_ds3_get_link_status(lmc_softc_t * const sc) -{ - u_int16_t link_status; - - lmc_mii_writereg(sc, 0, 17, 7); - link_status = lmc_mii_readreg(sc, 0, 18); - - if ((link_status & LMC_FRAMER_REG0_DLOS) == 0) - return 1; - else - return 0; -} - -/* - * 0 == 16bit, 1 == 32bit - */ -static void -lmc_ds3_set_crc_length(lmc_softc_t * const sc, int state) -{ - if (state == LMC_CTL_CRC_LENGTH_32) { - /* 32 bit */ - sc->lmc_miireg16 |= LMC_MII16_DS3_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32; - } else { - /* 16 bit */ - sc->lmc_miireg16 &= ~LMC_MII16_DS3_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16; - } - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - - -/* - * SSI methods - */ - -static void -lmc_ssi_init(lmc_softc_t * const sc) -{ - u_int16_t mii17; - int cable; - - sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1000; - - mii17 = lmc_mii_readreg(sc, 0, 17); - - cable = (mii17 & LMC_MII17_SSI_CABLE_MASK) >> LMC_MII17_SSI_CABLE_SHIFT; - sc->ictl.cable_type = cable; - - lmc_gpio_mkoutput(sc, LMC_GEP_SSI_TXCLOCK); -} - -static void -lmc_ssi_default(lmc_softc_t * const sc) -{ - sc->lmc_miireg16 = LMC_MII16_LED_ALL; - - /* - * make TXCLOCK always be an output - */ - lmc_gpio_mkoutput(sc, LMC_GEP_SSI_TXCLOCK); - - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_EXT); - sc->lmc_media->set_speed(sc, NULL); - sc->lmc_media->set_crc_length(sc, LMC_CTL_CRC_LENGTH_16); -} - -/* - * Given a user provided state, set ourselves up to match it. This will - * always reset the card if needed. - */ -static void -lmc_ssi_set_status(lmc_softc_t * const sc, lmc_ctl_t *ctl) -{ - if (ctl == NULL) { - sc->lmc_media->set_clock_source(sc, sc->ictl.clock_source); - sc->lmc_media->set_speed(sc, &sc->ictl); - lmc_set_protocol(sc, NULL); - - return; - } - - /* - * check for change in clock source - */ - if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_INT - && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_EXT) { - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_INT); - sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT; - } else if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_EXT - && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_INT) { - sc->lmc_media->set_clock_source(sc, LMC_CTL_CLOCK_SOURCE_EXT); - sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT; - } - - if (ctl->clock_rate != sc->ictl.clock_rate) - sc->lmc_media->set_speed(sc, ctl); - - lmc_set_protocol(sc, ctl); -} - -/* - * 1 == internal, 0 == external - */ -static void -lmc_ssi_set_clock(lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_CLOCK_SOURCE_EXT) { - sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT; - printf(LMC_PRINTF_FMT ": clock external\n", - LMC_PRINTF_ARGS); - } else { - sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK; - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT; - printf(LMC_PRINTF_FMT ": clock internal\n", - LMC_PRINTF_ARGS); - } -} - -static void -lmc_ssi_set_speed(lmc_softc_t * const sc, lmc_ctl_t *ctl) -{ - lmc_ctl_t *ictl = &sc->ictl; - lmc_av9110_t *av; - - /* original settings for clock rate of: - * 100 KHz (8,25,0,0,2) were incorrect - * they should have been 80,125,1,3,3 - * There are 17 param combinations to produce this freq. - * For 1.5 MHz use 120,100,1,1,2 (226 param. combinations) - */ - if (ctl == NULL) { - av = &ictl->cardspec.ssi; - ictl->clock_rate = 1500000; - av->f = ictl->clock_rate; - av->n = 120; - av->m = 100; - av->v = 1; - av->x = 1; - av->r = 2; - - write_av9110(sc, av->n, av->m, av->v, av->x, av->r); - return; - } - - av = &ctl->cardspec.ssi; - - if (av->f == 0) - return; - - ictl->clock_rate = av->f; /* really, this is the rate we are */ - ictl->cardspec.ssi = *av; - - write_av9110(sc, av->n, av->m, av->v, av->x, av->r); -} - -/* - * return hardware link status. - * 0 == link is down, 1 == link is up. - */ -static int -lmc_ssi_get_link_status(lmc_softc_t * const sc) -{ - u_int16_t link_status; - - /* - * missing CTS? Hmm. If we require CTS on, we may never get the - * link to come up, so omit it in this test. - * - * Also, it seems that with a loopback cable, DCD isn't asserted, - * so just check for things like this: - * DSR _must_ be asserted. - * One of DCD or CTS must be asserted. - */ - -#ifdef CONFIG_LMC_IGNORE_HARDWARE_HANDSHAKE - link_status = LMC_CSR_READ(sc, csr_gp_timer); - link_status = 0x0000ffff - ( link_status & 0x0000ffff); - - return( link_status ); -#else - - link_status = lmc_mii_readreg(sc, 0, 16); - - if ((link_status & LMC_MII16_SSI_DSR) == 0) - return (0); - - if ((link_status & (LMC_MII16_SSI_CTS | LMC_MII16_SSI_DCD)) == 0) - return (0); - - return (1); -#endif -} - -static void -lmc_ssi_set_link_status(lmc_softc_t * const sc, int state) -{ - if (state == LMC_LINK_UP) { - sc->lmc_miireg16 |= (LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS); - printf(LMC_PRINTF_FMT ": asserting DTR and RTS\n", - LMC_PRINTF_ARGS); - } else { - sc->lmc_miireg16 &= ~(LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS); - printf(LMC_PRINTF_FMT ": deasserting DTR and RTS\n", - LMC_PRINTF_ARGS); - } - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); - -} - -/* - * 0 == 16bit, 1 == 32bit - */ -static void -lmc_ssi_set_crc_length(lmc_softc_t * const sc, int state) -{ - if (state == LMC_CTL_CRC_LENGTH_32) { - /* 32 bit */ - sc->lmc_miireg16 |= LMC_MII16_SSI_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32; - sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4; - - } else { - /* 16 bit */ - sc->lmc_miireg16 &= ~LMC_MII16_SSI_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16; - sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2; - } - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -/* - * These are bits to program the ssi frequency generator - */ -static inline void -write_av9110_bit(lmc_softc_t *sc, int c) -{ - /* - * set the data bit as we need it. - */ - sc->lmc_gpio &= ~(LMC_GEP_SERIALCLK); - if (c & 0x01) - sc->lmc_gpio |= LMC_GEP_SERIAL; - else - sc->lmc_gpio &= ~(LMC_GEP_SERIAL); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - - /* - * set the clock to high - */ - sc->lmc_gpio |= LMC_GEP_SERIALCLK; - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - - /* - * set the clock to low again. - */ - sc->lmc_gpio &= ~(LMC_GEP_SERIALCLK); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); -} - -static void -write_av9110(lmc_softc_t *sc, u_int32_t n, u_int32_t m, u_int32_t v, - u_int32_t x, u_int32_t r) -{ - int i; - -#if 0 - printf(LMC_PRINTF_FMT ": speed %u, %d %d %d %d %d\n", - LMC_PRINTF_ARGS, sc->ictl.clock_rate, - n, m, v, x, r); -#endif - - sc->lmc_gpio |= LMC_GEP_SSI_GENERATOR; - sc->lmc_gpio &= ~(LMC_GEP_SERIAL | LMC_GEP_SERIALCLK); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - - /* - * Set the TXCLOCK, GENERATOR, SERIAL, and SERIALCLK - * as outputs. - */ - lmc_gpio_mkoutput(sc, (LMC_GEP_SERIAL | LMC_GEP_SERIALCLK - | LMC_GEP_SSI_GENERATOR)); - - sc->lmc_gpio &= ~(LMC_GEP_SSI_GENERATOR); - LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio); - - /* - * a shifting we will go... - */ - for (i = 0 ; i < 7 ; i++) - write_av9110_bit(sc, n >> i); - for (i = 0 ; i < 7 ; i++) - write_av9110_bit(sc, m >> i); - for (i = 0 ; i < 1 ; i++) - write_av9110_bit(sc, v >> i); - for (i = 0 ; i < 2 ; i++) - write_av9110_bit(sc, x >> i); - for (i = 0 ; i < 2 ; i++) - write_av9110_bit(sc, r >> i); - for (i = 0 ; i < 5 ; i++) - write_av9110_bit(sc, 0x17 >> i); - - /* - * stop driving serial-related signals - */ - lmc_gpio_mkinput(sc, - (LMC_GEP_SERIAL | LMC_GEP_SERIALCLK - | LMC_GEP_SSI_GENERATOR)); -} - -static void -lmc_ssi_watchdog (lmc_softc_t * const sc) -{ - u_int16_t mii17; - struct ssicsr2 { - unsigned short dtr:1, dsr:1, rts:1, cable:3, crc:1, led0:1, - led1:1, led2:1, led3:1, fifo:1, ll:1, rl:1, tm:1, loop:1; - }; - struct ssicsr2 *ssicsr; - mii17 = lmc_mii_readreg (sc, 0, 17); - ssicsr = (struct ssicsr2 *) &mii17; - if (ssicsr->cable == 7) { - lmc_led_off (sc, LMC_MII16_LED2); - } - else { - lmc_led_on (sc, LMC_MII16_LED2); - } - -} - - -/* - * T1 methods - */ - -/* - * The framer regs are multiplexed through MII regs 17 & 18 - * write the register address to MII reg 17 and the * data to MII reg 18. */ -static void lmc_t1_write(lmc_softc_t * const sc, int a, int d) -{ - lmc_mii_writereg(sc, 0, 17, a); - lmc_mii_writereg(sc, 0, 18, d); -} - -static int lmc_t1_read(lmc_softc_t * const sc, int a) -{ - lmc_mii_writereg(sc, 0, 17, a); - return lmc_mii_readreg(sc, 0, 18); -} - -static void - lmc_t1_init(lmc_softc_t * const sc) -{ - u_int16_t mii16; - int i; - - sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200; - mii16 = lmc_mii_readreg(sc, 0, 16); - - mii16 &= ~LMC_MII16_T1_XOE; - lmc_mii_writereg (sc, 0, 16, mii16); - sc->lmc_miireg16 = mii16; - - /* reset 8370 */ - mii16 &= ~LMC_MII16_T1_RST; - lmc_mii_writereg(sc, 0, 16, mii16 | LMC_MII16_T1_RST); - lmc_mii_writereg(sc, 0, 16, mii16); - - /* set T1 or E1 line impedance */ - /* mii16 &= ~LMC_MII16_T1_Z; */ - mii16 |= LMC_MII16_T1_Z; - lmc_mii_writereg(sc, 0, 16, mii16); - - /* Standard LMC1200 init code */ - lmc_t1_write(sc, 0x01, 0x1B); /* CR0 - primary control */ - lmc_t1_write(sc, 0x02, 0x42); /* JAT_CR - jitter atten config */ - lmc_t1_write(sc, 0x14, 0x00); /* LOOP - loopback config */ - lmc_t1_write(sc, 0x15, 0x00); /* DL3_TS - xtrnl datalink timeslot */ - lmc_t1_write(sc, 0x18, 0xFF); /* PIO - programmable I/O */ - lmc_t1_write(sc, 0x19, 0x30); /* POE - programmable OE */ - lmc_t1_write(sc, 0x1A, 0x0F); /* CMUX - clock input mux */ - lmc_t1_write(sc, 0x20, 0x41); /* LIU_CR - RX LIU config */ - lmc_t1_write(sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */ - lmc_t1_write(sc, 0x40, 0x03); /* RCR0 - RX config */ - lmc_t1_write(sc, 0x45, 0x00); /* RALM - RX alarm config */ - lmc_t1_write(sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */ - lmc_t1_write(sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */ - lmc_t1_write(sc, 0x70, 0x0D); /* TCR0 - TX framer config */ - lmc_t1_write(sc, 0x71, 0x05); /* TCR1 - TX config */ - lmc_t1_write(sc, 0x72, 0x0B); /* TFRM - TX frame format */ - lmc_t1_write(sc, 0x73, 0x00); /* TERROR - TX error insert */ - lmc_t1_write(sc, 0x74, 0x00); /* TMAN - TX manual Sa/FEBE config */ - lmc_t1_write(sc, 0x75, 0x00); /* TALM - TX alarm signal config */ - lmc_t1_write(sc, 0x76, 0x00); /* TPATT - TX test pattern config */ - lmc_t1_write(sc, 0x77, 0x00); /* TLB - TX inband loopback confg */ - lmc_t1_write(sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter confg */ - lmc_t1_write(sc, 0x91, 0x05); /* CSEL - clad freq sel */ - lmc_t1_write(sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */ - lmc_t1_write(sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */ - lmc_t1_write(sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */ - lmc_t1_write(sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */ - lmc_t1_write(sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */ - for (i=0; i<32; i++) - { - lmc_t1_write(sc, 0x0E0+i, 0x00); /*SBCn sysbus perchannel ctl */ - lmc_t1_write(sc, 0x100+i, 0x00); /* TPCn - TX per-channel ctl */ - lmc_t1_write(sc, 0x180+i, 0x00); /* RPCn - RX per-channel ctl */ - } - for (i=1; i<25; i++) - { lmc_t1_write(sc, 0x0E0+i, 0x0D); - /* SBCn - sys bus per-channel ctl */ - } - - mii16 |= LMC_MII16_T1_XOE; - lmc_mii_writereg(sc, 0, 16, mii16); - sc->lmc_miireg16 = mii16; -} - -static void lmc_t1_default(lmc_softc_t * const sc) -{ - sc->lmc_miireg16 = LMC_MII16_LED_ALL; - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); - sc->lmc_media->set_circuit_type(sc, LMC_CTL_CIRCUIT_TYPE_T1); - sc->lmc_media->set_crc_length(sc, LMC_CTL_CRC_LENGTH_16); -} - -/* - * Given a user provided state, set ourselves up to match it. This will - * always reset the card if needed. - */ - -static void -lmc_t1_set_status(lmc_softc_t * const sc, lmc_ctl_t *ctl){ - if (ctl == NULL) { - sc->lmc_media->set_circuit_type(sc, sc->ictl.circuit_type); - lmc_set_protocol(sc, NULL); - - return; - } - - /* - * check for change in circuit type - */ - - if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_T1 - && sc->ictl.circuit_type == LMC_CTL_CIRCUIT_TYPE_E1) - sc->lmc_media->set_circuit_type(sc,LMC_CTL_CIRCUIT_TYPE_E1 ); - else if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_E1 - && sc->ictl.circuit_type == LMC_CTL_CIRCUIT_TYPE_T1) - sc->lmc_media->set_circuit_type(sc, LMC_CTL_CIRCUIT_TYPE_T1); - lmc_set_protocol(sc, ctl); -} - -/* - * return hardware link status. - * 0 == link is down, 1 == link is up. - */ - -static int -lmc_t1_get_link_status(lmc_softc_t * const sc){ - u_int16_t link_status; - lmc_mii_writereg(sc, 0, 17, T1FRAMER_ALARM1_STATUS ); - link_status = lmc_mii_readreg(sc, 0, 18); - - /* - * LMC 1200 LED definitions - * led0 yellow = far-end adapter is in Red alarm condition - * led1 blue = received an Alarm Indication signal (upstream failure) - * led2 Green = power to adapter, Gate Array loaded & driver attached - * led3 red = Loss of Signal (LOS) or out of frame (OOF) conditions - * detected on T3 receive signal - */ - - /* detect a change in Blue alarm indication signal */ - - if( (sc->t1_alarm1_status & T1F_RAIS) != (link_status & T1F_RAIS) ) - { - if( link_status & T1F_RAIS ) - { /* turn on blue LED */ - printf("%s: link status: RAIS turn ON Blue %x\n", sc->lmc_xname, link_status); /* DEBUG */ - lmc_led_on(sc, LMC_DS3_LED1); - } - else - { /* turn off blue LED */ - printf("%s: link status: RAIS turn OFF Blue %x\n", sc->lmc_xname, link_status ); /* DEBUG */ - lmc_led_off(sc, LMC_DS3_LED1); - } - } - /* - * T1F_RYEL wiggles quite a bit, - * taking it out until I understand why -baz 6/22/99 - */ - /* Yellow alarm indication */ - if( (sc->t1_alarm1_status & T1F_RMYEL) != - (link_status & T1F_RMYEL) ) - { - if( (link_status & (T1F_RYEL | T1F_RMYEL)) == 0 ) - { - /* turn off yellow LED */ - printf("%s: link status: RYEL turn OFF Yellow %x\n", sc->lmc_xname, link_status); /* DEBUG */ - lmc_led_off(sc, LMC_DS3_LED0); - - } - else - { - /* turn on yellow LED */ - printf("%s: link status: RYEL turn ON Yellow %x\n", sc->lmc_xname, link_status); /* DEBUG */ - lmc_led_on(sc, LMC_DS3_LED0); - } - } - - - sc->t1_alarm1_status = link_status; - - lmc_mii_writereg(sc, 0, 17, T1FRAMER_ALARM2_STATUS ); - sc->t1_alarm2_status = lmc_mii_readreg(sc, 0, 18); - - /* link status based upon T1 receive loss of frame or - * loss of signal - RED alarm indication */ - if ((link_status & (T1F_RLOF | T1F_RLOS)) == 0) - return 1; - else - return 0; -} - -/* - * 1 == T1 Circuit Type , 0 == E1 Circuit Type - */ -static void - lmc_t1_set_circuit_type(lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_CIRCUIT_TYPE_T1) - { - sc->lmc_miireg16 |= LMC_MII16_T1_Z; - sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_T1; - } else { sc->lmc_miireg16 &= ~LMC_MII16_T1_Z; - sc->ictl.scrambler_onoff = LMC_CTL_CIRCUIT_TYPE_E1; - } - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -/* - * 0 == 16bit, 1 == 32bit */ -static void - lmc_t1_set_crc_length(lmc_softc_t * const sc, int state) -{ - if (state == LMC_CTL_CRC_LENGTH_32) { - /* 32 bit */ - sc->lmc_miireg16 |= LMC_MII16_T1_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32; - sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4; - - } else { - /* 16 bit */ - sc->lmc_miireg16 &= ~LMC_MII16_T1_CRC; - sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16; - sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2; - - } - - lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16); -} - -/* - * 1 == internal, 0 == external - */ -static void -lmc_t1_set_clock (lmc_softc_t * const sc, int ie) -{ - if (ie == LMC_CTL_CLOCK_SOURCE_EXT) { - sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK); - LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT; - printf (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS); - } - else { - sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK; - LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio); - sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT; - printf (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS); - } -} - -static void -lmc_t1_watchdog(lmc_softc_t * const sc) -{ - int t1stat; - - /* read alarm 1 status (receive) */ - t1stat = lmc_t1_read (sc, 0x47); - /* blue alarm -- RAIS */ - if (t1stat & 0x08) { - if (sc->lmc_blue != 1) - printf ("%s: AIS Received\n", sc->lmc_xname); - lmc_led_on (sc, LMC_DS3_LED1 | LMC_DS3_LED2); - sc->lmc_blue = 1; - } else { - if (sc->lmc_blue == 1) - printf ("%s: AIS ok\n", sc->lmc_xname); - lmc_led_off (sc, LMC_DS3_LED1); - lmc_led_on (sc, LMC_DS3_LED2); - sc->lmc_blue = 0; - } - - /* Red alarm -- LOS | LOF */ - if (t1stat & 0x04) { - /* Only print the error once */ - if (sc->lmc_red != 1) - printf ("%s: Red Alarm\n", sc->lmc_xname); - lmc_led_on (sc, LMC_DS3_LED2 | LMC_DS3_LED3); - sc->lmc_red = 1; - } else { - if (sc->lmc_red == 1) - printf ("%s: Red Alarm ok\n", sc->lmc_xname); - lmc_led_off (sc, LMC_DS3_LED3); - lmc_led_on (sc, LMC_DS3_LED2); - sc->lmc_red = 0; - } - - /* check for Receive Multiframe Yellow Alarm - * Ignore Receive Yellow Alarm - */ - if (t1stat & 0x80) { - if (sc->lmc_yel != 1) { - printf ("%s: Receive Yellow Alarm\n", sc->lmc_xname); - } - lmc_led_on (sc, LMC_DS3_LED0 | LMC_DS3_LED2); - sc->lmc_yel = 1; - } - else { - if (sc->lmc_yel == 1) - printf ("%s: Yellow Alarm ok\n", sc->lmc_xname); - lmc_led_off (sc, LMC_DS3_LED0); - lmc_led_on (sc, LMC_DS3_LED2); - sc->lmc_yel = 0; - } -} - - -static void -lmc_set_protocol(lmc_softc_t * const sc, lmc_ctl_t *ctl) -{ - if (ctl == 0) { - sc->ictl.keepalive_onoff = LMC_CTL_ON; - - return; - } - - if (ctl->keepalive_onoff != sc->ictl.keepalive_onoff) { - switch (ctl->keepalive_onoff) { - case LMC_CTL_ON: - printf(LMC_PRINTF_FMT ": enabling keepalive\n", - LMC_PRINTF_ARGS); - sc->ictl.keepalive_onoff = LMC_CTL_ON; - sc->lmc_sppp.pp_flags = PP_CISCO | PP_KEEPALIVE; - break; - case LMC_CTL_OFF: - printf(LMC_PRINTF_FMT ": disabling keepalive\n", - LMC_PRINTF_ARGS); - sc->ictl.keepalive_onoff = LMC_CTL_OFF; - sc->lmc_sppp.pp_flags = PP_CISCO; - } - } -} diff --git a/sys/dev/pci/if_lmc_obsd.c b/sys/dev/pci/if_lmc_obsd.c deleted file mode 100644 index aa1e1c9aac3..00000000000 --- a/sys/dev/pci/if_lmc_obsd.c +++ /dev/null @@ -1,403 +0,0 @@ -/* $OpenBSD: if_lmc_obsd.c,v 1.25 2015/03/14 03:38:48 jsg Exp $ */ -/* $NetBSD: if_lmc_nbsd.c,v 1.1 1999/03/25 03:32:43 explorer Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -/* - * This file is INCLUDED (gross, I know, but...) - */ - -static int lmc_busdma_init(lmc_softc_t * const sc); -static int lmc_busdma_allocmem(lmc_softc_t * const sc, size_t size, - bus_dmamap_t *map_p, lmc_desc_t **desc_p); - -static int -lmc_pci_probe(struct device *parent, - void *match, - void *aux) -{ - struct pci_attach_args *pa = (struct pci_attach_args *)aux; - u_int32_t id; - - /* - * check first for the DEC chip we expect to find. We expect - * 21140A, pass 2.2 or higher. - */ - if (PCI_VENDORID(pa->pa_id) != PCI_VENDOR_DEC) - return 0; - if (PCI_CHIPID(pa->pa_id) != PCI_PRODUCT_DEC_21140) - return 0; - id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFRV) & 0xff; - if (id < 0x22) - return 0; - - /* - * Next, check the subsystem ID and see if it matches what we - * expect. - */ - id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SSID); - if (PCI_VENDORID(id) != PCI_VENDOR_LMC) - return 0; - if ((PCI_CHIPID(id) != PCI_PRODUCT_LMC_HSSI) - && (PCI_CHIPID(id) != PCI_PRODUCT_LMC_HSSIC) - && (PCI_CHIPID(id) != PCI_PRODUCT_LMC_DS3) - && (PCI_CHIPID(id) != PCI_PRODUCT_LMC_SSI) - && (PCI_CHIPID(id) != PCI_PRODUCT_LMC_DS1)) - return 0; - - return 20; /* must be > than any other tulip driver */ -} - -static void lmc_pci_attach(struct device * const parent, - struct device * const self, void * const aux); - -struct cfattach lmc_ca = { - sizeof(lmc_softc_t), lmc_pci_probe, lmc_pci_attach -}; - -struct cfdriver lmc_cd = { - NULL, "lmc", DV_IFNET -}; - -static void -lmc_pci_attach(struct device * const parent, - struct device * const self, void * const aux) -{ - u_int32_t revinfo, cfdainfo, id, ssid; - pci_intr_handle_t intrhandle; - const char *intrstr; - unsigned csroffset = LMC_PCI_CSROFFSET; - unsigned csrsize = LMC_PCI_CSRSIZE; - lmc_csrptr_t csr_base; - lmc_spl_t s; - lmc_intrfunc_t (*intr_rtn)(void *) = lmc_intr_normal; - lmc_softc_t * const sc = (lmc_softc_t *) self; - struct pci_attach_args * const pa = (struct pci_attach_args *) aux; - extern lmc_media_t lmc_hssi_media; - extern lmc_media_t lmc_ds3_media; - extern lmc_media_t lmc_t1_media; - extern lmc_media_t lmc_ssi_media; - - revinfo = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFRV) & 0xFF; - id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFID); - cfdainfo = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CFDA); - ssid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SSID); - - switch (PCI_CHIPID(ssid)) { - case PCI_PRODUCT_LMC_HSSI: - printf(": HSSI\n"); - sc->lmc_media = &lmc_hssi_media; - break; - case PCI_PRODUCT_LMC_HSSIC: - printf(": HSSIc\n"); - sc->lmc_media = &lmc_hssi_media; - break; - case PCI_PRODUCT_LMC_DS3: - printf(": DS3\n"); - sc->lmc_media = &lmc_ds3_media; - break; - case PCI_PRODUCT_LMC_SSI: - printf(": SSI\n"); - sc->lmc_media = &lmc_ssi_media; - break; - case PCI_PRODUCT_LMC_DS1: - printf(": T1\n"); - sc->lmc_media = &lmc_t1_media; - break; - } - - sc->lmc_pci_busno = parent; - sc->lmc_pci_devno = pa->pa_device; - - sc->lmc_chipid = LMC_21140A; - sc->lmc_features |= LMC_HAVE_STOREFWD; - if (sc->lmc_chipid == LMC_21140A && revinfo <= 0x22) - sc->lmc_features |= LMC_HAVE_RXBADOVRFLW; - - if (cfdainfo & (TULIP_CFDA_SLEEP | TULIP_CFDA_SNOOZE)) { - cfdainfo &= ~(TULIP_CFDA_SLEEP | TULIP_CFDA_SNOOZE); - pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_CFDA, cfdainfo); - DELAY(11 * 1000); - } - - bcopy(self->dv_xname, sc->lmc_if.if_xname, IFNAMSIZ); - sc->lmc_if.if_softc = sc; - sc->lmc_pc = pa->pa_pc; - - sc->lmc_revinfo = revinfo; - sc->lmc_if.if_softc = sc; - - csr_base = 0; - { - bus_space_tag_t iot, memt; - bus_space_handle_t ioh, memh; - int ioh_valid, memh_valid; - - ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, - 0, &iot, &ioh, NULL, NULL, 0) == 0); - memh_valid = (pci_mapreg_map(pa, PCI_CBMA, - PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, - &memh, NULL, NULL, 0) == 0); - - if (memh_valid) { - sc->lmc_bustag = memt; - sc->lmc_bushandle = memh; - } else if (ioh_valid) { - sc->lmc_bustag = iot; - sc->lmc_bushandle = ioh; - } else { - printf("%s: unable to map device registers\n", - sc->lmc_dev.dv_xname); - return; - } - } - - sc->lmc_dmatag = pa->pa_dmat; - if ((lmc_busdma_init(sc)) != 0) { - printf("error initing bus_dma\n"); - return; - } - - lmc_initcsrs(sc, csr_base + csroffset, csrsize); - lmc_initring(sc, &sc->lmc_rxinfo, sc->lmc_rxdescs, - LMC_RXDESCS); - lmc_initring(sc, &sc->lmc_txinfo, sc->lmc_txdescs, - LMC_TXDESCS); - - lmc_gpio_mkinput(sc, 0xff); - sc->lmc_gpio = 0; /* drive no signals yet */ - - sc->lmc_media->defaults(sc); - - sc->lmc_media->set_link_status(sc, LMC_LINK_DOWN); /* down */ - - /* - * Make sure there won't be any interrupts or such... - */ - LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET); - - /* - * Wait 10 microseconds (actually 50 PCI cycles but at - * 33MHz that comes to two microseconds but wait a - * bit longer anyways) - */ - DELAY(100); - - lmc_read_macaddr(sc); - - if (pci_intr_map(pa, &intrhandle)) { - printf("%s: couldn't map interrupt\n", - sc->lmc_dev.dv_xname); - return; - } - intrstr = pci_intr_string(pa->pa_pc, intrhandle); - - sc->lmc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, - intr_rtn, sc, self->dv_xname); - - if (sc->lmc_ih == NULL) { - printf("%s: couldn't establish interrupt", - sc->lmc_dev.dv_xname); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - return; - } - - printf("%s: pass %d.%d, serial " LMC_EADDR_FMT ", %s\n", - sc->lmc_dev.dv_xname, - (sc->lmc_revinfo & 0xF0) >> 4, sc->lmc_revinfo & 0x0F, - LMC_EADDR_ARGS(sc->lmc_enaddr), intrstr); - - s = LMC_RAISESPL(); - lmc_dec_reset(sc); - lmc_reset(sc); - lmc_attach(sc); - LMC_RESTORESPL(s); -} - -static int -lmc_busdma_allocmem( - lmc_softc_t * const sc, - size_t size, - bus_dmamap_t *map_p, - lmc_desc_t **desc_p) -{ - bus_dma_segment_t segs[1]; - int nsegs, error; - error = bus_dmamem_alloc(sc->lmc_dmatag, size, 1, NBPG, - segs, nitems(segs), &nsegs, BUS_DMA_NOWAIT); - if (error == 0) { - void *desc; - error = bus_dmamem_map(sc->lmc_dmatag, segs, nsegs, size, - (void *) &desc, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); - if (error == 0) { - bus_dmamap_t map; - error = bus_dmamap_create(sc->lmc_dmatag, size, 1, size, 0, - BUS_DMA_NOWAIT, &map); - if (error == 0) { - error = bus_dmamap_load(sc->lmc_dmatag, map, desc, - size, NULL, BUS_DMA_NOWAIT); - if (error) - bus_dmamap_destroy(sc->lmc_dmatag, map); - else - *map_p = map; - } - if (error) - bus_dmamem_unmap(sc->lmc_dmatag, desc, size); - } - if (error) - bus_dmamem_free(sc->lmc_dmatag, segs, nsegs); - else - *desc_p = desc; - } - return error; -} - -static int -lmc_busdma_init( - lmc_softc_t * const sc) -{ - int error = 0; - - /* - * Allocate space and dmamap for transmit ring - */ - if (error == 0) { - error = lmc_busdma_allocmem(sc, sizeof(lmc_desc_t) * LMC_TXDESCS, - &sc->lmc_txdescmap, - &sc->lmc_txdescs); - } - - /* - * Allocate dmamaps for each transmit descriptors - */ - if (error == 0) { - while (error == 0 && sc->lmc_txmaps_free < LMC_TXDESCS) { - bus_dmamap_t map; - if ((error = LMC_TXMAP_CREATE(sc, &map)) == 0) - sc->lmc_txmaps[sc->lmc_txmaps_free++] = map; - } - if (error) { - while (sc->lmc_txmaps_free > 0) - bus_dmamap_destroy(sc->lmc_dmatag, - sc->lmc_txmaps[--sc->lmc_txmaps_free]); - } - } - - /* - * Allocate space and dmamap for receive ring - */ - if (error == 0) { - error = lmc_busdma_allocmem(sc, sizeof(lmc_desc_t) * LMC_RXDESCS, - &sc->lmc_rxdescmap, - &sc->lmc_rxdescs); - } - - /* - * Allocate dmamaps for each receive descriptors - */ - if (error == 0) { - while (error == 0 && sc->lmc_rxmaps_free < LMC_RXDESCS) { - bus_dmamap_t map; - if ((error = LMC_RXMAP_CREATE(sc, &map)) == 0) - sc->lmc_rxmaps[sc->lmc_rxmaps_free++] = map; - } - if (error) { - while (sc->lmc_rxmaps_free > 0) - bus_dmamap_destroy(sc->lmc_dmatag, - sc->lmc_rxmaps[--sc->lmc_rxmaps_free]); - } - } - - return error; -} diff --git a/sys/dev/pci/if_lmc_types.h b/sys/dev/pci/if_lmc_types.h deleted file mode 100644 index 7a40ab19c59..00000000000 --- a/sys/dev/pci/if_lmc_types.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $OpenBSD: if_lmc_types.h,v 1.5 2005/11/14 14:56:02 mickey Exp $ */ -/* $NetBSD: if_lmc_types.h,v 1.2 1999/03/25 04:09:33 explorer Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LMC_TYPES_H -#define LMC_TYPES_H - -#if defined(_KERNEL) - -/* - * LMC has weird endianness issues, so we can't use the tulip_desc_t. - */ -typedef struct { - u_int32_t d_status; - u_int32_t d_ctl; - u_int32_t d_addr1; - u_int32_t d_addr2; -} lmc_desc_t; - -#define LMC_CTL_FLGS(x) (((x)>>22)&0x3ff) -#define LMC_CTL_LEN2(x) (((x)>>11)&0x7ff) -#define LMC_CTL_LEN1(x) ((x)&0x7ff) -#define LMC_CTL(f,l1,l2) ((((f)&0x3ff)<<22)|(((l2)&0x7ff)<<11)|((l1)&0x7ff)) - -typedef bus_size_t lmc_csrptr_t; - -#define lmc_intrfunc_t int - -typedef struct lmc___softc lmc_softc_t; -typedef struct lmc___media lmc_media_t; -typedef struct lmc_ringinfo lmc_ringinfo_t; - -#endif /* _KERNEL */ - -typedef struct lmc___ctl lmc_ctl_t; - -#endif /* LMC_TYPES_H */ diff --git a/sys/dev/pci/if_lmcioctl.h b/sys/dev/pci/if_lmcioctl.h deleted file mode 100644 index 597f0168738..00000000000 --- a/sys/dev/pci/if_lmcioctl.h +++ /dev/null @@ -1,297 +0,0 @@ -/* $OpenBSD: if_lmcioctl.h,v 1.6 2005/11/07 00:29:21 brad Exp $ */ -/* $Id: if_lmcioctl.h,v 1.6 2005/11/07 00:29:21 brad Exp $ */ - -/* - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * IOCTLs for the sane world. - */ -#define LMCIOCGINFO _IOW('i', 240, struct ifreq) -#define LMCIOCSINFO _IOWR('i', 241, struct ifreq) - -typedef struct { - u_int32_t n; - u_int32_t m; - u_int32_t v; - u_int32_t x; - u_int32_t r; - u_int32_t f; - u_int32_t exact; -} lmc_av9110_t; - -/* - * Common structure passed to the ioctl code. - */ -struct lmc___ctl { - u_int32_t cardtype; - u_int32_t clock_source; /* HSSI, T1 */ - u_int32_t clock_rate; /* T1 */ - u_int32_t crc_length; - u_int32_t cable_length; /* DS3 */ - u_int32_t scrambler_onoff; /* DS3 */ - u_int32_t cable_type; /* T1 */ - u_int32_t keepalive_onoff; /* protocol */ - u_int32_t ticks; /* ticks/sec */ - union { - lmc_av9110_t ssi; - } cardspec; - u_int32_t circuit_type; /* T1 or E1 */ -}; - -#define LMC_CARDTYPE_UNKNOWN -1 -#define LMC_CARDTYPE_HSSI 1 /* probed card is a HSSI card */ -#define LMC_CARDTYPE_DS3 2 /* probed card is a DS3 card */ -#define LMC_CARDTYPE_SSI 3 /* probed card is a SSI card */ -#define LMC_CARDTYPE_T1 4 /* probed card is a T1 card */ - -#define LMC_CTL_CARDTYPE_LMC5200 0 /* HSSI */ -#define LMC_CTL_CARDTYPE_LMC5245 1 /* DS3 */ -#define LMC_CTL_CARDTYPE_LMC1000 2 /* SSI, V.35 */ -#define LMC_CTL_CARDTYPE_LMC1200 3 /* DS1 */ - -#define LMC_CTL_OFF 0 /* generic OFF value */ -#define LMC_CTL_ON 1 /* generic ON value */ - -#define LMC_CTL_CLOCK_SOURCE_EXT 0 /* clock off line */ -#define LMC_CTL_CLOCK_SOURCE_INT 1 /* internal clock */ - -#define LMC_CTL_CRC_LENGTH_16 16 -#define LMC_CTL_CRC_LENGTH_32 32 -#define LMC_CTL_CRC_BYTESIZE_2 2 -#define LMC_CTL_CRC_BYTESIZE_4 4 - -#define LMC_CTL_CABLE_LENGTH_LT_100FT 0 /* DS3 cable < 100 feet */ -#define LMC_CTL_CABLE_LENGTH_GT_100FT 1 /* DS3 cable >= 100 feet */ - -#define LMC_CTL_CIRCUIT_TYPE_E1 0 -#define LMC_CTL_CIRCUIT_TYPE_T1 1 - -/* - * These are not in the least IOCTL related, but I want them common. - */ -/* - * assignments for the GPIO register on the DEC chip (common) - */ -#define LMC_GEP_INIT 0x01 /* 0: */ -#define LMC_GEP_RESET 0x02 /* 1: */ -#define LMC_GEP_LOAD 0x10 /* 4: */ -#define LMC_GEP_DP 0x20 /* 5: */ -#define LMC_GEP_SERIAL 0x40 /* 6: serial out */ -#define LMC_GEP_SERIALCLK 0x80 /* 7: serial clock */ - -/* - * HSSI GPIO assignments - */ -#define LMC_GEP_HSSI_ST 0x04 /* 2: receive timing sense (deprecated) */ -#define LMC_GEP_HSSI_CLOCK 0x08 /* 3: clock source */ - -/* - * T1 GPIO assignments - */ -#define LMC_GEP_SSI_GENERATOR 0x04 /* 2: enable prog freq gen serial i/f */ -#define LMC_GEP_SSI_TXCLOCK 0x08 /* 3: provide clock on TXCLOCK output */ - -/* - * Common MII16 bits - */ -#define LMC_MII16_LED0 0x0080 -#define LMC_MII16_LED1 0x0100 -#define LMC_MII16_LED2 0x0200 -#define LMC_MII16_LED3 0x0400 /* Error, and the red one */ -#define LMC_MII16_LED_ALL 0x0780 /* LED bit mask */ -#define LMC_MII16_FIFO_RESET 0x0800 - -/* - * definitions for HSSI - */ -#define LMC_MII16_HSSI_TA 0x0001 -#define LMC_MII16_HSSI_CA 0x0002 -#define LMC_MII16_HSSI_LA 0x0004 -#define LMC_MII16_HSSI_LB 0x0008 -#define LMC_MII16_HSSI_LC 0x0010 -#define LMC_MII16_HSSI_TM 0x0020 -#define LMC_MII16_HSSI_CRC 0x0040 - -/* - * assignments for the MII register 16 (DS3) - */ -#define LMC_MII16_DS3_ZERO 0x0001 -#define LMC_MII16_DS3_TRLBK 0x0002 -#define LMC_MII16_DS3_LNLBK 0x0004 -#define LMC_MII16_DS3_RAIS 0x0008 -#define LMC_MII16_DS3_TAIS 0x0010 -#define LMC_MII16_DS3_BIST 0x0020 -#define LMC_MII16_DS3_DLOS 0x0040 -#define LMC_MII16_DS3_CRC 0x1000 -#define LMC_MII16_DS3_SCRAM 0x2000 - -/* Note: 2 pairs of LEDs where swapped by mistake - * in Xilinx code for DS3 & DS1 adapters */ -#define LMC_DS3_LED0 0x0100 /* bit 08 yellow */ -#define LMC_DS3_LED1 0x0080 /* bit 07 blue */ -#define LMC_DS3_LED2 0x0400 /* bit 10 green */ -#define LMC_DS3_LED3 0x0200 /* bit 09 red */ - -/* - * framer register 0 and 7 (7 is latched and reset on read) - */ -#define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */ -#define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */ -#define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */ -#define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */ -#define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */ - -/* - * And SSI, LMC1000 - */ -#define LMC_MII16_SSI_DTR 0x0001 /* DTR output RW */ -#define LMC_MII16_SSI_DSR 0x0002 /* DSR input RO */ -#define LMC_MII16_SSI_RTS 0x0004 /* RTS output RW */ -#define LMC_MII16_SSI_CTS 0x0008 /* CTS input RO */ -#define LMC_MII16_SSI_DCD 0x0010 /* DCD input RO */ -#define LMC_MII16_SSI_RI 0x0020 /* RI input RO */ -#define LMC_MII16_SSI_CRC 0x1000 /* CRC select - RW */ - -/* - * bits 0x0080 through 0x0800 are generic, and described - * above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET - */ -#define LMC_MII16_SSI_LL 0x1000 /* LL output RW */ -#define LMC_MII16_SSI_RL 0x2000 /* RL output RW */ -#define LMC_MII16_SSI_TM 0x4000 /* TM input RO */ -#define LMC_MII16_SSI_LOOP 0x8000 /* loopback enable RW */ - -/* - * Some of the MII16 bits are mirrored in the MII17 register as well, - * but let's keep thing separate for now, and get only the cable from - * the MII17. - */ -#define LMC_MII17_SSI_CABLE_MASK 0x0038 /* mask to extract the cable type */ -#define LMC_MII17_SSI_CABLE_SHIFT 3 /* shift to extract the cable type */ - -/* - * And T1, LMC1200 - */ -#define LMC_MII16_T1_UNUSED1 0x0003 -#define LMC_MII16_T1_XOE 0x0004 -#define LMC_MII16_T1_RST 0x0008 /* T1 chip reset - RW */ -#define LMC_MII16_T1_Z 0x0010 /* output impedance T1=1, E1=0 output - RW */ -#define LMC_MII16_T1_INTR 0x0020 /* interrupt from 8370 - RO */ -#define LMC_MII16_T1_ONESEC 0x0040 /* one second square wave - ro */ - -#define LMC_MII16_T1_LED0 0x0100 -#define LMC_MII16_T1_LED1 0x0080 -#define LMC_MII16_T1_LED2 0x0400 -#define LMC_MII16_T1_LED3 0x0200 -#define LMC_MII16_T1_FIFO_RESET 0x0800 - -#define LMC_MII16_T1_CRC 0x1000 /* CRC select - RW */ -#define LMC_MII16_T1_UNUSED2 0xe000 - -/* 8370 framer registers */ - -#define T1FRAMER_ALARM1_STATUS 0x47 -#define T1FRAMER_ALARM2_STATUS 0x48 -#define T1FRAMER_FERR_LSB 0x50 -#define T1FRAMER_FERR_MSB 0x51 /* framing bit error counter */ -#define T1FRAMER_LCV_LSB 0x54 -#define T1FRAMER_LCV_MSB 0x55 /* line code violation counter */ -#define T1FRAMER_AERR 0x5A - -/* mask for the above AERR register */ -#define T1FRAMER_LOF_MASK (0x0f0) /* receive loss of frame */ -#define T1FRAMER_COFA_MASK (0x0c0) /* change of frame alignment */ -#define T1FRAMER_SEF_MASK (0x03) /* severely errored frame */ - -/* 8370 framer register ALM1 (0x47) values - * used to determine link status - */ - -#define T1F_SIGFRZ 0x01 /* signaling freeze */ -#define T1F_RLOF 0x02 /* receive loss of frame alignment */ -#define T1F_RLOS 0x04 /* receive loss of signal */ -#define T1F_RALOS 0x08 /* receive analog loss of signal or RCKI loss of clock */ -#define T1F_RAIS 0x10 /* receive alarm indication signal */ -#define T1F_UNUSED 0x20 -#define T1F_RYEL 0x40 /* receive yellow alarm */ -#define T1F_RMYEL 0x80 /* receive multiframe yellow alarm */ - -/* ------------------ end T1 defs ------------------- */ - -#define LMC_MII_LedMask 0x0780 -#define LMC_MII_LedBitPos 7 - -#if defined(_KERNEL) -/* - * media independent methods to check on media status, link, light LEDs, - * etc. - */ -struct lmc___media { - void (* init)(lmc_softc_t * const); - void (* defaults)(lmc_softc_t * const); - void (* set_status)(lmc_softc_t * const, lmc_ctl_t *); - void (* set_clock_source)(lmc_softc_t * const, int); - void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *); - void (* set_cable_length)(lmc_softc_t * const, int); - void (* set_scrambler)(lmc_softc_t * const, int); - int (* get_link_status)(lmc_softc_t * const); - void (* set_link_status)(lmc_softc_t * const, int); - void (* set_crc_length)(lmc_softc_t * const, int); - void (* set_circuit_type)(lmc_softc_t * const, int); - void (* watchdog)(lmc_softc_t * const); -}; - -u_int32_t lmc_mii_readreg(lmc_softc_t * const sc, u_int32_t devaddr, - u_int32_t regno); -void lmc_mii_writereg(lmc_softc_t * const sc, u_int32_t devaddr, - u_int32_t regno, u_int32_t data); -void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, - size_t csr_size); -void lmc_dec_reset(lmc_softc_t * const sc); -void lmc_reset(lmc_softc_t * const sc); -void lmc_led_on(lmc_softc_t * const sc, u_int32_t led); -void lmc_led_off(lmc_softc_t * const sc, u_int32_t led); -void lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits); -void lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits); -lmc_intrfunc_t lmc_intr_normal(void *); -int lmc_read_macaddr(lmc_softc_t * const sc); -void lmc_attach(lmc_softc_t * const sc); -void lmc_initring(lmc_softc_t * const sc, lmc_ringinfo_t * const ri, - lmc_desc_t *descs, int ndescs); -#endif /* _KERNEL */ diff --git a/sys/dev/pci/if_lmcvar.h b/sys/dev/pci/if_lmcvar.h deleted file mode 100644 index fa5a5764251..00000000000 --- a/sys/dev/pci/if_lmcvar.h +++ /dev/null @@ -1,575 +0,0 @@ -/* $OpenBSD: if_lmcvar.h,v 1.12 2015/02/10 03:51:58 mpi Exp $ */ -/* $NetBSD: if_lmcvar.h,v 1.1 1999/03/25 03:32:43 explorer Exp $ */ - -/*- - * Copyright (c) 1997-1999 LAN Media Corporation (LMC) - * All rights reserved. www.lanmedia.com - * - * This code is written by Michael Graff for LMC. - * The code is derived from permitted modifications to software created - * by Matt Thomas (matt@3am-software.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. All marketing or advertising materials mentioning features or - * use of this software must display the following acknowledgement: - * This product includes software developed by LAN Media Corporation - * and its contributors. - * 4. Neither the name of LAN Media Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define LMC_MTU 1500 -#define PPP_HEADER_LEN 4 -#define BIG_PACKET -#define LMC_DATA_PER_DESC 2032 - -/* - * This turns on all sort of debugging stuff and make the - * driver much larger. - */ -#if 0 -#define LMC_DEBUG -typedef enum { - LMC_21040_GENERIC, /* Generic 21040 (works with most any board) */ - LMC_21140_ISV, /* Digital Semicondutor 21140 ISV SROM Format */ - LMC_21142_ISV, /* Digital Semicondutor 21142 ISV SROM Format */ - LMC_21143_ISV, /* Digital Semicondutor 21143 ISV SROM Format */ - LMC_21140_DEC_EB, /* Digital Semicondutor 21140 Evaluation Board */ - LMC_21140_MII, /* 21140[A] with MII */ - LMC_21140_DEC_DE500, /* Digital DE500-?? 10/100 */ - LMC_21140_SMC_9332, /* SMC 9332 */ - LMC_21140_COGENT_EM100, /* Cogent EM100 100 only */ - LMC_21140_ZNYX_ZX34X, /* ZNYX ZX342 10/100 */ - LMC_21140_ASANTE, /* AsanteFast 10/100 */ - LMC_21140_EN1207, /* Accton EN2107 10/100 BNC */ - LMC_21041_GENERIC /* Generic 21041 card */ -} lmc_board_t; - -typedef enum { - LMC_MEDIAPOLL_TIMER, /* 100ms timer fired */ - LMC_MEDIAPOLL_FASTTIMER, /* <100ms timer fired */ - LMC_MEDIAPOLL_LINKFAIL, /* called from interrupt routine */ - LMC_MEDIAPOLL_LINKPASS, /* called from interrupt routine */ - LMC_MEDIAPOLL_START, /* start a media probe (called from reset) */ - LMC_MEDIAPOLL_TXPROBE_OK, /* txprobe succeeded */ - LMC_MEDIAPOLL_TXPROBE_FAILED, /* txprobe failed */ - LMC_MEDIAPOLL_MAX -} lmc_mediapoll_event_t; -#define DP(x) printf x -#else -#define DP(x) -#endif - -/* - * the dec chip has its own idea of what a receive error is, but we don't - * want to use it, as it will get the crc error wrong when 16-bit - * crcs are used. So, we only care about certain conditions. - */ -#ifndef TULIP_DSTS_RxMIIERR -#define TULIP_DSTS_RxMIIERR 0x00000008 -#endif -#define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR) - -/* - * This is the PCI configuration support. - */ -#define PCI_CFID 0x00 /* Configuration ID */ -#define PCI_CFCS 0x04 /* Configurtion Command/Status */ -#define PCI_CFRV 0x08 /* Configuration Revision */ -#define PCI_CFLT 0x0c /* Configuration Latency Timer */ -#define PCI_CBIO 0x10 /* Configuration Base IO Address */ -#define PCI_CBMA 0x14 /* Configuration Base Memory Address */ -#define PCI_SSID 0x2c /* subsystem config register */ -#define PCI_CFIT 0x3c /* Configuration Interrupt */ -#define PCI_CFDA 0x40 /* Configuration Driver Area */ - -#define LMC_HZ 10 - -#ifndef TULIP_GP_PINSET -#define TULIP_GP_PINSET 0x00000100L -#endif -#ifndef TULIP_BUSMODE_READMULTIPLE -#define TULIP_BUSMODE_READMULTIPLE 0x00200000L -#endif - -#define LMC_CSR_READ(sc, csr) \ - bus_space_read_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr) -#define LMC_CSR_WRITE(sc, csr, val) \ - bus_space_write_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val)) - -#define LMC_CSR_READBYTE(sc, csr) \ - bus_space_read_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr) -#define LMC_CSR_WRITEBYTE(sc, csr, val) \ - bus_space_write_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val)) - -#define LMC_PCI_CSRSIZE 8 -#define LMC_PCI_CSROFFSET 0 - -/* - * This structure contains "pointers" for the registers on - * the various 21x4x chips. - */ -typedef struct { - lmc_csrptr_t csr_busmode; /* CSR0 */ - lmc_csrptr_t csr_txpoll; /* CSR1 */ - lmc_csrptr_t csr_rxpoll; /* CSR2 */ - lmc_csrptr_t csr_rxlist; /* CSR3 */ - lmc_csrptr_t csr_txlist; /* CSR4 */ - lmc_csrptr_t csr_status; /* CSR5 */ - lmc_csrptr_t csr_command; /* CSR6 */ - lmc_csrptr_t csr_intr; /* CSR7 */ - lmc_csrptr_t csr_missed_frames; /* CSR8 */ - lmc_csrptr_t csr_9; /* CSR9 */ - lmc_csrptr_t csr_10; /* CSR10 */ - lmc_csrptr_t csr_11; /* CSR11 */ - lmc_csrptr_t csr_12; /* CSR12 */ - lmc_csrptr_t csr_13; /* CSR13 */ - lmc_csrptr_t csr_14; /* CSR14 */ - lmc_csrptr_t csr_15; /* CSR15 */ -} lmc_regfile_t; - -#define csr_enetrom csr_9 /* 21040 */ -#define csr_reserved csr_10 /* 21040 */ -#define csr_full_duplex csr_11 /* 21040 */ -#define csr_bootrom csr_10 /* 21041/21140A/?? */ -#define csr_gp csr_12 /* 21140* */ -#define csr_watchdog csr_15 /* 21140* */ -#define csr_gp_timer csr_11 /* 21041/21140* */ -#define csr_srom_mii csr_9 /* 21041/21140* */ -#define csr_sia_status csr_12 /* 2104x */ -#define csr_sia_connectivity csr_13 /* 2104x */ -#define csr_sia_tx_rx csr_14 /* 2104x */ -#define csr_sia_general csr_15 /* 2104x */ - -/* - * While 21x4x allows chaining of its descriptors, this driver - * doesn't take advantage of it. We keep the descriptors in a - * traditional FIFO ring. - */ -struct lmc_ringinfo { - lmc_desc_t *ri_first; /* first entry in ring */ - lmc_desc_t *ri_last; /* one after last entry */ - lmc_desc_t *ri_nextin; /* next to processed by host */ - lmc_desc_t *ri_nextout; /* next to processed by adapter */ - int ri_max; - int ri_free; -}; - -/* - * The 21040 has a stupid restriction in that the receive - * buffers must be longword aligned. But since Ethernet - * headers are not a multiple of longwords in size this forces - * the data to non-longword aligned. Since IP requires the - * data to be longword aligned, we need to copy it after it has - * been DMA'ed in our memory. - * - * Since we have to copy it anyways, we might as well as allocate - * dedicated receive space for the input. This allows to use a - * small receive buffer size and more ring entries to be able to - * better keep with a flood of tiny Ethernet packets. - * - * The receive space MUST ALWAYS be a multiple of the page size. - * And the number of receive descriptors multiplied by the size - * of the receive buffers must equal the recevive space. This - * is so that we can manipulate the page tables so that even if a - * packet wraps around the end of the receive space, we can - * treat it as virtually contiguous. - * - * The above used to be true (the stupid restriction is still true) - * but we gone to directly DMA'ing into MBUFs (unless it's on an - * architecture which can't handle unaligned accesses) because with - * 100Mb/s cards the copying is just too much of a hit. - */ - -#define LMC_RXDESCS 48 -#define LMC_TXDESCS 128 -#define LMC_RXQ_TARGET 32 -#if LMC_RXQ_TARGET >= LMC_RXDESCS -#error LMC_RXQ_TARGET must be less than LMC_RXDESCS -#endif - -#define LMC_RX_BUFLEN ((MCLBYTES < 2048 ? MCLBYTES : 2048) - 16) - -#define LMC_LINK_UP 1 -#define LMC_LINK_DOWN 0 - -typedef enum { - LMC_21140, LMC_21140A, - LMC_CHIPID_UNKNOWN -} lmc_chipid_t; - -#define LMC_BIT(b) (1L << ((int)(b))) - -typedef struct { - /* - * Transmit Statistics - */ - u_int32_t dot3StatsSingleCollisionFrames; - u_int32_t dot3StatsMultipleCollisionFrames; - u_int32_t dot3StatsSQETestErrors; - u_int32_t dot3StatsDeferredTransmissions; - u_int32_t dot3StatsLateCollisions; - u_int32_t dot3StatsExcessiveCollisions; - u_int32_t dot3StatsCarrierSenseErrors; - u_int32_t dot3StatsInternalMacTransmitErrors; - u_int32_t dot3StatsInternalTransmitUnderflows; /* not in rfc1650! */ - u_int32_t dot3StatsInternalTransmitBabbles; /* not in rfc1650! */ - /* - * Receive Statistics - */ - u_int32_t dot3StatsMissedFrames; /* not in rfc1650! */ - u_int32_t dot3StatsAlignmentErrors; - u_int32_t dot3StatsFCSErrors; - u_int32_t dot3StatsFrameTooLongs; - u_int32_t dot3StatsInternalMacReceiveErrors; -} lmc_dot3_stats_t; - -/* - * Now to important stuff. This is softc structure (where does softc - * come from??? No idea) for the tulip device. - * - */ -struct lmc___softc { - struct device lmc_dev; /* base device */ - void *lmc_ih; /* interrupt vectoring */ - void *lmc_ats; /* shutdown hook */ - bus_space_tag_t lmc_bustag; - bus_space_handle_t lmc_bushandle; /* CSR region handle */ - pci_chipset_tag_t lmc_pc; - - struct sppp lmc_sppp; -#define lmc_if lmc_sppp.pp_if - - u_int8_t lmc_enaddr[6]; /* yes, a small hack... */ - lmc_regfile_t lmc_csrs; - volatile u_int32_t lmc_txtick; - volatile u_int32_t lmc_rxtick; - u_int32_t lmc_flags; - - u_int32_t lmc_features; /* static bits indicating features of chip */ - u_int32_t lmc_intrmask; /* our copy of csr_intr */ - u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */ - u_int32_t lmc_last_system_error : 3; /* last system error (only value is LMC_SYSTEMERROR is also set) */ - u_int32_t lmc_system_errors; /* number of system errors encountered */ - u_int32_t lmc_statusbits; /* status bits from CSR5 that may need to be printed */ - - u_int8_t lmc_revinfo; /* revision of chip */ - u_int8_t lmc_cardtype; /* LMC_CARDTYPE_HSSI or ..._DS3 */ - u_int32_t lmc_gpio_io; /* state of in/out settings */ - u_int32_t lmc_gpio; /* state of outputs */ - u_int8_t lmc_gp; - - lmc_chipid_t lmc_chipid; /* type of chip we are using */ - u_int32_t lmc_miireg16; - struct ifqueue lmc_txq; - struct ifqueue lmc_rxq; - lmc_dot3_stats_t lmc_dot3stats; - lmc_ringinfo_t lmc_rxinfo; - lmc_ringinfo_t lmc_txinfo; - u_int8_t lmc_rombuf[128]; - lmc_media_t *lmc_media; - lmc_ctl_t ictl; - - bus_dma_tag_t lmc_dmatag; /* bus DMA tag */ - bus_dmamap_t lmc_setupmap; - bus_dmamap_t lmc_txdescmap; - bus_dmamap_t lmc_txmaps[LMC_TXDESCS]; - unsigned lmc_txmaps_free; - bus_dmamap_t lmc_rxdescmap; - bus_dmamap_t lmc_rxmaps[LMC_RXDESCS]; - unsigned lmc_rxmaps_free; - - struct device *lmc_pci_busno; /* needed for multiport boards */ - u_int8_t lmc_pci_devno; /* needed for multiport boards */ - lmc_desc_t *lmc_rxdescs; - lmc_desc_t *lmc_txdescs; - - u_int32_t lmc_crcSize; - u_int32_t tx_clockState; - char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */ - char lmc_timing; /* for HSSI and SSI */ - u_int16_t t1_alarm1_status; - u_int16_t t1_alarm2_status; -#if defined(LMC_DEBUG) - /* - * Debugging/Statistical information - */ - struct { - lmc_media_t dbg_last_media; - u_int32_t dbg_intrs; - u_int32_t dbg_media_probes; - u_int32_t dbg_txprobe_nocarr; - u_int32_t dbg_txprobe_exccoll; - u_int32_t dbg_link_downed; - u_int32_t dbg_link_suspected; - u_int32_t dbg_link_intrs; - u_int32_t dbg_link_pollintrs; - u_int32_t dbg_link_failures; - u_int32_t dbg_nway_starts; - u_int32_t dbg_nway_failures; - u_int16_t dbg_phyregs[32][4]; - u_int32_t dbg_rxlowbufs; - u_int32_t dbg_rxintrs; - u_int32_t dbg_last_rxintrs; - u_int32_t dbg_high_rxintrs_hz; - u_int32_t dbg_no_txmaps; - u_int32_t dbg_txput_finishes[8]; - u_int32_t dbg_txprobes_ok; - u_int32_t dbg_txprobes_failed; - u_int32_t dbg_events[LMC_MEDIAPOLL_MAX]; - u_int32_t dbg_rxpktsperintr[LMC_RXDESCS]; - } lmc_dbg; -#endif -}; - -/* - * lmc_flags - */ -#define LMC_IFUP 0x00000001 -#define LMC_00000002 0x00000002 -#define LMC_00000004 0x00000004 -#define LMC_00000008 0x00000008 -#define LMC_00000010 0x00000010 -#define LMC_MODEMOK 0x00000020 -#define LMC_00000040 0x00000040 -#define LMC_00000080 0x00000080 -#define LMC_RXACT 0x00000100 -#define LMC_INRESET 0x00000200 -#define LMC_NEEDRESET 0x00000400 -#define LMC_00000800 0x00000800 -#define LMC_00001000 0x00001000 -#define LMC_00002000 0x00002000 -#define LMC_WANTTXSTART 0x00004000 -#define LMC_NEWTXTHRESH 0x00008000 -#define LMC_NOAUTOSENSE 0x00010000 -#define LMC_PRINTLINKUP 0x00020000 -#define LMC_LINKUP 0x00040000 -#define LMC_RXBUFSLOW 0x00080000 -#define LMC_NOMESSAGES 0x00100000 -#define LMC_SYSTEMERROR 0x00200000 -#define LMC_TIMEOUTPENDING 0x00400000 -#define LMC_00800000 0x00800000 -#define LMC_01000000 0x01000000 -#define LMC_02000000 0x02000000 -#define LMC_RXIGNORE 0x04000000 -#define LMC_08000000 0x08000000 -#define LMC_10000000 0x10000000 -#define LMC_20000000 0x20000000 -#define LMC_40000000 0x40000000 -#define LMC_80000000 0x80000000 - -/* - * lmc_features - */ -#define LMC_HAVE_GPR 0x00000001 /* have gp register (140[A]) */ -#define LMC_HAVE_RXBADOVRFLW 0x00000002 /* RX corrupts on overflow */ -#define LMC_HAVE_POWERMGMT 0x00000004 /* Snooze/sleep modes */ -#define LMC_HAVE_MII 0x00000008 /* Some medium on MII */ -#define LMC_HAVE_SIANWAY 0x00000010 /* SIA does NWAY */ -#define LMC_HAVE_DUALSENSE 0x00000020 /* SIA senses both AUI & TP */ -#define LMC_HAVE_SIAGP 0x00000040 /* SIA has a GP port */ -#define LMC_HAVE_BROKEN_HASH 0x00000080 /* Broken Multicast Hash */ -#define LMC_HAVE_ISVSROM 0x00000100 /* uses ISV SROM Format */ -#define LMC_HAVE_BASEROM 0x00000200 /* Board ROM can be cloned */ -#define LMC_HAVE_SLAVEDROM 0x00000400 /* Board ROM cloned */ -#define LMC_HAVE_SLAVEDINTR 0x00000800 /* Board slaved interrupt */ -#define LMC_HAVE_SHAREDINTR 0x00001000 /* Board shares interrupts */ -#define LMC_HAVE_OKROM 0x00002000 /* ROM was recognized */ -#define LMC_HAVE_NOMEDIA 0x00004000 /* did not detect any media */ -#define LMC_HAVE_STOREFWD 0x00008000 /* have CMD_STOREFWD */ -#define LMC_HAVE_SIA100 0x00010000 /* has LS100 in SIA status */ - -#if 0 -static const char * const lmc_status_bits[] = { - NULL, - "transmit process stopped", - NULL, - "transmit jabber timeout", - - NULL, - "transmit underflow", - NULL, - "receive underflow", - - "receive process stopped", - "receive watchdog timeout", - NULL, - NULL, - - "link failure", - NULL, - NULL, -}; -#endif - -/* - * This driver supports a maximum of 32 devices. - */ -#define LMC_MAX_DEVICES 32 - -#define LMC_RXDESC_PRESYNC(sc, di, s) \ - bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_rxdescmap, \ - (caddr_t) di - (caddr_t) (sc)->lmc_rxdescs, \ - (s), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define LMC_RXDESC_POSTSYNC(sc, di, s) \ - bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_rxdescmap, \ - (caddr_t) di - (caddr_t) (sc)->lmc_rxdescs, \ - (s), BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) -#define LMC_RXMAP_PRESYNC(sc, map) \ - bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \ - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define LMC_RXMAP_POSTSYNC(sc, map) \ - bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \ - BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) -#define LMC_RXMAP_CREATE(sc, mapp) \ - bus_dmamap_create((sc)->lmc_dmatag, LMC_RX_BUFLEN, 2, \ - LMC_DATA_PER_DESC, 0, \ - BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, (mapp)) - -#define LMC_TXDESC_PRESYNC(sc, di, s) \ - bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_txdescmap, \ - (caddr_t) di - (caddr_t) (sc)->lmc_txdescs, \ - (s), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define LMC_TXDESC_POSTSYNC(sc, di, s) \ - bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_txdescmap, \ - (caddr_t) di - (caddr_t) (sc)->lmc_txdescs, \ - (s), BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) -#define LMC_TXMAP_PRESYNC(sc, map) \ - bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \ - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define LMC_TXMAP_POSTSYNC(sc, map) \ - bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \ - BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) -#define LMC_TXMAP_CREATE(sc, mapp) \ - bus_dmamap_create((sc)->lmc_dmatag, LMC_DATA_PER_DESC, \ - LMC_MAX_TXSEG, LMC_DATA_PER_DESC, \ - 0, BUS_DMA_NOWAIT, (mapp)) - -typedef void ifnet_ret_t; -typedef u_long ioctl_cmd_t; -extern struct cfattach lmc_ca; -extern struct cfdriver lmc_cd; -#define LMC_UNIT_TO_SOFTC(unit) ((lmc_softc_t *) lmc_cd.cd_devs[unit]) -#define LMC_IFP_TO_SOFTC(ifp) ((lmc_softc_t *)((ifp)->if_softc)) -#define lmc_unit lmc_dev.dv_unit -#define lmc_xname lmc_if.if_xname -#define LMC_RAISESPL() splnet() -#define LMC_RAISESOFTSPL() splsoftnet() -#define LMC_RESTORESPL(s) splx(s) -/* #define lmc_enaddr lmc_enaddr */ -#define loudprintf printf -#define LMC_PRINTF_FMT "%s" -#define LMC_PRINTF_ARGS sc->lmc_xname - -#ifndef LMC_PRINTF_FMT -#define LMC_PRINTF_FMT "%s%d" -#endif -#ifndef LMC_PRINTF_ARGS -#define LMC_PRINTF_ARGS sc->lmc_name, sc->lmc_unit -#endif - -#ifndef LMC_BURSTSIZE -#define LMC_BURSTSIZE(unit) 3 -#endif - -#ifndef lmc_unit -#define lmc_unit lmc_sppp.pp_if.if_unit -#endif - -#ifndef lmc_name -#define lmc_name lmc_sppp.pp_if.if_name -#endif - -#if !defined(lmc_bpf) -#define lmc_bpf lmc_sppp.pp_if.if_bpf -#endif - -#ifndef LMC_RAISESPL -#define LMC_RAISESPL() splnet() -#endif -#ifndef LMC_RAISESOFTSPL -#define LMC_RAISESOFTSPL() splnet() -#endif -#ifndef TULUP_RESTORESPL -#define LMC_RESTORESPL(s) splx(s) -#endif - -/* - * While I think FreeBSD's 2.2 change to the bpf is a nice simplification, - * it does add yet more conditional code to this driver. Sigh. - */ -#if !defined(LMC_BPF_MTAP) && NBPFILTER > 0 -#define LMC_BPF_MTAP(sc, m, d) bpf_mtap((sc)->lmc_bpf, m, d) -#define LMC_BPF_TAP(sc, p, l, d) bpf_tap((sc)->lmc_bpf, p, l, d) -#define LMC_BPF_ATTACH(sc) bpfattach(&(sc)->lmc_bpf, &(sc)->lmc_sppp.pp_if, DLT_PPP, PPP_HEADER_LEN) -#endif - -/* - * However, this change to FreeBSD I am much less enamored with. - */ -#if !defined(LMC_EADDR_FMT) -#define LMC_EADDR_FMT "%s" -#define LMC_EADDR_ARGS(addr) ether_sprintf(addr) -#endif - -#define LMC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */ -#define LMC_MAX_TXSEG 30 - -#define LMC_ADDREQUAL(a1, a2) \ - (((u_int16_t *)a1)[0] == ((u_int16_t *)a2)[0] \ - && ((u_int16_t *)a1)[1] == ((u_int16_t *)a2)[1] \ - && ((u_int16_t *)a1)[2] == ((u_int16_t *)a2)[2]) -#define LMC_ADDRBRDCST(a1) \ - (((u_int16_t *)a1)[0] == 0xFFFFU \ - && ((u_int16_t *)a1)[1] == 0xFFFFU \ - && ((u_int16_t *)a1)[2] == 0xFFFFU) - -typedef int lmc_spl_t; - -#define LMC_GETCTX(m, t) ((t) (m)->m_pkthdr.ph_cookie + 0) -#define LMC_SETCTX(m, c) ((void) ((m)->m_pkthdr.ph_cookie = (void *)(c))) diff --git a/sys/dev/pci/if_san_common.c b/sys/dev/pci/if_san_common.c deleted file mode 100644 index d5b8ccc6534..00000000000 --- a/sys/dev/pci/if_san_common.c +++ /dev/null @@ -1,467 +0,0 @@ -/* $OpenBSD: if_san_common.c,v 1.21 2014/12/05 15:50:04 mpi Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - - -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include -# include - -#ifdef _DEBUG_ -#define STATIC -#else -#define STATIC static -#endif - -/* WAN link driver entry points */ -#if 0 -static int shutdown(sdla_t *card); -#endif - -/* Miscellaneous functions */ -static int wan_ioctl(struct ifnet*, u_long, struct ifreq *); -static int sdla_isr(void *); - -static void release_hw(sdla_t *card); - -static int wan_ioctl_dump(sdla_t *, void *); -static int wan_ioctl_hwprobe(struct ifnet *, void *); - -/* - * Global Data - * Note: All data must be explicitly initialized!!! - */ - -/* private data */ -extern char *san_drvname; -LIST_HEAD(, sdla) wan_cardlist = LIST_HEAD_INITIALIZER(wan_cardlist); - -#if 0 -static san_detach(void) -{ - wanpipe_common_t *common; - sdla_t *card, *tmp_card; - int err = 0; - - card = LIST_FIRST(&wan_cardlist); - while (card) { - if (card->disable_comm) - card->disable_comm(card); - - while ((common = LIST_FIRST(&card->dev_head))) { - LIST_REMOVE(common, next); - if (card->del_if) { - struct ifnet *ifp = - (struct ifnet*)&common->ifp; - log(LOG_INFO, "%s: Deleting interface...\n", - ifp->if_xname); - card->del_if(card, ifp); - } - } - log(LOG_INFO, "%s: Shutdown device\n", card->devname); - shutdown(card); - tmp_card = card; - card = LIST_NEXT(card, next); - LIST_REMOVE(tmp_card, next); - free(tmp_card, M_DEVBUF, 0); - } - - log(LOG_INFO, "\n"); - log(LOG_INFO, "%s: WANPIPE Generic Modules Unloaded.\n", - san_drvname); - - err = sdladrv_exit(); - return err; -} -#endif - - -int -san_dev_attach(void *hw, u_int8_t *devname, int namelen) -{ - sdla_t *card; - wanpipe_common_t *common = NULL; - int err = 0; - - card = malloc(sizeof(*card), M_DEVBUF, M_NOWAIT | M_ZERO); - if (!card) { - log(LOG_INFO, "%s: Failed allocate new card!\n", - san_drvname); - return (EINVAL); - } - card->magic = WANPIPE_MAGIC; - wanpipe_generic_name(card, card->devname, sizeof(card->devname)); - strlcpy(devname, card->devname, namelen); - card->hw = hw; - LIST_INIT(&card->dev_head); - - sdla_getcfg(card->hw, SDLA_CARDTYPE, &card->type); - if (sdla_is_te1(card->hw)) - sdla_te_defcfg(&card->fe_te.te_cfg); - - err = sdla_setup(card->hw); - if (err) { - log(LOG_INFO, "%s: Hardware setup Failed %d\n", - card->devname,err); - return (EINVAL); - } - err = sdla_intr_establish(card->hw, sdla_isr, (void*)card); - if (err) { - log(LOG_INFO, "%s: Failed set interrupt handler!\n", - card->devname); - sdla_down(card->hw); - return (EINVAL); - } - - switch (card->type) { - case SDLA_AFT: -#if defined(DEBUG_INIT) - log(LOG_INFO, "%s: Starting AFT Hardware Init.\n", - card->devname); -#endif - common = wan_xilinx_init(card); - break; - } - if (common == NULL) { - release_hw(card); - card->configured = 0; - return (EINVAL); - } - LIST_INSERT_HEAD(&card->dev_head, common, next); - - /* Reserve I/O region and schedule background task */ - card->critical = 0; - card->state = WAN_DISCONNECTED; - card->ioctl = wan_ioctl; - return (0); -} - - -/* - * Shut down WAN link driver. - * o shut down adapter hardware - * o release system resources. - * - */ -#if 0 -static int -shutdown (sdla_t *card) -{ - int err=0; - - if (card->state == WAN_UNCONFIGURED) { - return 0; - } - card->state = WAN_UNCONFIGURED; - - bit_set((u_int8_t*)&card->critical, PERI_CRIT); - - /* In case of piggibacking, make sure that - * we never try to shutdown both devices at the same - * time, because they depend on one another */ - - card->state = WAN_UNCONFIGURED; - - /* Release Resources */ - release_hw(card); - - /* only free the allocated I/O range if not an S514 adapter */ - if (!card->configured) { - card->hw = NULL; - if (card->same_cpu) { - card->same_cpu->hw = NULL; - card->same_cpu->same_cpu = NULL; - card->same_cpu=NULL; - } - } - - bit_clear((u_int8_t*)&card->critical, PERI_CRIT); - - return err; -} -#endif - -static void -release_hw(sdla_t *card) -{ - log(LOG_INFO, "%s: Master shutting down\n",card->devname); - sdla_down(card->hw); - sdla_intr_disestablish(card->hw); - card->configured = 0; - return; -} - - -/* - * Driver IOCTL Handlers - */ - -static int -wan_ioctl(struct ifnet *ifp, u_long cmd, struct ifreq *ifr) -{ - wanpipe_common_t *common = WAN_IFP_TO_COMMON(ifp); - int err; - - SAN_ASSERT(common == NULL); - SAN_ASSERT(common->card == NULL); - - if ((err = suser(curproc, 0)) != 0) - return err; - - switch (cmd) { - case SIOC_WANPIPE_HWPROBE: - err = wan_ioctl_hwprobe(ifp, ifr->ifr_data); - break; - - case SIOC_WANPIPE_DUMP: - err = wan_ioctl_dump(common->card, ifr->ifr_data); - break; - - default: - err = ENOTTY; - break; - } - return err; -} - -static int -wan_ioctl_hwprobe(struct ifnet *ifp, void *u_def) -{ - sdla_t *card = NULL; - wanpipe_common_t *common = WAN_IFP_TO_COMMON(ifp); - wanlite_def_t def; - unsigned char *str; - int err; - - SAN_ASSERT(common == NULL); - SAN_ASSERT(common->card == NULL); - card = common->card; - bzero(&def, sizeof(wanlite_def_t)); - /* Get protocol type */ - def.proto = common->protocol; - - /* Get hardware configuration */ - err = sdla_get_hwprobe(card->hw, (void**)&str); - if (err) - return EINVAL; - - strlcpy(def.hwprobe, str, sizeof(def.hwprobe)); - /* Get interface configuration */ - if (IS_TE1(&card->fe_te.te_cfg)) { - if (IS_T1(&card->fe_te.te_cfg)) - def.iface = IF_IFACE_T1; - else - def.iface = IF_IFACE_E1; - - bcopy(&card->fe_te.te_cfg, &def.te_cfg, sizeof(sdla_te_cfg_t)); - } - - err = copyout(&def, u_def, sizeof(def)); - if (err) { - log(LOG_INFO, "%s: Failed to copy to user space (%d)\n", - card->devname, __LINE__); - return ENOMEM; - } - return 0; -} - -static int -wan_ioctl_dump(sdla_t *card, void *u_dump) -{ - sdla_dump_t dump; - void* data; - u_int32_t memory; - int err = 0; - - err = copyin(u_dump, &dump, sizeof(sdla_dump_t)); - if (err) - return err; - - sdla_getcfg(card->hw, SDLA_MEMORY, &memory); - if (dump.magic != WANPIPE_MAGIC) - return EINVAL; - - if ((dump.offset + dump.length) > memory) - return EINVAL; - - data = malloc(dump.length, M_DEVBUF, M_NOWAIT); - if (data == NULL) - return ENOMEM; - - sdla_peek(card->hw, dump.offset, data, dump.length); - err = copyout(data, dump.ptr, dump.length); - if (err) { - log(LOG_INFO, "%s: Failed to copy to user space (%d)\n", - card->devname, __LINE__); - } - free(data, M_DEVBUF, 0); - return err; -} - - -/* - * SDLA Interrupt Service Routine. - * o call protocol-specific interrupt service routine, if any. - */ -int -sdla_isr(void *pcard) -{ - sdla_t *card = (sdla_t*)pcard; - - if (card == NULL || card->magic != WANPIPE_MAGIC) - return 0; - - switch (card->type) { - case SDLA_AFT: - if (card->isr) - card->isr(card); - break; - } - return (1); -} - -struct mbuf* -wan_mbuf_alloc(int len) -{ - struct mbuf *m; - - /* XXX handle len > MCLBYTES */ - if (len <= 0 || len > MCLBYTES) - return (NULL); - - MGETHDR(m, M_DONTWAIT, MT_DATA); - - if (m == NULL || len <= MHLEN) - return (m); - - m->m_pkthdr.len = len; - m->m_len = len; - MCLGET(m, M_DONTWAIT); - - if ((m->m_flags & M_EXT) == 0) { - m_freem(m); - return (NULL); - } - - return (m); -} - -int -wan_mbuf_to_buffer(struct mbuf **m_org) -{ - struct mbuf *m, *m0, *tmp; - char *buffer; - size_t len; - - if (m_org == NULL || *m_org == NULL) - return (EINVAL); - - m0 = *m_org; -#if 0 - /* no need to copy if it is a single, properly aligned mbuf */ - if (m0->m_next == NULL && (mtod(m0, u_int32_t) & 0x03) == 0) - return (0); -#endif - MGET(m, M_DONTWAIT, MT_DATA); - - if (m == NULL) - return (ENOMEM); - - MCLGET(m, M_DONTWAIT); - - if ((m->m_flags & M_EXT) == 0) { - m_freem(m); - return (ENOMEM); - } - - m->m_len = 0; - - /* XXX handle larger packets? */ - len = MCLBYTES ; - buffer = mtod(m, caddr_t); - - len -= 16; - buffer += 16; - - /* make sure the buffer is aligned to a 4-byte boundary */ - if (ADDR_MASK(buffer, 0x03)) { - unsigned int inc = 4 - ADDR_MASK(buffer, 0x03); - buffer += inc; - len -= inc; - } - - m->m_data = buffer; - - for (tmp = m0; tmp; tmp = tmp->m_next) { - if (tmp->m_len > len) { - m_freem(m); - return (EINVAL); - } - bcopy(mtod(tmp, caddr_t), buffer, tmp->m_len); - buffer += tmp->m_len; - m->m_len += tmp->m_len; - len -= tmp->m_len; - } - - m_freem(m0); - *m_org = m; - - return (0); -} diff --git a/sys/dev/pci/if_san_common.h b/sys/dev/pci/if_san_common.h deleted file mode 100644 index 59d19a882f1..00000000000 --- a/sys/dev/pci/if_san_common.h +++ /dev/null @@ -1,427 +0,0 @@ -/* $OpenBSD: if_san_common.h,v 1.9 2012/09/19 22:37:23 jsg Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IF_SAN_COMMON_H -#define __IF_SAN_COMMON_H - -# include -# include - -#define ADDR_MASK(x,y) (((caddr_t)(x) - (caddr_t)0) & (y)) - -#define WANPIPE_LITE_VERSION "1.1.1" -#define WAN_OPENBSD_PLATFORM 0x06 -#define WAN_PLATFORM_ID WAN_OPENBSD_PLATFORM -#define WANPIPE_MAGIC 0x414C4453L /* signature: 'SDLA' reversed */ - -#define ROUTER_NAME "wanrouter" /* in case we ever change it */ -#define ROUTER_IOCTL 'W' /* for IOCTL calls */ - -#define WANROUTER_MAJOR_VER 2 -#define WANROUTER_MINOR_VER 1 - -/* IOCTL codes for /proc/router/ entries (up to 255) */ -#define WANPIPE_DUMP _IOW(ROUTER_IOCTL, 16, wan_conf_t) -#define WANPIPE_EXEC _IOWR(ROUTER_IOCTL, 17, wan_conf_t) - -/* get monitor statistics */ -#define SIOC_WANPIPE_PIPEMON _IOWR('i', 150, struct ifreq) - -/* set generic device */ -#define SIOC_WANPIPE_DEVICE _IOWR('i', 151, struct ifreq) - -/* get hwprobe string */ -#define SIOC_WANPIPE_HWPROBE _IOWR('i', 152, struct ifreq) - -/* get memdump string (GENERIC) */ -#define SIOC_WANPIPE_DUMP _IOWR('i', 153, struct ifreq) - - -/* clocking options */ -#define WAN_EXTERNAL 0 -#define WAN_INTERNAL 1 - -/* intercace options */ -#define WAN_RS232 0 -#define WAN_V35 1 - -#define WAN_UDP_FAILED_CMD 0xCF -#define WAN_UDP_INVALID_CMD 0xCE -#define WAN_UDP_TIMEOUT_CMD 0xAA -#define WAN_UDP_INVALID_NET_CMD 0xCD - -#define WAN_NO 0 -#define WAN_YES 1 - -/* UDP Packet Management */ -#define UDP_PKT_FRM_STACK 0x00 -#define UDP_PKT_FRM_NETWORK 0x01 - -#define WANCONFIG_FR 102 /* frame relay link */ -#define WANCONFIG_PPP 103 /* synchronous PPP link */ -#define WANCONFIG_CHDLC 104 /* Cisco HDLC Link */ -#define WANCONFIG_AFT 117 /* AFT Hardware Support */ -/****** Data Types **********************************************************/ - - -/* Front-End status */ -enum fe_status { - FE_UNITIALIZED = 0x00, - FE_DISCONNECTED, - FE_CONNECTED -}; - -/* 'state' defines */ -enum wan_states -{ - WAN_UNCONFIGURED, /* link/channel is not configured */ - WAN_DISCONNECTED, /* link/channel is disconnected */ - WAN_CONNECTING, /* connection is in progress */ - WAN_CONNECTED, /* link/channel is operational */ - WAN_LIMIT, /* for verification only */ - WAN_DUALPORT, /* for Dual Port cards */ - WAN_DISCONNECTING, - WAN_FT1_READY /* FT1 Configurator Ready */ -}; - -/* 'modem_status' masks */ -#define WAN_MODEM_CTS 0x0001 /* CTS line active */ -#define WAN_MODEM_DCD 0x0002 /* DCD line active */ -#define WAN_MODEM_DTR 0x0010 /* DTR line active */ -#define WAN_MODEM_RTS 0x0020 /* RTS line active */ - -typedef struct wan_conf { - char devname[IFNAMSIZ+1]; - void* arg; -} wan_conf_t; - - -/* IOCTL numbers (up to 16) */ - -#define TRACE_ALL 0x00 -#define TRACE_PROT 0x01 -#define TRACE_DATA 0x02 - -/* values for request/reply byte */ -#define UDPMGMT_REQUEST 0x01 -#define UDPMGMT_REPLY 0x02 -#define UDP_OFFSET 12 - -#define MAX_FT1_RETRY 100 - -/* General Critical Flags */ -enum { - SEND_CRIT, - PERI_CRIT, - RX_CRIT, - PRIV_CRIT -}; - -/* - * Data structures for IOCTL calls. - */ - -typedef struct sdla_dump { /* WANPIPE_DUMP */ - unsigned long magic; /* for verification */ - unsigned long offset; /* absolute adapter memory address */ - unsigned long length; /* block length */ - void* ptr; /* -> buffer */ -} sdla_dump_t; - -typedef struct sdla_exec { /* WANPIPE_EXEC */ - unsigned long magic; /* for verification */ - void* cmd; /* -> command structure */ - void* data; /* -> data buffer */ -} sdla_exec_t; - -#define TRC_INCOMING_FRM 0x00 -#define TRC_OUTGOING_FRM 0x01 -typedef struct { - unsigned char status; - unsigned char data_avail; - unsigned short real_length; - unsigned short time_stamp; - unsigned long sec; - unsigned long usec; - unsigned char data[0]; -} wan_trace_pkt_t; - -typedef struct wan_trace { - unsigned long tracing_enabled; - struct ifqueue ifq; - unsigned int trace_timeout; - unsigned int max_trace_queue; -} wan_trace_t; - - -/******************************************************** - * GLOBAL DEFINITION FOR SANGOMA UDP STRUCTURE * - *******************************************************/ -#define GLOBAL_UDP_SIGNATURE "WANPIPE" -#define GLOBAL_UDP_SIGNATURE_LEN 7 -#define UDPMGMT_UDP_PROTOCOL 0x11 -#define WAN_UDP_CMD_START 0x60 -#define WAN_GET_PROTOCOL (WAN_UDP_CMD_START+0) -#define WAN_GET_PLATFORM (WAN_UDP_CMD_START+1) -#define WAN_GET_MEDIA_TYPE (WAN_UDP_CMD_START+2) -#define WAN_UDP_CMD_END 0x6F - -#define WAN_FE_CMD_START 0x90 -#define WAN_FE_CMD_END 0x9F - -#define WAN_INTERFACE_CMD_START 0xA0 -#define WAN_INTERFACE_CMD_END 0xAF - -#define WAN_FE_UDP_CMD_START 0xB0 -#define WAN_FE_UDP_CMD_END 0xBF - -typedef struct { - unsigned char signature[8]; - unsigned char request_reply; - unsigned char id; - unsigned char reserved[6]; -} wan_mgmt_t; - - -/****** DEFINITION OF UDP HEADER AND STRUCTURE PER PROTOCOL ******/ -typedef struct { - unsigned char num_frames; - unsigned char ismoredata; -} wan_trace_info_t; - -typedef struct wan_udp_hdr{ - wan_mgmt_t wan_mgmt; - wan_cmd_t wan_cmd; - union { - struct { - wan_trace_info_t trace_info; - unsigned char data[WAN_MAX_DATA_SIZE]; - } chdlc, aft; - unsigned char data[WAN_MAX_DATA_SIZE]; - } wan_udphdr_u; -#define wan_udphdr_signature wan_mgmt.signature -#define wan_udphdr_request_reply wan_mgmt.request_reply -#define wan_udphdr_id wan_mgmt.id -#define wan_udphdr_opp_flag wan_cmd.wan_cmd_opp_flag -#define wan_udphdr_command wan_cmd.wan_cmd_command -#define wan_udphdr_data_len wan_cmd.wan_cmd_data_len -#define wan_udphdr_return_code wan_cmd.wan_cmd_return_code -#define wan_udphdr_chdlc_num_frames wan_udphdr_u.chdlc.trace_info.num_frames -#define wan_udphdr_chdlc_ismoredata wan_udphdr_u.chdlc.trace_info.ismoredata -#define wan_udphdr_chdlc_data wan_udphdr_u.chdlc.data - -#define wan_udphdr_aft_num_frames wan_udphdr_u.aft.trace_info.num_frames -#define wan_udphdr_aft_ismoredata wan_udphdr_u.aft.trace_info.ismoredata -#define wan_udphdr_aft_data wan_udphdr_u.aft.data -#define wan_udphdr_data wan_udphdr_u.data -} wan_udp_hdr_t; - -#define MAX_LGTH_UDP_MGNT_PKT 2000 - -/* This is used for interrupt testing */ -#define INTR_TEST_MODE 0x02 - -#define WUM_SIGNATURE_L 0x50495046 -#define WUM_SIGNATURE_H 0x444E3845 - -#define WUM_KILL 0x50 -#define WUM_EXEC 0x51 - - -#if defined(_KERNEL) -/****** Kernel Interface ****************************************************/ - - -#define MAX_E1_CHANNELS 32 -#define MAX_FR_CHANNELS (991+1) - -#ifndef min -#define min(a,b) (((a)<(b))?(a):(b)) -#endif -#ifndef max -#define max(a,b) (((a)>(b))?(a):(b)) -#endif - -#define is_digit(ch) (((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')?1:0) - -#define is_alpha(ch) ((((ch)>=(unsigned)'a'&&(ch)<=(unsigned)'z')|| \ - ((ch)>=(unsigned)'A'&&(ch)<=(unsigned)'Z'))?1:0) - -#define is_hex_digit(ch) ((((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')|| \ - ((ch)>=(unsigned)'a'&&(ch)<=(unsigned)'f')||\ - ((ch)>=(unsigned)'A'&&(ch)<=(unsigned)'F'))?1:0) -#if !defined(offsetof) -# define offsetof(type, member) ((size_t)(&((type*)0)->member)) -#endif - -# define irqreturn_t void -/* Unsafe sprintf and vsprintf function removed from the kernel */ -# define WAN_IRQ_RETVAL(a) return; - -#define _bit_byte(bit) ((bit) >> 3) -#define _bit_mask(bit) (1 << ((bit)&0x7)) - -/* is bit N of bitstring name set? */ -#define bit_test(name, bit) ((name)[_bit_byte(bit)] & _bit_mask(bit)) - -/* set bit N of bitstring name */ -#define bit_set(name, bit) ((name)[_bit_byte(bit)] |= _bit_mask(bit)) - -/* clear bit N of bitstring name */ -#define bit_clear(name, bit) ((name)[_bit_byte(bit)] &= ~_bit_mask(bit)) - -/* Sangoma assert macro */ -#define SAN_ASSERT(a) \ - if (a){ \ - log(LOG_INFO, "%s:%d: Critical Error!\n", \ - __FUNCTION__,__LINE__); \ - return (EINVAL); \ - } - -/****** Data Structures *****************************************************/ - -typedef struct wan_udp_pkt { - struct ip ip_hdr; - struct udphdr udp_hdr; - wan_udp_hdr_t wan_udp_hdr; -#define wan_udp_cmd wan_udp_hdr.wan_cmd -#define wan_udp_signature wan_udp_hdr.wan_udphdr_signature -#define wan_udp_request_reply wan_udp_hdr.wan_udphdr_request_reply -#define wan_udp_id wan_udp_hdr.wan_udphdr_id -#define wan_udp_opp_flag wan_udp_hdr.wan_udphdr_opp_flag -#define wan_udp_command wan_udp_hdr.wan_udphdr_command -#define wan_udp_data_len wan_udp_hdr.wan_udphdr_data_len -#define wan_udp_return_code wan_udp_hdr.wan_udphdr_return_code -#define wan_udp_hdlc_PF_bit wan_udp_hdr.wan_udphdr_hdlc_PF_bit -#define wan_udp_fr_dlci wan_udp_hdr.wan_udphdr_fr_dlci -#define wan_udp_fr_attr wan_udp_hdr.wan_udphdr_fr_attr -#define wan_udp_fr_rxlost1 wan_udp_hdr.wan_udphdr_fr_rxlost1 -#define wan_udp_fr_rxlost2 wan_udp_hdr.wan_udphdr_fr_rxlost2 -#define wan_udp_chdlc_num_frames wan_udp_hdr.wan_udphdr_chdlc_num_frames -#define wan_udp_chdlc_ismoredata wan_udp_hdr.wan_udphdr_chdlc_ismoredata -#define wan_udp_chdlc_data wan_udp_hdr.wan_udphdr_chdlc_data - -#define wan_udp_aft_num_frames wan_udp_hdr.wan_udphdr_aft_num_frames -#define wan_udp_aft_ismoredata wan_udp_hdr.wan_udphdr_aft_ismoredata -#define wan_udp_data wan_udp_hdr.wan_udphdr_data -} wan_udp_pkt_t; - -#define WAN_IFP_TO_COMMON(ifp) (wanpipe_common_t*)((ifp)->if_softc) -typedef struct wanpipe_common { - struct sppp ifp; - void *card; - struct timeout dev_timer; - unsigned int protocol; - struct ifmedia ifm; - - LIST_ENTRY(wanpipe_common) next; -} wanpipe_common_t; - -typedef struct { - unsigned long time_slot_map; - unsigned long logic_ch_map; - unsigned char num_of_time_slots; - unsigned char top_logic_ch; - unsigned long bar; - void *trace_info; - void *dev_to_ch_map[MAX_E1_CHANNELS]; - void *rx_dma_ptr; - void *tx_dma_ptr; - unsigned short num_of_ch;/* Number of logical channels */ - unsigned short dma_per_ch;/* DMA buffers per logic channel */ - unsigned short mru_trans;/* MRU of transparent channels */ - unsigned long dma_mtu_off; - unsigned short dma_mtu; - unsigned char state_change_exit_isr; - unsigned long active_ch_map; - unsigned long fifo_addr_map; - struct timeout led_timer; -} sdla_xilinx_t; - -/* Adapter Data Space. - * This structure is needed because we handle multiple cards, otherwise - * static data would do it. - */ -typedef struct sdla { - unsigned magic; - char devname[IFNAMSIZ+1]; /* card name */ - void *hw; /* hw configuration */ - unsigned int type; /* adapter type */ - unsigned char line_idle; - - char state; /* device state */ - unsigned long critical; /* critical section flag */ - - int(*iface_up) (struct ifnet*); - int(*iface_down) (struct ifnet*); - int(*iface_send) (struct mbuf* skb, struct ifnet*); - int(*iface_ioctl) (struct ifnet*, u_long, struct ifreq*); - - unsigned long state_tick; /* link state timestamp */ - unsigned long in_isr; /* interrupt-in-service flag */ - unsigned long configured; /* configurations status */ - int(*del_if) (struct sdla*, struct ifnet*); - void(*isr)(struct sdla*); /* interrupt service routine */ - void(*poll)(struct sdla*); /* polling routine */ - int(*exec)(struct sdla*, void*, void*); - int(*ioctl) (struct ifnet*, u_long, struct ifreq*); - - union { - sdla_xilinx_t xilinx; - } u; - - sdla_fe_iface_t fe_iface; - union { -#define fe_te u_fe.te_sc - sdla_te_softc_t te_sc; - } u_fe; - - unsigned char front_end_status; - WRITE_FRONT_END_REG_T* write_front_end_reg; - READ_FRONT_END_REG_T* read_front_end_reg; - void(*te_enable_timer) (void*); - void(*te_link_state) (void*); - - LIST_HEAD(,wanpipe_common) dev_head; - LIST_ENTRY(sdla) next; /* -> next device */ -} sdla_t; - -/****** Public Functions ****************************************************/ - -void* wan_xilinx_init(sdla_t*); /* Xilinx Hardware Support */ -struct mbuf* wan_mbuf_alloc(int); -int wan_mbuf_to_buffer(struct mbuf**); - -#endif /* __KERNEL__ */ -#endif /* __IF_SAN_COMMON_H */ diff --git a/sys/dev/pci/if_san_front_end.h b/sys/dev/pci/if_san_front_end.h deleted file mode 100644 index 920a560a1d3..00000000000 --- a/sys/dev/pci/if_san_front_end.h +++ /dev/null @@ -1,283 +0,0 @@ -/* $OpenBSD: if_san_front_end.h,v 1.5 2007/09/12 13:56:40 chl Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * The code is derived from permitted modifications to software created - * by Nenad Corbic (ncorbic@sangoma.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IF_SAN_FRONT_END_H_ -#define __IF_SAN_FRONT_END_H_ - -/* The hardware media */ -#define WAN_MEDIA_NONE 0x00 /* Regular card */ -#define WAN_MEDIA_T1 0x01 /* T1 connection */ -#define WAN_MEDIA_E1 0x02 /* E1 connection */ -#define WAN_MEDIA_56K 0x03 /* 56K connection */ - -/* settings for the 'adapter_type' */ -#define S508_ADPTR 0x0001 /* S508 */ -#define S5141_ADPTR_1_CPU_SERIAL 0x0011 /* S5141, single CPU, serial */ -#define S5142_ADPTR_2_CPU_SERIAL 0x0012 /* S5142, dual CPU, serial */ -#define S5143_ADPTR_1_CPU_FT1 0x0013 /* S5143, single CPU, FT1 */ -#define S5144_ADPTR_1_CPU_T1E1 0x0014 /* S5144, single CPU, T1/E1 */ -#define S5145_ADPTR_1_CPU_56K 0x0015 /* S5145, single CPU, 56K */ -#define S5147_ADPTR_2_CPU_T1E1 0x0017 /* S5147, dual CPU, T1/E1 */ -#define S5148_ADPTR_1_CPU_T1E1 0x0018 /* S5148, single CPU, T1/E1 */ - -#define S518_ADPTR_1_CPU_ADSL 0x0018 /* S518, adsl card */ - -#define A101_ADPTR_T1E1_MASK 0x0040 /* T1/E1 type mask */ -#define A101_ADPTR_1TE1 0x0041 /* 1 Channel T1/E1 */ -#define A101_ADPTR_2TE1 0x0042 /* 2 Channels T1/E1 */ - -#define A100_ADPTR_T3E3_MASK 0x0080 /* T3/E3 type mask */ -#define A100_ADPTR_1_CHN_T3E3 0x0081 /* 1 Channel T3/E3 (Proto.) */ -#define A105_ADPTR_1_CHN_T3E3 0x0082 /* 1 Channel T3/E3 */ - -#define OPERATE_T1E1_AS_SERIAL 0x8000 /* For bitstreaming only - * Allow the application to - * E1 front end */ - -#define SDLA_ADPTR_DECODE(adapter_type) \ - (adapter_type == S5141_ADPTR_1_CPU_SERIAL) ? "S514-1-PCI" : \ - (adapter_type == S5142_ADPTR_2_CPU_SERIAL) ? "S514-2-PCI" : \ - (adapter_type == S5143_ADPTR_1_CPU_FT1) ? "S514-3-PCI" : \ - (adapter_type == S5144_ADPTR_1_CPU_T1E1) ? "S514-4-PCI" : \ - (adapter_type == S5145_ADPTR_1_CPU_56K) ? "S514-5-PCI" : \ - (adapter_type == S5147_ADPTR_2_CPU_T1E1) ? "S514-7-PCI" : \ - (adapter_type == S518_ADPTR_1_CPU_ADSL) ? "S518-PCI " : \ - (adapter_type == A101_ADPTR_1TE1) ? "AFT-A101 " : \ - (adapter_type == A101_ADPTR_2TE1) ? "AFT-A102 " : \ - (adapter_type == A105_ADPTR_1_CHN_T3E3) ? "A105-1-PCI" : \ - (adapter_type == A105_ADPTR_1_CHN_T3E3) ? "A105-2 " : \ - "UNKNOWN " - -/* front-end UDP command */ -#define WAN_FE_GET_STAT (WAN_FE_UDP_CMD_START + 0) -#define WAN_FE_SET_LB_MODE (WAN_FE_UDP_CMD_START + 1) -#define WAN_FE_FLUSH_PMON (WAN_FE_UDP_CMD_START + 2) -#define WAN_FE_GET_CFG (WAN_FE_UDP_CMD_START + 3) - -/* front-end configuration and access interface commands */ - -/* 0x90 read from front-end register */ -#define READ_FRONT_END_REGISTER (WAN_FE_CMD_START+0) - -/* 0x91 write to front-end register */ -#define WRITE_FRONT_END_REGISTER (WAN_FE_CMD_START+1) - -/* 0x92 read the front-end statistics */ -#define READ_FRONT_END_STATISTICS (WAN_FE_CMD_START+2) - -/* 0x93 flush the front-end statistics */ -#define FLUSH_FRONT_END_STATISTICS (WAN_FE_CMD_START+3) - -#ifdef _KERNEL - -/* adapter configuration interface commands */ - -/* 0xA0 set adapter configuration */ -#define SET_ADAPTER_CONFIGURATION (WAN_INTERFACE_CMD_START+0) - -/* 0xA1 read adapter configuration */ -#define READ_ADAPTER_CONFIGURATION (WAN_INTERFACE_CMD_START+1) - -/* front-end command */ -#define WAN_FE_GET_STAT (WAN_FE_UDP_CMD_START + 0) -#define WAN_FE_SET_LB_MODE (WAN_FE_UDP_CMD_START + 1) -#define WAN_FE_FLUSH_PMON (WAN_FE_UDP_CMD_START + 2) -#define WAN_FE_GET_CFG (WAN_FE_UDP_CMD_START + 3) - -/* - * return codes from interface commands - */ -/* the length of the FE_RX_DISC_TX_IDLE_STRUCT is invalid */ -#define LGTH_FE_CFG_DATA_INVALID 0x91 - -/* the length of the passed configuration data is invalid */ -#define LGTH_ADAPTER_CFG_DATA_INVALID 0x91 - -/* the passed SET_FE_RX_DISC_TX_IDLE_CFG data is invalid */ -#define INVALID_FE_CFG_DATA 0x92 - -/* an invalid adapter operating frequency was selected */ -#define ADPTR_OPERATING_FREQ_INVALID 0x92 - -/* set the protocol-level configuration before setting the FE configuration */ -#define PROT_CFG_BEFORE_FE_CFG 0x93 - -/* set the front-end Rx discard/Tx idle configuration */ -#define SET_FE_RX_DISC_TX_IDLE_CFG 0x98 - -/* read the front-end Rx discard/Tx idle configuration */ -#define READ_FE_RX_DISC_TX_IDLE_CFG 0x99 - -/* set the T1/E1 signaling configuration */ -#define SET_TE1_SIGNALING_CFG 0x9A - -/* read the T1/E1 signaling configuration */ -#define READ_TE1_SIGNALING_CFG 0x9B - - -/* the command is invalid for the adapter type */ -#define COMMAND_INVALID_FOR_ADAPTER 0x9F - - -/* - * Constants for the SET_FE_RX_DISC_TX_IDLE_CFG - * and READ_FE_RX_DISC_TX_IDLE_CFG commands - */ - -/* T1 - no active time slots used for reception */ -#define NO_ACTIVE_RX_TIME_SLOTS_T1 24 - -/* T1 - no active time slots used for transmission */ -#define NO_ACTIVE_TX_TIME_SLOTS_T1 24 - -/* E1 - no active time slots used for reception */ -#define NO_ACTIVE_RX_TIME_SLOTS_E1 32 - -/* - * E1 - no active time slots used for transmission - * (channel 0 reserved for framing) - */ -#define NO_ACTIVE_TX_TIME_SLOTS_E1 31 - -/* Read/Write to front-end register */ -#define READ_REG(reg) card->read_front_end_reg(card, reg) -#define WRITE_REG(reg, value) card->write_front_end_reg(card, reg, \ - (unsigned char)(value)) - -/* - * the structure used for the SET_FE_RX_DISC_TX_IDLE_CFG and - * READ_FE_RX_DISC_TX_IDLE_CFG command - */ -#pragma pack(1) -typedef struct { - /* the length of the Rx discard buffer */ - unsigned short lgth_Rx_disc_bfr; - - /* the length of the Tx idle buffer */ - unsigned short lgth_Tx_idle_bfr; - - /* the transmit idle data buffer */ - unsigned char Tx_idle_data_bfr[NO_ACTIVE_TX_TIME_SLOTS_E1]; -} FE_RX_DISC_TX_IDLE_STRUCT; -#pragma pack() - - -/* - * Constants for front-end access - */ - -/* - * the structure used for the READ_FRONT_END_REGISTER and - * WRITE_FRONT_END_REGISTER command - */ -#pragma pack(1) -typedef struct { - /* the register number to be read from or written to */ - unsigned short register_number; - - /* the register value read/written */ - unsigned char register_value; -} FRONT_END_REG_STRUCT; -#pragma pack() - - -/* ----------------------------------------------------------------------------- - * Constants for the READ_FRONT_END_STATISTICS command - * ---------------------------------------------------------------------------*/ - -/* the front-end statistics structure */ -#pragma pack(1) -typedef struct { - /* the number of front-end interrupts generated */ - unsigned long FE_interrupt_count; - - /* the number of front-end interrupt application timeouts */ - unsigned long FE_app_timeout_count; -} FE_STATISTICS_STRUCT; -#pragma pack() - - - -/* - * Constants for the SET_ADAPTER_CONFIGURATION - * and READ_ADAPTER_CONFIGURATION commands - */ - -/* the adapter configuration structure */ -#pragma pack(1) -typedef struct { - unsigned short adapter_type; /* type of adapter */ - unsigned short adapter_config; /* misc adapter config */ - unsigned long operating_frequency; /* adapter operating freq */ -} ADAPTER_CONFIGURATION_STRUCT; -#pragma pack() - - - -typedef unsigned char (WRITE_FRONT_END_REG_T) - (void *, unsigned short, unsigned char); -typedef unsigned char (READ_FRONT_END_REG_T) - (void *, unsigned short); - - -enum { - AFT_LED_ON, - AFT_LED_OFF, - AFT_LED_TOGGLE -}; - - -/* - * Sangoma Front-End interface structure - */ -typedef struct { - /* In-Service or Not (T1/E1/56K) */ - unsigned long (*get_fe_service_status)(void*); - - /* Print Front-End alarm (T1/E1/56K) */ - void (*print_fe_alarm)(void*,unsigned long); - - /* Print Front-End alarm (T1/E1/56K) */ - char* (*print_fe_act_channels)(void*); - - /* Set Front-End alarm (T1/E1) */ - void (*set_fe_alarm)(void*,unsigned long); -} sdla_fe_iface_t; - - -#endif /* _KERNEL */ - -#endif diff --git a/sys/dev/pci/if_san_obsd.c b/sys/dev/pci/if_san_obsd.c deleted file mode 100644 index e9de78cd211..00000000000 --- a/sys/dev/pci/if_san_obsd.c +++ /dev/null @@ -1,444 +0,0 @@ -/* $OpenBSD: if_san_obsd.c,v 1.18 2015/03/14 03:38:48 jsg Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bpfilter.h" -#if NBPFILTER > 0 -# include -#endif -#include -#include -#include -#include - -#include -#include - -#include -#include - - -#ifdef _DEBUG_ -#define STATIC -#else -#define STATIC static -#endif - -#define PPP_HEADER_LEN 4 /* should be globaly defined by sppp */ - - -static sdla_t *wanpipe_generic_getcard(struct ifnet *); -static int wanpipe_generic_ioctl(struct ifnet *, u_long, caddr_t); -static void wanpipe_generic_watchdog(struct ifnet*); -static void wanpipe_generic_start(struct ifnet *); - - -static sdla_t * -wanpipe_generic_getcard(struct ifnet *ifp) -{ - sdla_t* card; - - if (ifp->if_softc == NULL) { - log(LOG_INFO, "%s: Invalid device private structure pointer\n", - ifp->if_xname); - return (NULL); - } - card = ((sdla_t*)((wanpipe_common_t*)ifp->if_softc)->card); - if (card == NULL) { - log(LOG_INFO, "%s: Invalid Sangoma device card\n", - ifp->if_xname); - return (NULL); - } - return (card); -} - -int -wanpipe_generic_name(sdla_t *card, char *ifname, int len) -{ - static int ifunit = 0; - - snprintf(ifname, len, "san%d", ifunit++); - return (0); -} - -int -wanpipe_generic_register(sdla_t *card, struct ifnet *ifp, char *ifname) -{ - wanpipe_common_t* common = WAN_IFP_TO_COMMON(ifp); - - if (ifname == NULL || strlen(ifname) > IFNAMSIZ) - return (EINVAL); - else - bcopy(ifname, ifp->if_xname, strlen(ifname)); - - IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); - IFQ_SET_READY(&ifp->if_snd); - ifp->if_mtu = PP_MTU; - ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; - common->protocol = IF_PROTO_CISCO; - - ((struct sppp *)ifp)->pp_flags |= PP_CISCO; - ((struct sppp *)ifp)->pp_flags |= PP_KEEPALIVE; - ((struct sppp *)ifp)->pp_framebytes = 3; - - ifp->if_ioctl = wanpipe_generic_ioctl; /* Will set from new_if() */ - ifp->if_start = wanpipe_generic_start; - ifp->if_watchdog = wanpipe_generic_watchdog; - - if_attach(ifp); - if_alloc_sadl(ifp); - sppp_attach(ifp); - -#if NBPFILTER > 0 - bpfattach(&ifp->if_bpf, ifp, DLT_PPP, PPP_HEADER_LEN); -#endif /* NBPFILTER > 0 */ - - return (0); -} - -void -wanpipe_generic_unregister(struct ifnet *ifp) -{ - log(LOG_INFO, "%s: Unregister interface!\n", ifp->if_xname); - - sppp_detach(ifp); - if_free_sadl(ifp); - if_detach(ifp); -} - -static void -wanpipe_generic_start(struct ifnet *ifp) -{ - sdla_t *card; - struct mbuf *opkt; - int err = 0; - - if ((card = wanpipe_generic_getcard(ifp)) == NULL) - return; - - while (1) { - if (sppp_isempty(ifp)) { - /* No more packets in send queue */ - break; - } - - if ((opkt = sppp_dequeue(ifp)) == NULL) { - /* Should never happened, packet pointer is NULL */ - break; - } - if (card->iface_send == NULL) { - m_freem(opkt); - break; - } - /* report the packet to BPF if present and attached */ -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, opkt, BPF_DIRECTION_OUT); -#endif /* NBPFILTER > 0 */ - - if (wan_mbuf_to_buffer(&opkt)) { - m_freem(opkt); - break; - } - - err = card->iface_send(opkt, ifp); - if (err) - break; - } -} - - -static int -wanpipe_generic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) -{ - struct proc *p = curproc; - struct ifreq *ifr = (struct ifreq*)data; - sdla_t *card; - wanpipe_common_t* common = WAN_IFP_TO_COMMON(ifp); - struct if_settings ifsettings; - unsigned long ts_map; - int err = 0, s; - - if ((card = wanpipe_generic_getcard(ifp)) == NULL) - return (EINVAL); - - s = splnet(); - - switch (cmd) { - case SIOCSIFADDR: - // XXX because sppp does an implicit setflags - log(LOG_INFO, "%s: Bringing interface up.\n", - ifp->if_xname); - if (card->iface_up) - card->iface_up(ifp); - wanpipe_generic_start(ifp); - err = 1; - break; - - case SIOCSIFMEDIA: - /* You can't set new media type while card is running */ - if (card->state != WAN_DISCONNECTED) { - log(LOG_INFO, "%s: Unable to change media type!\n", - ifp->if_xname); - err = EINVAL; - } else - err = ifmedia_ioctl(ifp, ifr, &common->ifm, cmd); - goto ioctl_out; - - case SIOCGIFMEDIA: - err = ifmedia_ioctl(ifp, ifr, &common->ifm, cmd); - goto ioctl_out; - - case SIOCSIFTIMESLOT: - if ((err = suser(p, 0)) != 0) - goto ioctl_out; - if (card->state != WAN_DISCONNECTED) { - log(LOG_INFO, "%s: Unable to change timeslot map!\n", - ifp->if_xname); - err = EINVAL; - goto ioctl_out; - } - - err = copyin(ifr->ifr_data, &ts_map, sizeof(ts_map)); - if (err == 0) - sdla_te_settimeslot(card, ts_map); - - goto ioctl_out; - - case SIOCGIFTIMESLOT: - ts_map = sdla_te_gettimeslot(card); - err = copyout(ifr->ifr_data, &ts_map, sizeof(ts_map)); - goto ioctl_out; - - case SIOCSIFFLAGS: - /* - ** If the interface is marked up - enable communications. - ** If down - disable communications. IFF_UP is taken - ** care of before entering this function. - */ - err = 1; - if ((ifp->if_flags & IFF_UP) == 0) { - if ((ifp->if_flags & IFF_RUNNING) == 0) - break; - /* bring it down */ - log(LOG_INFO, "%s: Bringing interface down.\n", - ifp->if_xname); - if (card->iface_down) - card->iface_down(ifp); - } else { /* bring it up */ - if (ifp->if_flags & IFF_RUNNING) - break; - log(LOG_INFO, "%s: Bringing interface up.\n", - ifp->if_xname); - if (card->iface_up) - card->iface_up(ifp); - wanpipe_generic_start(ifp); - } - break; - - case SIOC_WANPIPE_DEVICE: - err = copyin(ifr->ifr_data, &ifsettings, - sizeof(struct if_settings)); - - if (err) { - log(LOG_INFO, "%s: Failed to copy from user space!\n", - card->devname); - goto ioctl_out; - } - - switch (ifsettings.type) { - case IF_GET_PROTO: - ifsettings.type = common->protocol; - err = copyout(&ifsettings, ifr->ifr_data, - sizeof(struct if_settings)); - if (err) - log(LOG_INFO, - "%s: Failed to copy to uspace!\n", - card->devname); - break; - - case IF_PROTO_CISCO: - case IF_PROTO_PPP: - if ((err = suser(p, 0)) != 0) - goto ioctl_out; - err = wp_lite_set_proto(ifp, (struct ifreq*)data); - break; - - case IF_IFACE_T1: - case IF_IFACE_E1: - if ((err = suser(p, 0)) != 0) - goto ioctl_out; - err = wp_lite_set_te1_cfg(ifp, (struct ifreq*)data); - break; - - default: - if (card->iface_ioctl) - err = card->iface_ioctl(ifp, cmd, - (struct ifreq*)data); - break; - } - goto ioctl_out; - - default: - if (card->iface_ioctl) { - /* Argument seqeunce is change for Linux order */ - err = card->iface_ioctl(ifp, cmd, (struct ifreq*)data); - } - break; - } - - if (err) - err = sppp_ioctl(ifp, cmd, data); - -ioctl_out: - splx(s); - return (err); -} - -static void -wanpipe_generic_watchdog(struct ifnet *ifp) -{ - return; -} - -int -wanpipe_generic_open(struct ifnet *ifp) -{ - return (0); -} - -int -wanpipe_generic_close(struct ifnet *ifp) -{ - return (0); -} - -int -wanpipe_generic_input(struct ifnet *ifp, struct mbuf *m) -{ - sdla_t *card; -#if NBPFILTER > 0 -#endif /* NBPFILTER > 0 */ - - if ((card = wanpipe_generic_getcard(ifp)) == NULL) { - return (-EINVAL); - } - m->m_pkthdr.rcvif = ifp; -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); -#endif /* NBPFILTER > 0 */ - ifp->if_ipackets ++; - sppp_input(ifp, m); - return (0); -} - -int -wp_lite_set_proto(struct ifnet *ifp, struct ifreq *ifr) -{ - wanpipe_common_t *common; - struct if_settings *ifsettings; - int err = 0; - - if ((common = ifp->if_softc) == NULL) { - log(LOG_INFO, "%s: Private structure is null!\n", - ifp->if_xname); - return (EINVAL); - } - - ifsettings = (struct if_settings*) ifr->ifr_data; - - switch (ifsettings->type) { - case IF_PROTO_CISCO: - if (common->protocol == IF_PROTO_CISCO) - return 0; - ((struct sppp *)ifp)->pp_flags |= PP_CISCO; - ((struct sppp *)ifp)->pp_flags |= PP_KEEPALIVE; - common->protocol = IF_PROTO_CISCO; - break; - case IF_PROTO_PPP: - if (common->protocol == IF_PROTO_PPP) - return 0; - ((struct sppp *)ifp)->pp_flags &= ~PP_CISCO; - ((struct sppp *)ifp)->pp_flags |= PP_KEEPALIVE; - common->protocol = IF_PROTO_PPP; - break; - } - - err = sppp_ioctl(ifp, SIOCSIFFLAGS, ifr); - return (err); -} - -int -wp_lite_set_te1_cfg(struct ifnet *ifp, struct ifreq *ifr) -{ - sdla_t *card; - struct if_settings *ifsettings; - sdla_te_cfg_t te_cfg; - int err = 0; - - if ((card = wanpipe_generic_getcard(ifp)) == NULL) - return (EINVAL); - - ifsettings = (struct if_settings*)ifr->ifr_data; - err = copyin(ifsettings->ifs_te1, &te_cfg, sizeof(sdla_te_cfg_t)); - - if (ifsettings->flags & SANCFG_CLOCK_FLAG) - card->fe_te.te_cfg.te_clock = te_cfg.te_clock; - - switch (ifsettings->type) { - case IF_IFACE_T1: - if (ifsettings->flags & SANCFG_LBO_FLAG) - card->fe_te.te_cfg.lbo = te_cfg.lbo; - break; - } - - return (err); -} diff --git a/sys/dev/pci/if_san_obsd.h b/sys/dev/pci/if_san_obsd.h deleted file mode 100644 index 250fbe92b02..00000000000 --- a/sys/dev/pci/if_san_obsd.h +++ /dev/null @@ -1,105 +0,0 @@ -/* $OpenBSD: if_san_obsd.h,v 1.5 2005/04/01 21:42:36 canacar Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - - - -#ifndef __IF_SAN_OBSD_H -# define __IF_SAN_OBSD_H - -#define IF_IFACE_V35 0x1001 -#define IF_IFACE_T1 0x1002 -#define IF_IFACE_E1 0x1003 -#define IF_IFACE_SYNC_SERIAL 0x1004 - -#define IF_PROTO_HDLC 0x2001 -#define IF_PROTO_PPP 0x2002 -#define IF_PROTO_CISCO 0x2003 -#define IF_PROTO_FR 0x2004 -#define IF_PROTO_FR_ADD_PVC 0x2005 -#define IF_PROTO_FR_DEL_PVC 0x2006 -#define IF_PROTO_X25 0x2007 -#define WAN_PROTO_X25 0x2007 - -#define IF_GET_PROTO 0x3001 - -#define te1_settings void -#define sync_serial_settings void - -#define ifs_size data_length -#define ifs_te1 data -#define ifs_sync data -#define ifs_cisco data -#define ifs_fr data -#define ifs_fr_pvc data -#define ifs_fr_pvc_info data - - -#define SANCFG_LBO_FLAG 0x0001 -#define SANCFG_CLOCK_FLAG 0x0002 - -typedef struct { int dummy; } cisco_proto, fr_proto, fr_proto_pvc; -struct if_settings { - unsigned int type; - unsigned int data_length; - unsigned long flags; - void* data; -}; - -typedef struct { - int proto; - int iface; - char hwprobe[100]; - sdla_te_cfg_t te_cfg; - union { - cisco_proto cisco; - fr_proto fr; - fr_proto_pvc fr_pvc; - } protocol; -} wanlite_def_t; - -/* WANPIPE Generic function interface */ -# if defined(_KERNEL) -struct ifnet *wanpipe_generic_alloc (sdla_t *); -void wanpipe_generic_free (struct ifnet *); -int wanpipe_generic_name (sdla_t *, char *, int); -int wanpipe_generic_register(sdla_t *, struct ifnet *, char *); -void wanpipe_generic_unregister(struct ifnet *); -int wanpipe_generic_open(struct ifnet *); -int wanpipe_generic_close(struct ifnet *); -int wanpipe_generic_input(struct ifnet *, struct mbuf *); -int wanpipe_generic_tx_timeout(struct ifnet *); -int wp_lite_set_proto(struct ifnet *, struct ifreq *); -int wp_lite_set_te1_cfg(struct ifnet *, struct ifreq *); -# endif -#endif /* __IF_SAN_OBSD_H */ diff --git a/sys/dev/pci/if_san_te1.c b/sys/dev/pci/if_san_te1.c deleted file mode 100644 index 099bdb461cb..00000000000 --- a/sys/dev/pci/if_san_te1.c +++ /dev/null @@ -1,3866 +0,0 @@ -/* $OpenBSD: if_san_te1.c,v 1.14 2014/12/05 15:50:04 mpi Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - - -#define FIRST_SAMPLE 0 -#define LAST_SAMPLE 23 -#define FIRST_UI 0 -#define LAST_UI 4 - -#define MAX_BUSY_READ 0x05 - -/* Enabling/Disabling register debugging */ -#undef WAN_DEBUG_TE1_REG -#ifdef WAN_DEBUG_TE1_REG - -#define TEST_REG(reg,value) \ -{ \ - unsigned char test_value = READ_REG(reg); \ - if (test_value != value) { \ - log(LOG_INFO, "%s:%d: Test failed!\n", \ - __FILE__,__LINE__); \ - log(LOG_INFO, "%s:%d: Reg=%02x, Val=%02x\n", \ - __FILE__,__LINE__,reg, value); \ - } \ -} - -#define TEST_RPSC_REG(card,reg,channel,value) \ -{ \ - unsigned char test_value = ReadRPSCReg(card,channel,reg); \ - if (test_value != value) { \ - log(LOG_INFO, "%s:%d: RPSC REG Test failed!\n", \ - __FILE__,__LINE__); \ - log(LOG_INFO, "%s:%d: Reg=%02x,Channel=%d,Val=%02x!\n", \ - __FILE__, __LINE__, reg, channel, value); \ - } \ -} - -#define TEST_TPSC_REG(card,reg,channel,value) \ -{ \ - unsigned char test_value = ReadTPSCReg(card,channel,reg); \ - if (test_value != value) { \ - log(LOG_INFO, "%s:%d: TPSC REG Test failed!\n", \ - __FILE__,__LINE__); \ - log(LOG_INFO, "%s:%d: Reg=%02x,Channel=%d,Val=%02x)!\n",\ - __FILE__, __LINE__, reg, channel, value); \ - } \ -} - -#else - -#define TEST_REG(reg,value) -#define TEST_RPSC_REG(card,reg,channel,value) -#define TEST_TPSC_REG(card,reg,channel,value) - -#endif - -#define READ_RPSC_REG(reg,channel) ReadRPSCReg(card,reg,channel) -#define READ_TPSC_REG(reg,channel) ReadTPSCReg(card,reg,channel) -#define READ_SIGX_REG(reg,channel) ReadSIGXReg(card,reg,channel) -#define WRITE_RPSC_REG(reg,channel,value) \ - { \ - WriteRPSCReg(card,reg,channel,(unsigned char)value); \ - TEST_RPSC_REG(card,reg,channel,(unsigned char)value); \ - } - -#define WRITE_TPSC_REG(reg,channel,value) \ - { \ - WriteTPSCReg(card,reg,channel,(unsigned char)value); \ - TEST_TPSC_REG(card,reg,channe,(unsigned char)value); \ - } - -#if 0 -#define WRITE_SIGX_REG(reg,channel,value) \ - { \ - WriteSIGXReg(card,reg,channel,(unsigned char)value); \ - TEST_SIGX_REG(card,reg,channel,(unsigned char)value); \ - } -#endif - -#define IS_T1_ALARM(alarm) ((alarm) & \ - ( \ - BIT_RED_ALARM | \ - BIT_AIS_ALARM | \ - BIT_YEL_ALARM \ - )) - -#define IS_E1_ALARM(alarm) ((alarm) & \ - ( \ - BIT_RED_ALARM | \ - BIT_AIS_ALARM | \ - BIT_ALOS_ALARM \ - )) - - -typedef -unsigned char TX_WAVEFORM[LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1]; - -typedef struct RLPS_EQUALIZER_RAM_T { - /*unsigned char address;*/ - unsigned char byte1; - unsigned char byte2; - unsigned char byte3; - unsigned char byte4; -} RLPS_EQUALIZER_RAM; - - - -/* Transmit Waveform Values for T1 Long Haul (LBO 0db) -** unsigned char t1_tx_waveform_lh_0db -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_lh_0db = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x20, 0x43, 0x00, 0x00, 0x00 }, - { 0x32, 0x43, 0x00, 0x00, 0x00 }, - { 0x3E, 0x42, 0x00, 0x00, 0x00 }, - { 0x3D, 0x42, 0x00, 0x00, 0x00 }, - { 0x3C, 0x41, 0x00, 0x00, 0x00 }, - { 0x3B, 0x41, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x39, 0x00, 0x00, 0x00, 0x00 }, - { 0x39, 0x00, 0x00, 0x00, 0x00 }, - { 0x38, 0x00, 0x00, 0x00, 0x00 }, - { 0x37, 0x00, 0x00, 0x00, 0x00 }, - { 0x36, 0x00, 0x00, 0x00, 0x00 }, - { 0x34, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x4F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4C, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - -/* Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB): -** unsigned char t1_tx_waveform_lh_75db -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_lh_75db = -{ - { 0x00, 0x10, 0x00, 0x00, 0x00 }, - { 0x01, 0x0E, 0x00, 0x00, 0x00 }, - { 0x02, 0x0C, 0x00, 0x00, 0x00 }, - { 0x04, 0x0A, 0x00, 0x00, 0x00 }, - { 0x08, 0x08, 0x00, 0x00, 0x00 }, - { 0x0C, 0x06, 0x00, 0x00, 0x00 }, - { 0x10, 0x04, 0x00, 0x00, 0x00 }, - { 0x16, 0x02, 0x00, 0x00, 0x00 }, - { 0x1A, 0x01, 0x00, 0x00, 0x00 }, - { 0x1E, 0x00, 0x00, 0x00, 0x00 }, - { 0x22, 0x00, 0x00, 0x00, 0x00 }, - { 0x26, 0x00, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x2B, 0x00, 0x00, 0x00, 0x00 }, - { 0x2C, 0x00, 0x00, 0x00, 0x00 }, - { 0x2D, 0x00, 0x00, 0x00, 0x00 }, - { 0x2C, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x24, 0x00, 0x00, 0x00, 0x00 }, - { 0x20, 0x00, 0x00, 0x00, 0x00 }, - { 0x1C, 0x00, 0x00, 0x00, 0x00 }, - { 0x18, 0x00, 0x00, 0x00, 0x00 }, - { 0x14, 0x00, 0x00, 0x00, 0x00 }, - { 0x12, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Long Haul (LBO 15 dB) -** unsigned char t1_tx_waveform_lh_15db -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_lh_15db = -{ - { 0x00, 0x2A, 0x09, 0x01, 0x00 }, - { 0x00, 0x28, 0x08, 0x01, 0x00 }, - { 0x00, 0x26, 0x08, 0x01, 0x00 }, - { 0x00, 0x24, 0x07, 0x01, 0x00 }, - { 0x01, 0x22, 0x07, 0x01, 0x00 }, - { 0x02, 0x20, 0x06, 0x01, 0x00 }, - { 0x04, 0x1E, 0x06, 0x01, 0x00 }, - { 0x07, 0x1C, 0x05, 0x00, 0x00 }, - { 0x0A, 0x1B, 0x05, 0x00, 0x00 }, - { 0x0D, 0x19, 0x05, 0x00, 0x00 }, - { 0x10, 0x18, 0x04, 0x00, 0x00 }, - { 0x14, 0x16, 0x04, 0x00, 0x00 }, - { 0x18, 0x15, 0x04, 0x00, 0x00 }, - { 0x1B, 0x13, 0x03, 0x00, 0x00 }, - { 0x1E, 0x12, 0x03, 0x00, 0x00 }, - { 0x21, 0x10, 0x03, 0x00, 0x00 }, - { 0x24, 0x0F, 0x03, 0x00, 0x00 }, - { 0x27, 0x0D, 0x03, 0x00, 0x00 }, - { 0x2A, 0x0D, 0x02, 0x00, 0x00 }, - { 0x2D, 0x0B, 0x02, 0x00, 0x00 }, - { 0x30, 0x0B, 0x02, 0x00, 0x00 }, - { 0x30, 0x0A, 0x02, 0x00, 0x00 }, - { 0x2E, 0x0A, 0x02, 0x00, 0x00 }, - { 0x2C, 0x09, 0x02, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB) -** unsigned char t1_tx_waveform_lh_225db -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_lh_225db = -{ - { 0x00, 0x1F, 0x16, 0x06, 0x01 }, - { 0x00, 0x20, 0x15, 0x05, 0x01 }, - { 0x00, 0x21, 0x15, 0x05, 0x01 }, - { 0x00, 0x22, 0x14, 0x05, 0x01 }, - { 0x00, 0x22, 0x13, 0x04, 0x00 }, - { 0x00, 0x23, 0x12, 0x04, 0x00 }, - { 0x01, 0x23, 0x12, 0x04, 0x00 }, - { 0x01, 0x24, 0x11, 0x03, 0x00 }, - { 0x01, 0x23, 0x10, 0x03, 0x00 }, - { 0x02, 0x23, 0x10, 0x03, 0x00 }, - { 0x03, 0x22, 0x0F, 0x03, 0x00 }, - { 0x05, 0x22, 0x0E, 0x03, 0x00 }, - { 0x07, 0x21, 0x0E, 0x02, 0x00 }, - { 0x09, 0x20, 0x0D, 0x02, 0x00 }, - { 0x0B, 0x1E, 0x0C, 0x02, 0x00 }, - { 0x0E, 0x1D, 0x0C, 0x02, 0x00 }, - { 0x10, 0x1B, 0x0B, 0x02, 0x00 }, - { 0x13, 0x1B, 0x0A, 0x02, 0x00 }, - { 0x15, 0x1A, 0x0A, 0x02, 0x00 }, - { 0x17, 0x19, 0x09, 0x01, 0x00 }, - { 0x19, 0x19, 0x08, 0x01, 0x00 }, - { 0x1B, 0x18, 0x08, 0x01, 0x00 }, - { 0x1D, 0x17, 0x07, 0x01, 0x00 }, - { 0x1E, 0x17, 0x06, 0x01, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (0 - 110 ft.) -** unsigned char t1_tx_waveform_sh_110ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_110ft = -{ - { 0x00, 0x45, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x20, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3C, 0x41, 0x00, 0x00, 0x00 }, - { 0x3B, 0x41, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x39, 0x00, 0x00, 0x00, 0x00 }, - { 0x39, 0x00, 0x00, 0x00, 0x00 }, - { 0x38, 0x00, 0x00, 0x00, 0x00 }, - { 0x37, 0x00, 0x00, 0x00, 0x00 }, - { 0x36, 0x00, 0x00, 0x00, 0x00 }, - { 0x34, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x59, 0x00, 0x00, 0x00, 0x00 }, - { 0x55, 0x00, 0x00, 0x00, 0x00 }, - { 0x50, 0x00, 0x00, 0x00, 0x00 }, - { 0x4D, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x48, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (110 - 220 ft.) -** unsigned char t1_tx_waveform_sh_220ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_220ft = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x36, 0x42, 0x00, 0x00, 0x00 }, - { 0x34, 0x42, 0x00, 0x00, 0x00 }, - { 0x30, 0x41, 0x00, 0x00, 0x00 }, - { 0x2F, 0x41, 0x00, 0x00, 0x00 }, - { 0x2E, 0x00, 0x00, 0x00, 0x00 }, - { 0x2D, 0x00, 0x00, 0x00, 0x00 }, - { 0x2C, 0x00, 0x00, 0x00, 0x00 }, - { 0x2B, 0x00, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x26, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x68, 0x00, 0x00, 0x00, 0x00 }, - { 0x54, 0x00, 0x00, 0x00, 0x00 }, - { 0x4F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (220 - 330 ft.) -** unsigned char t1_tx_waveform_sh_330ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_330ft = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3A, 0x43, 0x00, 0x00, 0x00 }, - { 0x3A, 0x42, 0x00, 0x00, 0x00 }, - { 0x38, 0x42, 0x00, 0x00, 0x00 }, - { 0x30, 0x41, 0x00, 0x00, 0x00 }, - { 0x2F, 0x41, 0x00, 0x00, 0x00 }, - { 0x2E, 0x00, 0x00, 0x00, 0x00 }, - { 0x2D, 0x00, 0x00, 0x00, 0x00 }, - { 0x2C, 0x00, 0x00, 0x00, 0x00 }, - { 0x2B, 0x00, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x23, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x6C, 0x00, 0x00, 0x00, 0x00 }, - { 0x60, 0x00, 0x00, 0x00, 0x00 }, - { 0x4F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (330 - 440 ft.) -** unsigned char t1_tx_waveform_sh_440ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_440ft = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x2F, 0x41, 0x00, 0x00, 0x00 }, - { 0x2E, 0x41, 0x00, 0x00, 0x00 }, - { 0x2D, 0x00, 0x00, 0x00, 0x00 }, - { 0x2C, 0x00, 0x00, 0x00, 0x00 }, - { 0x2B, 0x00, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x19, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x7F, 0x00, 0x00, 0x00, 0x00 }, - { 0x60, 0x00, 0x00, 0x00, 0x00 }, - { 0x4F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (440 - 550 ft.) -** unsigned char t1_tx_waveform_sh_550ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_550ft = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x30, 0x41, 0x00, 0x00, 0x00 }, - { 0x2B, 0x41, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x27, 0x00, 0x00, 0x00, 0x00 }, - { 0x26, 0x00, 0x00, 0x00, 0x00 }, - { 0x26, 0x00, 0x00, 0x00, 0x00 }, - { 0x24, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x7F, 0x00, 0x00, 0x00, 0x00 }, - { 0x7F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4F, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for T1 Short Haul (550 - 660 ft.) -** unsigned char t1_tx_waveform_sh_660ft -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM t1_tx_waveform_sh_660ft = -{ - { 0x00, 0x44, 0x00, 0x00, 0x00 }, - { 0x0A, 0x44, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x43, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3F, 0x42, 0x00, 0x00, 0x00 }, - { 0x3F, 0x41, 0x00, 0x00, 0x00 }, - { 0x30, 0x41, 0x00, 0x00, 0x00 }, - { 0x2A, 0x00, 0x00, 0x00, 0x00 }, - { 0x29, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x27, 0x00, 0x00, 0x00, 0x00 }, - { 0x26, 0x00, 0x00, 0x00, 0x00 }, - { 0x25, 0x00, 0x00, 0x00, 0x00 }, - { 0x24, 0x00, 0x00, 0x00, 0x00 }, - { 0x4A, 0x00, 0x00, 0x00, 0x00 }, - { 0x7F, 0x00, 0x00, 0x00, 0x00 }, - { 0x7F, 0x00, 0x00, 0x00, 0x00 }, - { 0x5F, 0x00, 0x00, 0x00, 0x00 }, - { 0x50, 0x00, 0x00, 0x00, 0x00 }, - { 0x49, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x47, 0x00, 0x00, 0x00, 0x00 }, - { 0x46, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for E1 120 Ohm -** unsigned char e1_tx_waveform_120 -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM e1_tx_waveform_120 = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x0A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3F, 0x00, 0x00, 0x00, 0x00 }, - { 0x3F, 0x00, 0x00, 0x00, 0x00 }, - { 0x39, 0x00, 0x00, 0x00, 0x00 }, - { 0x38, 0x00, 0x00, 0x00, 0x00 }, - { 0x36, 0x00, 0x00, 0x00, 0x00 }, - { 0x36, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x35, 0x00, 0x00, 0x00, 0x00 }, - { 0x2D, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 } -}; - - -/* Transmit Waveform Values for E1 75 Ohm -** unsigned char e1_tx_waveform_75 -** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */ -TX_WAVEFORM e1_tx_waveform_75 = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x0A, 0x00, 0x00, 0x00, 0x00 }, - { 0x28, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x3A, 0x00, 0x00, 0x00, 0x00 }, - { 0x32, 0x00, 0x00, 0x00, 0x00 }, - { 0x14, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00 } -}; - - -RLPS_EQUALIZER_RAM t1_rlps_ram_table[] = -{ - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xEE, 0x18, 0x40 }, - { 0x03, 0xE6, 0x18, 0x40 }, - { 0x03, 0xDE, 0x18, 0x40 }, - { 0x03, 0xD6, 0x18, 0x40 }, - { 0x03, 0xD6, 0x18, 0x40 }, - { 0x03, 0xD6, 0x18, 0x40 }, - { 0x03, 0xCE, 0x18, 0x40 }, - { 0x03, 0xCE, 0x18, 0x40 }, - { 0x03, 0xCE, 0x18, 0x40 }, - { 0x03, 0xCE, 0x18, 0x40 }, - { 0x03, 0xC6, 0x18, 0x40 }, - { 0x03, 0xC6, 0x18, 0x40 }, - { 0x03, 0xC6, 0x18, 0x40 }, - { 0x0B, 0xBE, 0x18, 0x40 }, - { 0x0B, 0xBE, 0x18, 0x40 }, - { 0x0B, 0xBE, 0x18, 0x40 }, - { 0x0B, 0xBE, 0x18, 0x40 }, - { 0x0B, 0xB6, 0x18, 0x40 }, - { 0x0B, 0xB6, 0x18, 0x40 }, - { 0x0B, 0xB6, 0x18, 0x40 }, - { 0x0B, 0xB6, 0x18, 0x40 }, - { 0x13, 0xAE, 0x18, 0x38 }, - { 0x13, 0xAE, 0x18, 0x3C }, - { 0x13, 0xAE, 0x18, 0x40 }, - { 0x13, 0xAE, 0x18, 0x40 }, - { 0x13, 0xAE, 0x18, 0x40 }, - { 0x13, 0xAE, 0x18, 0x40 }, - { 0x1B, 0xB6, 0x18, 0xB8 }, - { 0x1B, 0xAE, 0x18, 0xB8 }, - { 0x1B, 0xAE, 0x18, 0xBC }, - { 0x1B, 0xAE, 0x18, 0xC0 }, - { 0x1B, 0xAE, 0x18, 0xC0 }, - { 0x23, 0xA6, 0x18, 0xC0 }, - { 0x23, 0xA6, 0x18, 0xC0 }, - { 0x23, 0xA6, 0x18, 0xC0 }, - { 0x23, 0xA6, 0x18, 0xC0 }, - { 0x23, 0xA6, 0x18, 0xC0 }, - { 0x23, 0x9E, 0x18, 0xC0 }, - { 0x23, 0x9E, 0x18, 0xC0 }, - { 0x23, 0x9E, 0x18, 0xC0 }, - { 0x23, 0x9E, 0x18, 0xC0 }, - { 0x23, 0x9E, 0x18, 0xC0 }, - { 0x2B, 0x96, 0x18, 0xC0 }, - { 0x2B, 0x96, 0x18, 0xC0 }, - { 0x2B, 0x96, 0x18, 0xC0 }, - { 0x33, 0x96, 0x19, 0x40 }, - { 0x37, 0x96, 0x19, 0x40 }, - { 0x37, 0x96, 0x19, 0x40 }, - { 0x37, 0x96, 0x19, 0x40 }, - { 0x3F, 0x9E, 0x19, 0xC0 }, - { 0x3F, 0x9E, 0x19, 0xC0 }, - { 0x3F, 0x9E, 0x19, 0xC0 }, - { 0x3F, 0xA6, 0x1A, 0x40 }, - { 0x3F, 0xA6, 0x1A, 0x40 }, - { 0x3F, 0xA6, 0x1A, 0x40 }, - { 0x3F, 0xA6, 0x1A, 0x40 }, - { 0x3F, 0x96, 0x19, 0xC0 }, - { 0x3F, 0x96, 0x19, 0xC0 }, - { 0x3F, 0x96, 0x19, 0xC0 }, - { 0x3F, 0x96, 0x19, 0xC0 }, - { 0x47, 0x9E, 0x1A, 0x40 }, - { 0x47, 0x9E, 0x1A, 0x40 }, - { 0x47, 0x9E, 0x1A, 0x40 }, - { 0x47, 0x96, 0x1A, 0x40 }, - { 0x47, 0x96, 0x1A, 0x40 }, - { 0x47, 0x96, 0x1A, 0x40 }, - { 0x47, 0x96, 0x1A, 0x40 }, - { 0x4F, 0x8E, 0x1A, 0x40 }, - { 0x4F, 0x8E, 0x1A, 0x40 }, - { 0x4F, 0x8E, 0x1A, 0x40 }, - { 0x4F, 0x8E, 0x1A, 0x40 }, - { 0x4F, 0x8E, 0x1A, 0x40 }, - { 0x57, 0x86, 0x1A, 0x40 }, - { 0x57, 0x86, 0x1A, 0x40 }, - { 0x57, 0x86, 0x1A, 0x40 }, - { 0x57, 0x86, 0x1A, 0x40 }, - { 0x57, 0x86, 0x1A, 0x40 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x86, 0x1A, 0xC0 }, - { 0x5F, 0x7E, 0x1A, 0xC0 }, - { 0x5F, 0x7E, 0x1A, 0xC0 }, - { 0x5F, 0x7E, 0x1A, 0xC0 }, - { 0x5F, 0x7E, 0x1A, 0xC0 }, - { 0x5F, 0x7E, 0x1A, 0xC0 }, - { 0x67, 0x7E, 0x2A, 0xC0 }, - { 0x67, 0x7E, 0x2A, 0xC0 }, - { 0x67, 0x7E, 0x2A, 0xC0 }, - { 0x67, 0x7E, 0x2A, 0xC0 }, - { 0x67, 0x76, 0x2A, 0xC0 }, - { 0x67, 0x76, 0x2A, 0xC0 }, - { 0x67, 0x76, 0x2A, 0xC0 }, - { 0x67, 0x76, 0x2A, 0xC0 }, - { 0x67, 0x76, 0x2A, 0xC0 }, - { 0x6F, 0x6E, 0x2A, 0xC0 }, - { 0x6F, 0x6E, 0x2A, 0xC0 }, - { 0x6F, 0x6E, 0x2A, 0xC0 }, - { 0x6F, 0x6E, 0x2A, 0xC0 }, - { 0x77, 0x6E, 0x3A, 0xC0 }, - { 0x77, 0x6E, 0x3A, 0xC0 }, - { 0x77, 0x6E, 0x3A, 0xC0 }, - { 0x77, 0x6E, 0x3A, 0xC0 }, - { 0x7F, 0x66, 0x3A, 0xC0 }, - { 0x7F, 0x66, 0x3A, 0xC0 }, - { 0x7F, 0x66, 0x4A, 0xC0 }, - { 0x7F, 0x66, 0x4A, 0xC0 }, - { 0x7F, 0x66, 0x4A, 0xC0 }, - { 0x7F, 0x66, 0x4A, 0xC0 }, - { 0x87, 0x66, 0x5A, 0xC0 }, - { 0x87, 0x66, 0x5A, 0xC0 }, - { 0x87, 0x66, 0x5A, 0xC0 }, - { 0x87, 0x66, 0x5A, 0xC0 }, - { 0x87, 0x66, 0x5A, 0xC0 }, - { 0x87, 0x5E, 0x5A, 0xC0 }, - { 0x87, 0x5E, 0x5A, 0xC0 }, - { 0x87, 0x5E, 0x5A, 0xC0 }, - { 0x87, 0x5E, 0x5A, 0xC0 }, - { 0x87, 0x5E, 0x5A, 0xC0 }, - { 0x8F, 0x5E, 0x6A, 0xC0 }, - { 0x8F, 0x5E, 0x6A, 0xC0 }, - { 0x8F, 0x5E, 0x6A, 0xC0 }, - { 0x8F, 0x5E, 0x6A, 0xC0 }, - { 0x97, 0x5E, 0x7A, 0xC0 }, - { 0x97, 0x5E, 0x7A, 0xC0 }, - { 0x97, 0x5E, 0x7A, 0xC0 }, - { 0x97, 0x5E, 0x7A, 0xC0 }, - { 0x9F, 0x5E, 0x8A, 0xC0 }, - { 0x9F, 0x5E, 0x8A, 0xC0 }, - { 0x9F, 0x5E, 0x8A, 0xC0 }, - { 0x9F, 0x5E, 0x8A, 0xC0 }, - { 0x9F, 0x5E, 0x8A, 0xC0 }, - { 0xA7, 0x56, 0x9A, 0xC0 }, - { 0xA7, 0x56, 0x9A, 0xC0 }, - { 0xA7, 0x56, 0x9A, 0xC0 }, - { 0xA7, 0x56, 0x9A, 0xC0 }, - { 0xA7, 0x56, 0xAA, 0xC0 }, - { 0xA7, 0x56, 0xAA, 0xC0 }, - { 0xA7, 0x56, 0xAA, 0xC0 }, - { 0xAF, 0x4E, 0xAA, 0xC0 }, - { 0xAF, 0x4E, 0xAA, 0xC0 }, - { 0xAF, 0x4E, 0xAA, 0xC0 }, - { 0xAF, 0x4E, 0xAA, 0xC0 }, - { 0xAF, 0x4E, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xAA, 0xC0 }, - { 0xB7, 0x46, 0xBA, 0xC0 }, - { 0xB7, 0x46, 0xBA, 0xC0 }, - { 0xB7, 0x46, 0xBA, 0xC0 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBF, 0x4E, 0xBB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xCB, 0x40 }, - { 0xBE, 0x46, 0xDB, 0x40 }, - { 0xBE, 0x46, 0xDB, 0x40 }, - { 0xBE, 0x46, 0xDB, 0x40 }, - { 0xC6, 0x3E, 0xCB, 0x40 }, - { 0xC6, 0x3E, 0xCB, 0x40 }, - { 0xC6, 0x3E, 0xDB, 0x40 }, - { 0xC6, 0x3E, 0xDB, 0x40 }, - { 0xC6, 0x3E, 0xDB, 0x40 }, - { 0xC6, 0x44, 0xDB, 0x40 }, - { 0xC6, 0x44, 0xDB, 0x40 }, - { 0xC6, 0x44, 0xDB, 0x40 }, - { 0xC6, 0x44, 0xDB, 0x40 }, - { 0xC6, 0x3C, 0xDB, 0x40 }, - { 0xC6, 0x3C, 0xDB, 0x40 }, - { 0xC6, 0x3C, 0xDB, 0x40 }, - { 0xC6, 0x3C, 0xDB, 0x40 }, - { 0xD6, 0x34, 0xDB, 0x40 }, - { 0xD6, 0x34, 0xDB, 0x40 }, - { 0xD6, 0x34, 0xDB, 0x40 }, - { 0xD6, 0x34, 0xDB, 0x40 }, - { 0xD6, 0x34, 0xDB, 0x40 }, - { 0xDE, 0x2C, 0xDB, 0x3C }, - { 0xDE, 0x2C, 0xDB, 0x3C }, - { 0xDE, 0x2C, 0xDB, 0x3C }, - { 0xE6, 0x2C, 0xDB, 0x40 }, - { 0xE6, 0x2C, 0xDB, 0x40 }, - { 0xE6, 0x2C, 0xDB, 0x40 }, - { 0xE6, 0x2C, 0xDB, 0x40 }, - { 0xE6, 0x2C, 0xDB, 0x40 }, - { 0xE6, 0x2C, 0xEB, 0x40 }, - { 0xE6, 0x2C, 0xEB, 0x40 }, - { 0xE6, 0x2C, 0xEB, 0x40 }, - { 0xEE, 0x2C, 0xFB, 0x40 }, - { 0xEE, 0x2C, 0xFB, 0x40 }, - { 0xEE, 0x2C, 0xFB, 0x40 }, - { 0xEE, 0x2D, 0x0B, 0x40 }, - { 0xEE, 0x2D, 0x0B, 0x40 }, - { 0xEE, 0x2D, 0x0B, 0x40 }, - { 0xEE, 0x2D, 0x0B, 0x40 }, - { 0xEE, 0x2D, 0x0B, 0x40 }, - { 0xF5, 0x25, 0x0B, 0x38 }, - { 0xF5, 0x25, 0x0B, 0x3C }, - { 0xF5, 0x25, 0x0B, 0x40 }, - { 0xF5, 0x25, 0x1B, 0x40 }, - { 0xF5, 0x25, 0x1B, 0x40 }, - { 0xF5, 0x25, 0x1B, 0x40 }, - { 0xF5, 0x25, 0x1B, 0x40 }, - { 0xF5, 0x25, 0x1B, 0x40 }, - { 0xFD, 0x25, 0x2B, 0x40 }, - { 0xFD, 0x25, 0x2B, 0x40 }, - { 0xFD, 0x25, 0x2B, 0x40 }, - { 0xFD, 0x25, 0x2B, 0x40 }, - { 0xFD, 0x25, 0x27, 0x40 }, - { 0xFD, 0x25, 0x27, 0x40 }, - { 0xFD, 0x25, 0x27, 0x40 }, - { 0xFD, 0x25, 0x23, 0x40 }, - { 0xFD, 0x25, 0x23, 0x40 }, - { 0xFD, 0x25, 0x23, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFD, 0x25, 0x33, 0x40 }, - { 0xFC, 0x25, 0x33, 0x40 }, - { 0xFC, 0x25, 0x33, 0x40 }, - { 0xFC, 0x25, 0x43, 0x40 }, - { 0xFC, 0x25, 0x43, 0x40 }, - { 0xFC, 0x25, 0x43, 0x40 }, - { 0xFC, 0x25, 0x43, 0x44 }, - { 0xFC, 0x25, 0x43, 0x48 }, - { 0xFC, 0x25, 0x43, 0x4C }, - { 0xFC, 0x25, 0x43, 0xBC }, - { 0xFC, 0x25, 0x43, 0xC0 }, - { 0xFC, 0x25, 0x43, 0xC0 }, - { 0xFC, 0x23, 0x43, 0xC0 }, - { 0xFC, 0x23, 0x43, 0xC0 }, - { 0xFC, 0x23, 0x43, 0xC0 }, - { 0xFC, 0x21, 0x43, 0xC0 }, - { 0xFC, 0x21, 0x43, 0xC0 }, - { 0xFC, 0x21, 0x53, 0xC0 }, - { 0xFC, 0x21, 0x53, 0xC0 }, - { 0xFC, 0x21, 0x53, 0xC0 } -}; - -RLPS_EQUALIZER_RAM t1_rlps_perf_mode_ram_table[] = -{ - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xFE, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xF6, 0x18, 0x40 }, - { 0x03, 0xEE, 0x18, 0x40 }, - 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{ 0x37, 0x7E, 0x1A, 0x2C }, - { 0x37, 0x7E, 0x1A, 0xAC }, - { 0x37, 0x7E, 0x1A, 0xAC }, - { 0x37, 0x7E, 0x1A, 0xAC }, - { 0x37, 0x7E, 0x1A, 0xAC }, - { 0x3F, 0x7E, 0x2A, 0xAC }, - { 0x3F, 0x7E, 0x2A, 0xAC }, - { 0x3F, 0x76, 0x2A, 0xAC }, - { 0x3F, 0x86, 0x2B, 0x2C }, - { 0x3F, 0x7E, 0x2B, 0x2C }, - { 0x47, 0x7E, 0x2B, 0x2C }, - { 0x47, 0x7E, 0x2F, 0x2C }, - { 0x47, 0x7E, 0x2F, 0x2C }, - { 0x47, 0x7E, 0x2F, 0x2C }, - { 0x47, 0x76, 0x2F, 0x2C }, - { 0x4F, 0x76, 0x2F, 0x2C }, - { 0x4F, 0x76, 0x2F, 0x2C }, - { 0x4F, 0x6E, 0x2F, 0x2C }, - { 0x4F, 0x6E, 0x2F, 0x2C }, - { 0x4F, 0x6E, 0x2F, 0x2C }, - { 0x57, 0x6E, 0x2F, 0x2C }, - { 0x57, 0x6E, 0x2F, 0x2C }, - { 0x57, 0x6E, 0x3F, 0x2C }, - { 0x57, 0x6E, 0x3F, 0x2C }, - { 0x57, 0x6E, 0x3F, 0x2C }, - { 0x5F, 0x6E, 0x3F, 0x2C }, - { 0x5F, 0x6E, 0x4F, 0x2C }, - { 0x5F, 0x6E, 0x4F, 0x2C }, - { 0x5F, 0x6E, 0x4F, 0x2C }, - { 0x5F, 0x66, 0x4F, 0x2C }, - { 0x67, 0x66, 0x4F, 0x2C }, - { 0x67, 0x66, 0x4F, 0x2C }, - { 0x67, 0x5E, 0x4F, 0x2C }, - { 0x67, 0x5E, 0x4F, 0x2C }, - { 0x67, 0x66, 0x4F, 0x2C }, - { 0x67, 0x66, 0x4F, 0x2C }, - { 0x67, 0x66, 0x5F, 0x2C }, - { 0x6F, 0x6E, 0x5F, 0x2C }, - { 0x6F, 0x6E, 0x6F, 0x2C }, - { 0x6F, 0x6E, 0x6F, 0x2C }, - { 0x6F, 0x6E, 0x7F, 0x2C }, - { 0x6F, 0x6E, 0x7F, 0x2C }, - { 0x6F, 0x6E, 0x7F, 0x2C }, - { 0x77, 0x66, 0x7F, 0x2C }, - { 0x77, 0x66, 0x7F, 0x2C }, - { 0x77, 0x5E, 0x6F, 0x2C }, - { 0x77, 0x5E, 0x7F, 0x2C }, - { 0x77, 0x5E, 0x7F, 0x2C }, - { 0x7F, 0x5E, 0x7F, 0x2C }, - { 0x7F, 0x5E, 0x8F, 0x2C }, - { 0x7F, 0x5E, 0x8F, 0x2C }, - { 0x7F, 0x5E, 0x8F, 0x2C }, - { 0x87, 0x56, 0x8F, 0x2C }, - { 0x87, 0x56, 0x8F, 0x2C }, - { 0x87, 0x56, 0x8F, 0x2C }, - { 0x87, 0x4E, 0x8F, 0x2C }, - { 0x87, 0x4E, 0x8F, 0x2C }, - { 0x87, 0x4E, 0x8F, 0x2C }, - { 0x8F, 0x4E, 0x9F, 0x2C }, - { 0x8F, 0x4E, 0x9F, 0x2C }, - { 0x8F, 0x4E, 0xAF, 0x2C }, - { 0x8F, 0x4E, 0xAF, 0x2C }, - { 0x8F, 0x4E, 0xAF, 0x2C }, - { 0x97, 0x4E, 0xAF, 0x2C }, - { 0x97, 0x4E, 0xAF, 0x2C }, - { 0x97, 0x4E, 0xAB, 0x2C }, - { 0x97, 0x4E, 0xAB, 0x2C }, - { 0x97, 0x4E, 0xAB, 0x2C }, - { 0x9F, 0x4E, 0xAB, 0x2C }, - { 0x9F, 0x4E, 0xBB, 0x2C }, - { 0x9F, 0x4E, 0xBB, 0x2C }, - { 0x9F, 0x4E, 0xBB, 0x2C }, - { 0x9F, 0x4E, 0xCB, 0x2C }, - { 0xA7, 0x4E, 0xCB, 0x2C }, - { 0xA7, 0x4E, 0xCB, 0x2C }, - { 0xA7, 0x46, 0xCB, 0x2C }, - { 0xA7, 0x46, 0xCB, 0x2C }, - { 0xA7, 0x46, 0xCB, 0x2C }, - { 0xA7, 0x46, 0xDB, 0x2C }, - { 0xAF, 0x46, 0xDB, 0x2C }, - { 0xAF, 0x46, 0xEB, 0x2C }, - { 0xAF, 0x46, 0xEB, 0x2C }, - { 0xAF, 0x4E, 0xEB, 0x2C }, - { 0xAE, 0x4E, 0xEB, 0x2C }, - { 0xAE, 0x4E, 0xEB, 0x2C }, - { 0xB5, 0x46, 0xFB, 0x2C }, - { 0xB5, 0x54, 0xFB, 0x2C }, - { 0xB5, 0x4C, 0xFB, 0x2C }, - { 0xB5, 0x54, 0xFB, 0x2C }, - { 0xB5, 0x54, 0xFB, 0x2C }, - { 0xBD, 0x54, 0xFB, 0x2C }, - { 0xBD, 0x4C, 0xFB, 0x2C }, - { 0xBD, 0x4C, 0xFB, 0x2C }, - { 0xBD, 0x4C, 0xFB, 0x2C }, - { 0xBD, 0x44, 0xEB, 0x2C }, - { 0xC5, 0x44, 0xFB, 0x2C }, - { 0xC5, 0x44, 0xFB, 0x2C }, - { 0xC5, 0x44, 0xFB, 0x2C }, - { 0xC5, 0x45, 0x0B, 0x2C }, - { 0xC5, 0x45, 0x0B, 0x2C }, - { 0xC5, 0x45, 0x0B, 0x2C }, - { 0xCD, 0x45, 0x0B, 0x2C }, - { 0xCD, 0x45, 0x0B, 0x2C }, - { 0xCD, 0x3D, 0x0B, 0x2C }, - { 0xCD, 0x3D, 0x0B, 0x2C }, - { 0xCD, 0x3D, 0x0B, 0x2C }, - { 0xD5, 0x3D, 0x0B, 0x2C }, - { 0xD5, 0x3D, 0x0B, 0x2C }, - { 0xD5, 0x3D, 0x1B, 0x2C }, - { 0xD5, 0x3D, 0x1B, 0x2C }, - { 0xD5, 0x3D, 0x1B, 0x2C }, - { 0xDD, 0x3D, 0x1B, 0x2C }, - { 0xDD, 0x3D, 0x1B, 0x2C }, - { 0xDD, 0x35, 0x1B, 0x2C }, - { 0xDD, 0x35, 0x1B, 0x2C }, - { 0xDD, 0x35, 0x1B, 0x2C }, - { 0xE5, 0x35, 0x1B, 0x2C }, - { 0xE5, 0x35, 0x1B, 0x2C }, - { 0xE5, 0x2D, 0x1B, 0x2C }, - { 0xE5, 0x2D, 0x1B, 0x2C }, - { 0xE5, 0x2D, 0x3B, 0x2C }, - { 0xED, 0x2D, 0x4B, 0x2C }, - { 0xED, 0x2D, 0x1B, 0xA8 }, - { 0xED, 0x2D, 0x1B, 0xAC }, - { 0xED, 0x2D, 0x17, 0xAC }, - { 0xED, 0x2D, 0x17, 0xAC }, - { 0xED, 0x2D, 0x27, 0xAC }, - { 0xF5, 0x2D, 0x27, 0xAC }, - { 0xF5, 0x2D, 0x27, 0xAC }, - { 0xF5, 0x2D, 0x2B, 0xAC }, - { 0xF5, 0x2D, 0x2B, 0xAC }, - { 0xF5, 0x2D, 0x2B, 0xAC }, - { 0xFD, 0x2D, 0x2B, 0xAC }, - { 0xFD, 0x2B, 0x2B, 0xAC }, - { 0xFD, 0x2B, 0x2B, 0xAC }, - { 0xFD, 0x2B, 0x2B, 0xAC }, - { 0xFD, 0x2B, 0x2B, 0xAC }, - { 0xFD, 0x23, 0x2B, 0xAC }, - { 0xFD, 0x23, 0x2B, 0xAC }, - { 0xFD, 0x23, 0x2B, 0xAC }, - { 0xFD, 0x21, 0x2B, 0xAC }, - { 0xFD, 0x21, 0x2B, 0xAC }, - { 0xFD, 0x29, 0x2B, 0xAC }, - { 0xFD, 0x29, 0x2B, 0xAC }, - { 0xFD, 0x29, 0x27, 0xAC }, - { 0xFD, 0x29, 0x37, 0xAC }, - { 0xFD, 0x29, 0x23, 0xAC }, - { 0xFD, 0x29, 0x23, 0xAC }, - { 0xFD, 0x29, 0x23, 0xAC }, - { 0xFD, 0x29, 0x23, 0xAC }, - { 0xFD, 0x21, 0x23, 0xAC }, - { 0xFD, 0x21, 0x23, 0xAC }, - { 0xFD, 0x21, 0x23, 0xAC }, - { 0xFD, 0x21, 0x33, 0xAC }, - { 0xFD, 0x21, 0x33, 0xAC }, - { 0xFD, 0x21, 0x33, 0xAC }, - { 0xFD, 0x21, 0x43, 0xAC }, - { 0xFD, 0x21, 0x43, 0xAC }, - { 0xFD, 0x21, 0x43, 0xAC }, - { 0xFC, 0x21, 0x43, 0xAC }, - { 0xFC, 0x21, 0x43, 0xAC }, - { 0xFC, 0x19, 0x43, 0xAC }, - { 0xFC, 0x19, 0x43, 0xAC }, - { 0xFC, 0x19, 0x43, 0xAC }, - { 0xFC, 0x19, 0x43, 0xAC }, - { 0xFC, 0x19, 0x53, 0xAC }, - { 0xFC, 0x19, 0x53, 0xAC }, - { 0xFC, 0x19, 0x53, 0xAC }, - { 0xFC, 0x19, 0x53, 0xAC }, - { 0xFC, 0x19, 0x63, 0xAC }, - { 0xFC, 0x19, 0x63, 0xAC }, - { 0xFC, 0x19, 0x63, 0xAC }, - { 0xFC, 0x19, 0x73, 0xAC }, - { 0xFC, 0x19, 0x73, 0xAC }, - { 0xFC, 0x19, 0x73, 0xAC }, - { 0xFC, 0x19, 0x73, 0xAC }, - { 0xFC, 0x19, 0x73, 0xAC }, - { 0xFC, 0x19, 0x83, 0xAC }, - { 0xFC, 0x19, 0x83, 0xAC }, - { 0xFC, 0x19, 0x83, 0xAC }, - { 0xFC, 0x19, 0x83, 0xAC }, - { 0xFC, 0x19, 0x83, 0xAC }, - { 0xFC, 0x19, 0x93, 0xAC }, - { 0xFC, 0x19, 0x93, 0xAC }, - { 0xFC, 0x19, 0x93, 0xAC }, - { 0xFC, 0x19, 0xA3, 0xAC }, - { 0xFC, 0x19, 0xA3, 0xAC }, - { 0xFC, 0x19, 0xB3, 0xAC }, - { 0xFC, 0x19, 0xB3, 0xAC }, - { 0xFC, 0x19, 0xB3, 0xAC }, - { 0xFC, 0x19, 0xB3, 0xAC } -}; - - -static void ClearTemplate(sdla_t *); -static unsigned char InitTemplate(sdla_t *); -static void InitLineReceiver(sdla_t *); - -static void ClearTPSCReg(sdla_t *); -static void ClearRPSCReg(sdla_t *); - -static int WriteTPSCReg(sdla_t *, int, int, unsigned char); -static unsigned char ReadTPSCReg(sdla_t *, int, int); - -static int WriteRPSCReg(sdla_t *, int, int, unsigned char); -static unsigned char ReadRPSCReg(sdla_t *, int, int); - -static void DisableAllChannels(sdla_t *); -static void EnableAllChannels(sdla_t *); -static int DisableTxChannel(sdla_t *, int); -static int DisableRxChannel(sdla_t *, int); -static int EnableTxChannel(sdla_t *, int); -static int EnableRxChannel(sdla_t *, int); - -static void sdla_te_set_intr(sdla_t *); -static void sdla_te_tx_intr(sdla_t *); -static void sdla_te_rx_intr(sdla_t *); -static void sdla_t1_rx_intr(sdla_t *); -static void sdla_e1_rx_intr(sdla_t *); - -static void sdla_te_set_status(sdla_t *, unsigned long); -static void sdla_te_enable_timer(sdla_t *, unsigned long); - -static int sdla_te_linelb(sdla_t *, unsigned char); -static int sdla_te_paylb(sdla_t *, unsigned char); -static int sdla_te_ddlb(sdla_t *, unsigned char); -static int sdla_te_lb(sdla_t *, unsigned char); - - -static void -ClearTemplate(sdla_t *card) -{ - int i = 0, j = 0; - unsigned int indirect_addr = 0x00; - - for (i = FIRST_UI; i <= LAST_UI; i++) { - for (j = FIRST_SAMPLE; j <= LAST_SAMPLE; j++) { - indirect_addr = (j << 3) | i; - /* Set up the indirect address */ - WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr); - WRITE_REG(REG_XLPG_WAVEFORM_DATA, 0x00); - } - } -} - -static unsigned char -InitTemplate(sdla_t *card) -{ - sdla_te_cfg_t* te_cfg = &card->fe_te.te_cfg; - int i = 0, j = 0; - unsigned char indirect_addr = 0x00, xlpg_scale = 0x00; - TX_WAVEFORM* tx_waveform = NULL; - - if (IS_T1(&card->fe_te.te_cfg)) { - switch (te_cfg->lbo) { - case WAN_T1_LBO_0_DB: - tx_waveform = &t1_tx_waveform_lh_0db; - xlpg_scale = 0x0C; - break; - case WAN_T1_LBO_75_DB: - tx_waveform = &t1_tx_waveform_lh_75db; - xlpg_scale = 0x07; - break; - case WAN_T1_LBO_15_DB: - tx_waveform = &t1_tx_waveform_lh_15db; - xlpg_scale = 0x03; - break; - case WAN_T1_LBO_225_DB: - tx_waveform = &t1_tx_waveform_lh_225db; - xlpg_scale = 0x02; - break; - case WAN_T1_0_110: - tx_waveform = &t1_tx_waveform_sh_110ft; - xlpg_scale = 0x0C; - break; - case WAN_T1_110_220: - tx_waveform = &t1_tx_waveform_sh_220ft; - xlpg_scale = 0x10; - break; - case WAN_T1_220_330: - tx_waveform = &t1_tx_waveform_sh_330ft; - xlpg_scale = 0x11; - break; - case WAN_T1_330_440: - tx_waveform = &t1_tx_waveform_sh_440ft; - xlpg_scale = 0x12; - break; - case WAN_T1_440_550: - tx_waveform = &t1_tx_waveform_sh_550ft; - xlpg_scale = 0x14; - break; - case WAN_T1_550_660: - tx_waveform = &t1_tx_waveform_sh_660ft; - xlpg_scale = 0x15; - break; - default: - /* Use 0DB as a default value */ - tx_waveform = &t1_tx_waveform_lh_0db; - xlpg_scale = 0x0C; - break; - } - } else { - tx_waveform = &e1_tx_waveform_120; - xlpg_scale = 0x0C; - /*xlpg_scale = 0x0B; */ - } - - for (i = FIRST_UI; i <= LAST_UI; i++) { - for (j = FIRST_SAMPLE; j <= LAST_SAMPLE; j++) { - indirect_addr = (j << 3) | i; - /* Set up the indirect address */ - WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr); - WRITE_REG(REG_XLPG_WAVEFORM_DATA, (*tx_waveform)[j][i]); - } - } - return xlpg_scale; -} - - -static void -InitLineReceiver(sdla_t *card) -{ - int ram_addr = 0x00; - RLPS_EQUALIZER_RAM *rlps_ram_table = NULL; - - if (IS_E1(&card->fe_te.te_cfg)) { - rlps_ram_table = e1_rlps_ram_table; - } else { - if (card->fe_te.te_cfg.high_impedance_mode == WAN_YES) { - log(LOG_INFO, "%s: Setting to High-Impedance Mode!\n", - card->devname); - rlps_ram_table = t1_rlps_perf_mode_ram_table; - } else { - rlps_ram_table = t1_rlps_ram_table; - } - } - for (ram_addr = 0; ram_addr <= 255; ram_addr++) { -/* ERRATA VVV */ - /* Configure a write into the RAM address */ - WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB); - /* Initiate write into the specified RAM address */ - WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr); - DELAY(100); -/* ERRATA ^^^ */ - /* Write 1st value from conten column */ - WRITE_REG(REG_RLPS_IND_DATA_1, rlps_ram_table[ram_addr].byte1); - /* Write 2st value from conten column */ - WRITE_REG(REG_RLPS_IND_DATA_2, rlps_ram_table[ram_addr].byte2); - /* Write 3st value from conten column */ - WRITE_REG(REG_RLPS_IND_DATA_3, rlps_ram_table[ram_addr].byte3); - /* Write 4st value from conten column */ - WRITE_REG(REG_RLPS_IND_DATA_4, rlps_ram_table[ram_addr].byte4); - /* Configure a write into the RAM address */ - WRITE_REG(REG_RLPS_EQ_RWB, 0x00); - /* Initiate write into the specified RAM address */ - WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr); -/* ERRATA VVV */ - DELAY(100); -/* ERRATA ^^^ */ - } -} - -static void -ClearTPSCReg(sdla_t *card) -{ - int channel = 0; - int start_channel = 0, stop_channel = 0; - - if (IS_E1(&card->fe_te.te_cfg)) { - start_channel = 0; - stop_channel = NUM_OF_E1_TIMESLOTS + 1; - } else { - start_channel = 1; - stop_channel = NUM_OF_T1_CHANNELS; - } - - for (channel = start_channel; channel <= stop_channel; channel++) { - WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, 0x00); - WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00); - WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00); - } - return; -} - -static void -ClearRPSCReg(sdla_t *card) -{ - int channel = 0; - int start_channel = 0, stop_channel = 0; - - if (IS_E1(&card->fe_te.te_cfg)) { - start_channel = 0; - stop_channel = NUM_OF_E1_TIMESLOTS + 1; - } else { - start_channel = 1; - stop_channel = NUM_OF_T1_CHANNELS; - } - - for (channel = start_channel; channel <= stop_channel; channel++) { - WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, 0x00); - WRITE_RPSC_REG(REG_RPSC_DATA_COND_BYTE, channel, 0x00); - WRITE_RPSC_REG(REG_RPSC_SIGNALING_BYTE, channel, 0x00); - } - return; -} - -/* - * Write value to TPSC indirect register. - * Arguments: card - Pointer to the card structure - * reg - Offset in TPSC indirect space. - * channel - Channel number. - * value - New PMC register value. - * Returns: 0 - success, otherwise - error - */ -static int -WriteTPSCReg(sdla_t *card, int reg, int channel, unsigned char value) -{ - unsigned char temp = 0x00; - int i = 0, busy_flag = 0; - int err = 0; - - reg += channel; - /* Set IND bit to 1 in TPSC to enable indirect access to - ** TPSC register */ - WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); - busy_flag = 1; - for (i = 0; i < MAX_BUSY_READ; i++) { - temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS); - if ((temp & BIT_TPSC_BUSY) == 0x0) { - busy_flag = 0; - break; - } - } - if (busy_flag == 1) { - log(LOG_INFO, "%s: Failed to write to TPSC Reg[%02x]<-%02x!\n", - card->devname, reg, value); - err = EBUSY; - goto write_tpsc_done; - } - - WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER, - (unsigned char)value); - WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, - (unsigned char)(reg & 0x7F)); - - for (i = 0; i < MAX_BUSY_READ; i++) { - temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS); - if ((temp & BIT_TPSC_BUSY) == 0x0) { - err = EBUSY; - goto write_tpsc_done; - } - } - log(LOG_INFO, "%s: Failed to write value to TPSC Reg=%02x, val=%02x.\n", - card->devname, reg, value); -write_tpsc_done: - /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */ - WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE); - return err; -} - -/* - * Read value from TPSC indirect register. - * - * Arguments: card - Pointer to the card structure - * reg - Offset in TPSC indirect space. - * channel - Channel number. - * Returns: Returns register value. - */ -static unsigned char -ReadTPSCReg(sdla_t *card, int reg, int channel) -{ - unsigned char tmp = 0x00, value = 0x00; - int i = 0, busy_flag = 0; - - reg += channel; - /* Set IND bit to 1 in TPSC to enable indirect access to - ** TPSC register */ - WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); - busy_flag = 1; - for (i = 0; i < MAX_BUSY_READ; i++) { - tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS); - if ((tmp & BIT_TPSC_BUSY) == 0x0) { - busy_flag = 0; - break; - } - } - if (busy_flag == 1) { - log(LOG_INFO, "%s: Failed to read value to TPSC Reg=%02x!\n", - card->devname, reg); - goto read_tpsc_done; - } - - WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, - (unsigned char)(reg | 0x80)); - - for (i = 0; i < MAX_BUSY_READ; i++) { - tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS); - if ((tmp & BIT_TPSC_BUSY) == 0x0) { - value = READ_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER); - goto read_tpsc_done; - } - } - log(LOG_INFO, "%s: Failed to read value to TPSC Reg=%02x.\n", - card->devname, reg); -read_tpsc_done: - /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */ - WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE); - return value; -} - -/* - * Write value to RPSC indirect register. - * - * Arguments: card - Pointer to the card structure - * reg - Offset in RPSC indirect space. - * channel - Channel number. - * value - New PMC register value. - * Returns: 0-success, otherwise - error - */ -static int -WriteRPSCReg(sdla_t* card, int reg, int channel, unsigned char value) -{ - unsigned char temp = 0x00; - int i = 0, busy_flag = 0; - int err = 0; - - reg += channel; - /* Set IND bit to 1 in RPSC to enable indirect access to - ** RPSC register*/ - WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND); - busy_flag = 1; - for (i = 0; i < MAX_BUSY_READ; i++) { - temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS); - if ((temp & BIT_RPSC_BUSY) == 0x0) { - busy_flag = 0; - break; - } - } - if (busy_flag == 1) { - log(LOG_INFO, "%s: Failed to write to RPSC Reg[%02x]<-%02x!\n", - card->devname, reg, value); - err = EBUSY; - goto write_rpsc_done; - } - - WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER, (unsigned char)value); - WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, - (unsigned char)(reg & 0x7F)); - - for (i = 0; i < MAX_BUSY_READ; i++) { - temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS); - if ((temp & BIT_RPSC_BUSY) == 0x0) { - err = EBUSY; - goto write_rpsc_done; - } - } - log(LOG_INFO, "%s: Failed to write value to RPSC Reg=%02x, val=%02x.\n", - card->devname, reg, value); -write_rpsc_done: - /* Set PCCE bit to 1 in RPSC to enable modifing the RPSC register */ - WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE); - return err; -} - -/* - * Read value from RPSC indirect register. - * Arguments: card - Pointer to the card structure - * reg - Offset in RPSC indirect space. - * channel - Channel number - * Returns: Returns register value. - */ -static unsigned char ReadRPSCReg(sdla_t* card, int reg, int channel) -{ - unsigned char tmp = 0x00, value = 0x00; - int i = 0,busy_flag = 0; - - reg += channel; - /* Set IND bit to 1 in RPSC to enable indirect access to - ** RPSC register*/ - WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND); - busy_flag = 1; - for (i = 0; i < MAX_BUSY_READ; i++) { - tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS); - if ((tmp & BIT_RPSC_BUSY) == 0x0) { - busy_flag = 0; - break; - } - } - if (busy_flag == 1) { - log(LOG_INFO, "%s: Failed to read value to RPSC Reg=%02x!\n", - card->devname, reg); - goto read_rpsc_done; - } - - WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, - (unsigned char)(reg | 0x80)); - - for (i = 0; i < MAX_BUSY_READ; i++) { - tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS); - if ((tmp & BIT_RPSC_BUSY) == 0x0) { - value = READ_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER); - goto read_rpsc_done; - } - } - log(LOG_INFO, "%s: Failed to read value to RPSC Reg=%02x.\n", - card->devname, reg); -read_rpsc_done: - /* Set PCCE bit to 1 in RPSC to enable modifing the RPSC register */ - WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE); - return value; -} - - -/* - * Description: Disable All channels for RX/TX - * Arguments: card - Pointer to the card structure. - * Returns: none - */ -static void DisableAllChannels(sdla_t* card) -{ - int i = 0; - - if (IS_E1(&card->fe_te.te_cfg)) { - DisableTxChannel(card, E1_FRAMING_TIMESLOT); - DisableRxChannel(card, E1_FRAMING_TIMESLOT); - for (i = 1; i <= NUM_OF_E1_TIMESLOTS; i++) { - DisableTxChannel(card, i); - DisableRxChannel(card, i); - } - } else { - for (i = 1; i <= NUM_OF_T1_CHANNELS; i++) { - DisableTxChannel(card, i); - DisableRxChannel(card, i); - } - } -} - -/* - * Description: Enable All channels. - * Arguments: card - Pointer to the card structure. - * Returns: none - */ -static void EnableAllChannels(sdla_t* card) -{ - int i = 0; - - if (IS_E1(&card->fe_te.te_cfg)) { - int first_ts = - (card->fe_te.te_cfg.frame == WAN_FR_UNFRAMED) ? - 0 : 1; - - DisableTxChannel(card, E1_FRAMING_TIMESLOT); - DisableRxChannel(card, E1_FRAMING_TIMESLOT); - for (i = first_ts; i <= NUM_OF_E1_TIMESLOTS; i++) { - EnableTxChannel(card, i); - EnableRxChannel(card, i); - } - } else { - for (i = 1; i <= NUM_OF_T1_CHANNELS; i++) { - EnableTxChannel(card, i); - EnableRxChannel(card, i); - } - } -} - -/* - * Description: Enable Tx for specific channel - * Arguments: card - pointer to the card structure - * channel - channel number - * Returns: 0-success, otherwise-error - */ -static int EnableTxChannel(sdla_t* card, int channel) -{ - sdla_te_cfg_t* te_cfg = &card->fe_te.te_cfg; - - if (te_cfg->lcode == WAN_LC_AMI) { - /* ZCs=1 AMI*/ - WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, - (((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) & - MASK_TPSC_DATA_CTRL_BYTE) & - ~BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0) | - BIT_TPSC_DATA_CTRL_BYTE_ZCS1)); - } else { - WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, - ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) & - MASK_TPSC_DATA_CTRL_BYTE) & - ~(BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0 | - BIT_TPSC_DATA_CTRL_BYTE_ZCS1 | - BIT_TPSC_DATA_CTRL_BYTE_ZCS0))); - } - - if (IS_E1(&card->fe_te.te_cfg)) { - /* Set SUBS=DS[0]=DS[1]=0x0 - no change to PCM timeslot data */ - WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel, - (READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) & - ~(BIT_TPSC_E1_CTRL_BYTE_SUBS | - BIT_TPSC_E1_CTRL_BYTE_DS0 | - BIT_TPSC_E1_CTRL_BYTE_DS1))); - } else { - WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00); - } - - /* Erase contents of IDLE code byte */ - WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00); - - return 0; -} -/* - * Description: Enable Rx for specific channel - * Arguments: card - pointer to the card structure - * channel - channel number - * Returns: 0-success, otherwise-error - */ -static int EnableRxChannel(sdla_t* card, int channel) -{ - /* Set DTRPC bit to 0 in RPSC */ - WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, - ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) & - MASK_RPSC_DATA_CTRL_BYTE) & - ~BIT_RPSC_DATA_CTRL_BYTE_DTRKC)); - return 0; -} - -/* - * Description: Disable Tx for specific channel - * Arguments: card - pointer to the card structure - * channel - channel number - * Returns: 0-success, otherwise-error - */ -static int DisableTxChannel(sdla_t* card, int channel) -{ - /* Set IDLE_DS0 to 1 for an IDLE code byte will insert and - * BTCLK will suppressed - */ - WRITE_TPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, - ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) & - MASK_TPSC_DATA_CTRL_BYTE) | BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0)); - if (IS_E1(&card->fe_te.te_cfg)) { - /* Set SUBS=1, DS0=0 - data substitution on - IDLE code - ** replaces BTPCM timeslot data */ - WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel, - ((READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) & - ~BIT_TPSC_E1_CTRL_BYTE_DS0) | BIT_TPSC_E1_CTRL_BYTE_SUBS)); - } else { - WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00); - } - /* Erase contents of IDLE code byte */ - WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x55); - return 0; -} - -/* - * Description: Disable Rx for specific channel - * Arguments: card - pointer to the card structure - * channel - channel number - * Returns: 0-success, otherwise-error - */ -static int DisableRxChannel(sdla_t* card, int channel) -{ - /* Set DTRPC bit to 1 in RPSC to hold low for the duration of - ** the channel */ - WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, - ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) & - MASK_RPSC_DATA_CTRL_BYTE) | BIT_RPSC_DATA_CTRL_BYTE_DTRKC)); - return 0; -} - -/* - * Set default T1 configuration - */ -int -sdla_te_defcfg(void *pte_cfg) -{ - sdla_te_cfg_t *te_cfg = (sdla_te_cfg_t*)pte_cfg; - - te_cfg->media = WAN_MEDIA_T1; - te_cfg->lcode = WAN_LC_B8ZS; - te_cfg->frame = WAN_FR_ESF; - te_cfg->lbo = WAN_T1_LBO_0_DB; - te_cfg->te_clock = WAN_NORMAL_CLK; - te_cfg->active_ch = ENABLE_ALL_CHANNELS; - te_cfg->high_impedance_mode = WAN_NO; - return 0; -} - - -int -sdla_te_setcfg(struct ifnet *ifp, struct ifmedia *ifm) -{ - struct ifreq ifr; - struct if_settings ifs; - - wanpipe_common_t *common = (wanpipe_common_t *)ifp->if_softc; - sdla_t *card = (sdla_t*)common->card; - sdla_te_cfg_t *te_cfg = (sdla_te_cfg_t*)&card->fe_te.te_cfg; - int ret; - - if (IFM_TYPE(ifm->ifm_media) != IFM_TDM) - return (EINVAL); - - bcopy(ifp->if_xname, ifr.ifr_name, sizeof(ifr.ifr_name)); - bzero(&ifs, sizeof(ifs)); - ifr.ifr_data = (caddr_t) &ifs; - - if ((ifm->ifm_media & IFM_OMASK) == IFM_TDM_PPP) - ifs.type = IF_PROTO_PPP; - else if ((ifm->ifm_media & IFM_OMASK) == 0) - ifs.type = IF_PROTO_CISCO; - else { - log(LOG_INFO, "%s: Unsupported ifmedia options\n", - card->devname); - return (EINVAL); - } - - ret = wp_lite_set_proto(ifp, &ifr); - if (ret != 0) - return (ret); - - switch (IFM_SUBTYPE(ifm->ifm_media)) { - case IFM_TDM_T1: -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting T1 media type!\n", - card->devname); -#endif /* DEBUG_INIT */ - te_cfg->media = WAN_MEDIA_T1; - te_cfg->lcode = WAN_LC_B8ZS; - te_cfg->frame = WAN_FR_ESF; - break; - case IFM_TDM_T1_AMI: -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting T1 AMI media type!\n", - card->devname); -#endif /* DEBUG_INIT */ - te_cfg->media = WAN_MEDIA_T1; - te_cfg->lcode = WAN_LC_AMI; - te_cfg->frame = WAN_FR_ESF; - break; - case IFM_TDM_E1: -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting E1 media type!\n", - card->devname); -#endif /* DEBUG_INIT */ - te_cfg->media = WAN_MEDIA_E1; - te_cfg->lcode = WAN_LC_HDB3; - te_cfg->frame = WAN_FR_NCRC4; - break; - case IFM_TDM_E1_AMI: -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting E1 AMI media type!\n", - card->devname); -#endif /* DEBUG_INIT */ - te_cfg->media = WAN_MEDIA_E1; - te_cfg->lcode = WAN_LC_AMI; - te_cfg->frame = WAN_FR_NCRC4; - break; - default: - log(LOG_INFO, "%s: Unsupported ifmedia type (%04X)\n", - card->devname, ifm->ifm_media); - return (EINVAL); - } - - return (0); -} - -/* - * Set timeslot map - */ -void -sdla_te_settimeslot(void* pcard, unsigned long ts_map) -{ - sdla_t *card = (sdla_t*)pcard; - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting timeslot map to %08lX\n", - card->devname, ts_map); -#endif /* DEBUG_INIT */ - if (IS_T1(&card->fe_te.te_cfg)) { - /* For T1, Shift timeslot map left by 1, because bit 0 - ** is not been used by T1 timeslot map (bit 1 is used for - ** channel 1, bit 2 is used for channel 2 and so on). */ - ts_map = ts_map >> 1; - } - card->fe_te.te_cfg.active_ch = ts_map; - return; -} - -unsigned long -sdla_te_gettimeslot(void* pcard) -{ - sdla_t *card = (sdla_t*)pcard; - unsigned long ts_map = card->fe_te.te_cfg.active_ch; - - if (IS_T1(&card->fe_te.te_cfg)) { - /* See explanation before. */ - ts_map = ts_map << 1; - } - return ts_map; -} - -/* - * Configure Sangoma TE1 board - * - * Arguments: - * Returns: 0 - TE1 configred successfully, otherwise EINVAL. - */ -short -sdla_te_config(void* card_id) -{ - sdla_t *card = (sdla_t*)card_id; - sdla_te_cfg_t *te_cfg = &card->fe_te.te_cfg; - u_int16_t adapter_type; - unsigned char value = 0x00, xlpg_scale = 0x00; - int channel_range = (IS_T1(&card->fe_te.te_cfg)) ? - NUM_OF_T1_CHANNELS : NUM_OF_E1_TIMESLOTS; - int i = 0; - - WAN_ASSERT(card == NULL); - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting %s configuration!\n", - card->devname, - IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"); - if (IS_T1(&card->fe_te.te_cfg)) { - log(LOG_DEBUG, "%s: Line decoding %s\n", - card->devname, - (te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "B8ZS"); - log(LOG_DEBUG, "%s: Frame type %s\n", - card->devname, - (te_cfg->frame == WAN_FR_ESF) ? "ESF" : - (te_cfg->frame == WAN_FR_D4) ? "D4" : "Unframed"); - switch (te_cfg->lbo) { - case WAN_T1_LBO_0_DB: - log(LOG_DEBUG, "%s: LBO 0 dB\n", card->devname); - break; - case WAN_T1_LBO_75_DB: - log(LOG_DEBUG, "%s: LBO 7.5 dB\n", card->devname); - break; - case WAN_T1_LBO_15_DB: - log(LOG_DEBUG, "%s: LBO 15 dB\n", card->devname); - break; - case WAN_T1_LBO_225_DB: - log(LOG_DEBUG, "%s: LBO 22.5 dB\n", card->devname); - break; - case WAN_T1_0_110: - log(LOG_DEBUG, "%s: LBO 0-110 ft.\n", card->devname); - break; - case WAN_T1_110_220: - log(LOG_DEBUG, "%s: LBO 110-220 ft.\n", card->devname); - break; - case WAN_T1_220_330: - log(LOG_DEBUG, "%s: LBO 220-330 ft.\n", card->devname); - break; - case WAN_T1_330_440: - log(LOG_DEBUG, "%s: LBO 330-440 ft.\n", card->devname); - break; - case WAN_T1_440_550: - log(LOG_DEBUG, "%s: LBO 440-550 ft.\n", card->devname); - break; - case WAN_T1_550_660: - log(LOG_DEBUG, "%s: LBO 550-660 ft.\n", - card->devname); - break; - } - } else { - log(LOG_DEBUG, "%s: Line decoding %s\n", card->devname, - (te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "HDB3"); - log(LOG_DEBUG, "%s: Frame type %s\n", card->devname, - (te_cfg->frame == WAN_FR_CRC4) ? "CRC4" : - (te_cfg->frame == WAN_FR_NCRC4) ? "non-CRC3" : - "Unframed"); - } - log(LOG_DEBUG, "%s: Clock mode %s\n", card->devname, - (te_cfg->te_clock == WAN_NORMAL_CLK) ? "Normal" : "Master"); -#endif /* DEBUG_INIT */ - - /* 1. Initiate software reset of the COMET */ - /* Set RESET=1 to place COMET into RESET */ - WRITE_REG(REG_RESET, BIT_RESET); - - /* Set RESET=0, disable software reset. COMET in default mode. */ - WRITE_REG(REG_RESET, 0x0/*~BIT_RESET*/); - - /* 2.Setup the XLPG(Transmit pulse template) to clear the pulse - ** template */ - ClearTemplate(card); - xlpg_scale = InitTemplate(card); - - /* Program PMC for T1/E1 mode (Reg 0x00) */ - if (IS_E1(&card->fe_te.te_cfg)) { - if (adapter_type & A101_ADPTR_T1E1_MASK) { - WRITE_REG(REG_GLOBAL_CFG, - BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE | - BIT_GLOBAL_E1); - } else { - WRITE_REG(REG_GLOBAL_CFG, - BIT_GLOBAL_PIO_OE | BIT_GLOBAL_E1); - } - } else { - if (adapter_type & A101_ADPTR_T1E1_MASK) { - WRITE_REG(REG_GLOBAL_CFG, - BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE); - } - } - - /* Set SCALE[4-0] value in XLPG Line driver Configuration (Reg. 0xF0) */ - WRITE_REG(REG_XLPG_LINE_CFG, xlpg_scale); - - /* Set system clock and XCLK (Reg 0xD6) */ - if (IS_T1(&card->fe_te.te_cfg)) { - WRITE_REG(REG_CSU_CFG, BIT_CSU_MODE0); - /*WRITE_REG(REG_CSU_CFG, - ** BIT_CSU_MODE2 | BIT_CSU_MODE1 | BIT_CSU_MODE0); */ - } else { - WRITE_REG(REG_CSU_CFG, 0x00); - } - - /* Set Line decoding (Reg. 0x10) */ - if (te_cfg->lcode == WAN_LC_AMI) { - WRITE_REG(REG_CDRC_CFG, BIT_CDRC_CFG_AMI); - } else { - WRITE_REG(REG_CDRC_CFG, 0x00); - } - - /* Program the RX-ELST/TX-ELST for the appropriate mode - ** (Reg 0x1C, 0x20)*/ - if (IS_E1(&card->fe_te.te_cfg)) { - WRITE_REG(REG_RX_ELST_CFG, BIT_RX_ELST_IR | BIT_RX_ELST_OR); - WRITE_REG(REG_TX_ELST_CFG, BIT_TX_ELST_IR | BIT_RX_ELST_OR); - } else { - WRITE_REG(REG_RX_ELST_CFG, 0x00); - WRITE_REG(REG_TX_ELST_CFG, 0x00); - } - - value = 0x00; - if (IS_E1(&card->fe_te.te_cfg)) { - /* Program the trasmitter framing and line decoding - ** (Reg. 0x80) */ - if (te_cfg->lcode == WAN_LC_AMI) { - value |= BIT_E1_TRAN_AMI; - } - if (te_cfg->frame == WAN_FR_CRC4) { - value |= BIT_E1_TRAN_GENCRC; - } else if (te_cfg->frame == WAN_FR_UNFRAMED) { - value |= BIT_E1_TRAN_FDIS; - } - /* E1 TRAN Configuration (Reg 0x80) */ - WRITE_REG(REG_E1_TRAN_CFG, value); - /* Configure the receive framer (Reg 0x90) */ - value = 0x00; - if (te_cfg->frame == WAN_FR_CRC4) { - value |= - (BIT_E1_FRMR_CRCEN | - BIT_E1_FRMR_CASDIS | - BIT_E1_FRMR_REFCRCEN); - } else if (te_cfg->frame == WAN_FR_NCRC4) { - value |= BIT_E1_FRMR_CASDIS; - } - WRITE_REG(REG_E1_FRMR_CFG, value); - } else { - /* Set framing format & line decoding for transmitter - ** (Reg 0x54) */ - if (te_cfg->lcode == WAN_LC_B8ZS) { - value |= BIT_T1_XBAS_B8ZS; - } else { - value |= BIT_T1_XBAS_ZCS0; - } - if (te_cfg->frame == WAN_FR_ESF) { - value |= BIT_T1_XBAS_ESF; - } - WRITE_REG(REG_T1_XBAS_CFG, value); - - /* Program framing format for receiving (Reg. 0x48) */ - value = 0x00; - if (te_cfg->frame == WAN_FR_ESF) { - value = BIT_T1_FRMR_ESF | BIT_T1_FRMR_ESFFA; - } - WRITE_REG(REG_T1_FRMR_CFG, value); - - /* Program the transmitter framing format and line deconding - ** (Reg. 0x60) */ - value = 0x00; - if (te_cfg->frame == WAN_FR_ESF) { - value = BIT_T1_ALMI_CFG_ESF; - } - WRITE_REG(REG_T1_ALMI_CFG, value); - } - - /* Configure the SIGX configuration register */ - if (IS_E1(&card->fe_te.te_cfg)) { - WRITE_REG(REG_SIGX_CFG, 0x00); - } else { - value = READ_REG(REG_SIGX_CFG); - if (te_cfg->frame == WAN_FR_ESF) { - value |= BIT_SIGX_ESF; - } - WRITE_REG(REG_SIGX_CFG, value); - } - /* Program the BTIF for the frame pulse mode */ - value = 0x00; - if (IS_E1(&card->fe_te.te_cfg)) { - value |= BIT_BTIF_RATE0; - } - if (te_cfg->lcode == WAN_LC_AMI) { - value |= BIT_BTIF_NXDS0_0; - } else if (te_cfg->frame != WAN_FR_UNFRAMED) { - value |= BIT_BTIF_NXDS0_1; - } - - if (adapter_type & A101_ADPTR_T1E1_MASK) { - value |= (BIT_BTIF_CMODE | BIT_BTIF_DE | BIT_BTIF_FE); - } - WRITE_REG(REG_BTIF_CFG, value); - /* Set the type of frame pulse on the backplane */ - value = 0x00; - - if (adapter_type & A101_ADPTR_T1E1_MASK) { - value = BIT_BTIF_FPMODE; - } - WRITE_REG(REG_BTIF_FR_PULSE_CFG, value); - - /* Program the BRIF for the frame pulse mode */ - value = 0x00; - if (IS_E1(&card->fe_te.te_cfg)) { - value |= BIT_BRIF_RATE0; - } - if (te_cfg->lcode == WAN_LC_AMI) { - value |= BIT_BRIF_NXDS0_0; - } else if (te_cfg->frame != WAN_FR_UNFRAMED) { - value |= BIT_BRIF_NXDS0_1; - } - if (adapter_type & A101_ADPTR_T1E1_MASK) { - value |= BIT_BRIF_CMODE; - } - WRITE_REG(REG_BRIF_CFG, value); - /* Set the type of frame pulse on the backplane */ - value = 0x00; - - if (adapter_type & A101_ADPTR_T1E1_MASK) { - value = BIT_BRIF_FPMODE; - } - WRITE_REG(REG_BRIF_FR_PULSE_CFG, value); - /* Program the data integraty checking on the BRIF */ - WRITE_REG(REG_BRIF_DATA_CFG, BIT_BRIF_DATA_TRI_0); - - /* Set TJAT FIFO output clock signal (Reg 0x06) */ - if (te_cfg->te_clock == WAN_NORMAL_CLK) { - WRITE_REG(REG_TX_TIMING_OPT, BIT_TX_PLLREF1 | BIT_TX_TXELSTBYP); - } else { - WRITE_REG(REG_TX_TIMING_OPT, - BIT_TX_PLLREF1 | BIT_TX_PLLREF0 | BIT_TX_TXELSTBYP); - } - - /* Set long or short and enable the equalizer (Reg 0xF8) */ - WRITE_REG(REG_RLPS_CFG_STATUS, BIT_RLPS_CFG_STATUS_LONGE); - - /* Select ALOS Detection and Clearance Thresholds (Reg 0xF9) */ - /* NC: Aug 20 2003: - * Set the correct ALSO Detection/Clearance tresholds - * for T1/E1 lines, to get rid of false ALOS alarms. - * - * Original incorrect value set was 0x00, for both T1/E1 */ - if (IS_E1(&card->fe_te.te_cfg)) { - WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR, - BIT_RLPS_ALOS_DET_THR_2| - BIT_RLPS_ALOS_DET_THR_1| - BIT_RLPS_ALOS_DET_THR_0); - } else { - WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR, - BIT_RLPS_ALOS_CLR_THR_2| - BIT_RLPS_ALOS_CLR_THR_0| - BIT_RLPS_ALOS_DET_THR_2| - BIT_RLPS_ALOS_DET_THR_0); - } - - /* Select ALOS Detection period to set the ALOS alarm (Reg 0xFA) */ - WRITE_REG(REG_RLPS_ALOS_DET_PER, REG_RLPS_ALOS_DET_PER_0); - /* Select ALOS Clearance period to clear the ALOS alarm (Reg 0xFB) */ - WRITE_REG(REG_RLPS_ALOS_CLR_PER, BIT_RLPS_ALOS_CLR_PER_0); - /* Program to 0x00 to initiate a microprocessor access to RAM - ** (Reg 0xFC) */ -/* ERRATA WRITE_REG(REG_RLPS_EQ_ADDR, 0x00); */ - /* Write the value 0x80 to this register to select a write to the RAM - ** (Reg 0xFD) */ -/* ERRATA WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB); */ - /* Program this register to 0x00 to reset the pointer to the RAM - ** (Reg 0xFE) */ - WRITE_REG(REG_RLPS_EQ_STATUS, 0x00); - /* Configure the Recive line Equalizer (Reg 0xFF) */ - WRITE_REG(REG_RLPS_EQ_CFG, - BIT_RLPS_EQ_RESERVED | BIT_RLPS_EQ_FREQ_1 | BIT_RLPS_EQ_FREQ_0); - - /* Configure the TJAT FIFO (Reg 0x1B) */ - WRITE_REG(REG_TJAT_CFG, BIT_TJAT_CENT); - - /* Configure the RJAT FIFO (Reg 0x17) */ - WRITE_REG(REG_RJAT_CFG, BIT_RJAT_CENT); - /* Program Receive Options (Reg 0x02) */ - if (te_cfg->frame == WAN_FR_UNFRAMED) { - WRITE_REG(REG_RECEIVE_OPT, BIT_RECEIVE_OPT_UNF); - } else { - WRITE_REG(REG_RECEIVE_OPT, 0x00); - } - - /* Configure XLPG Analog Test Positive control (Reg 0xF4) */ - WRITE_REG(REG_XLPG_TPC, BIT_XLPG_TPC_0); - /* Configure XLPG Analog Test Negative control (Reg 0xF5) */ - WRITE_REG(REG_XLPG_TNC, BIT_XLPG_TNC_0); - - /* Program the RLPS Equalizer Voltage (Reg 0xDC) */ - if (IS_E1(&card->fe_te.te_cfg)) { - WRITE_REG(REG_EQ_VREF, 0x34); - } else { - WRITE_REG(REG_EQ_VREF, 0x2C); - } - WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00); - -/* ERRATA WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00);*/ -/* ERRAT VVV */ - WRITE_REG(0xF4, 0x01); - WRITE_REG(0xF4, 0x01); - value = READ_REG(0xF4) & 0xFE; - WRITE_REG(0xF4, value); - - WRITE_REG(0xF5, 0x01); - WRITE_REG(0xF5, 0x01); - value = READ_REG(0xF5) & 0xFE; - WRITE_REG(0xF5, value); - - WRITE_REG(0xF6, 0x01); -/* ERRATA ^^^ */ - - InitLineReceiver(card); - - ClearRPSCReg(card); - ClearTPSCReg(card); - - - DisableAllChannels(card); - if (te_cfg->active_ch == ENABLE_ALL_CHANNELS) { -#ifdef DEBUG_INIT - log(LOG_DEBUG, "%s: All channels enabled\n", card->devname); -#endif /* DEBUG_INIT */ - EnableAllChannels(card); - } else { - for (i = 1; i <= channel_range; i++) { - if (te_cfg->active_ch & (1 << (i-1))) { -#ifdef DEBUG_INIT - log(LOG_DEBUG, "%s: Enable channel %d\n", - card->devname, i); -#endif /* DEBUG_INIT */ - EnableTxChannel(card, i); - EnableRxChannel(card, i); - } - } - } - - /* Initialize and start T1/E1 timer */ - card->fe_te.te_timer_cmd = TE_SET_INTR; - bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL); - timeout_set(&card->fe_te.te_timer, sdla_te_timer, (void*)card); - sdla_te_enable_timer(card, INTR_TE1_TIMER); - - bit_set((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED); - - return 0; -} - -/* - * Enable T1/E1 interrupts. - */ -static void -sdla_te_set_intr(sdla_t* card) -{ - - /* Enable LOS interrupt */ - /* WRITE_REG(REG_CDRC_INT_EN, BIT_CDRC_INT_EN_LOSE);*/ - /* Enable ALOS interrupt */ - WRITE_REG(REG_RLPS_CFG_STATUS, - READ_REG(REG_RLPS_CFG_STATUS) | BIT_RLPS_CFG_STATUS_ALOSE); - if (IS_T1(&card->fe_te.te_cfg)) { - /* Enable RBOC interrupt */ - WRITE_REG(REG_T1_RBOC_ENABLE, - BIT_T1_RBOC_ENABLE_IDLE | - BIT_T1_RBOC_ENABLE_BOCE); - /* Enable interrupt on RED, AIS, YEL alarms */ - WRITE_REG(REG_T1_ALMI_INT_EN, - BIT_T1_ALMI_INT_EN_REDE | - BIT_T1_ALMI_INT_EN_AISE | - BIT_T1_ALMI_INT_EN_YELE); - /* Enable interrupt on OOF alarm */ - /*WRITE_REG(REG_T1_FRMR_INT_EN, BIT_T1_FRMR_INT_EN_INFRE);*/ - } else { - /* Enable interrupt on RED, AIS alarms */ - WRITE_REG(REG_E1_FRMR_M_A_INT_EN, - BIT_E1_FRMR_M_A_INT_EN_REDE | - BIT_E1_FRMR_M_A_INT_EN_AISE); - /* Enable OOF Interrupt */ - /*WRITE_REG(REG_E1_FRMR_FRM_STAT_INT_EN, - BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE);*/ - } - -#if 0 - if (card->te_signaling_config == NULL) { - /* Enable SIGE and COSS */ - /* log(LOG_INFO,"%s: Enable SIGX interrupt\n",card->devname);*/ - WRITE_REG(REG_SIGX_CFG, - READ_REG(REG_SIGX_CFG) | BIT_SIGX_SIGE); - WRITE_REG(REG_SIGX_CFG, - READ_REG(REG_SIGX_CFG) | BIT_SIGX_COSS); - } -#endif - /* Initialize T1/E1 timer */ - bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL); - /* Start T1/E1 timer */ - card->fe_te.te_timer_cmd = TE_LINKDOWN_TIMER; - sdla_te_enable_timer(card, POLLING_TE1_TIMER); - return; -} - -/* - * T1/E1 unconfig. - */ -void sdla_te_unconfig(void* card_id) -{ - sdla_t* card = (sdla_t*)card_id; - - if (!bit_test((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED)) { - return; - } - - bit_clear((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED); - bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_KILL); - - timeout_del(&card->fe_te.te_timer); - return; -} - -/* - * Set T1/E1 status. Enable OOF and LCV interrupt - * if status changed to disconnected. - */ -static void -sdla_te_set_status(sdla_t *card, unsigned long alarms) -{ - - if (IS_T1(&card->fe_te.te_cfg)) { - if (IS_T1_ALARM(alarms)) { - if (card->front_end_status != FE_DISCONNECTED) { - log(LOG_INFO, "%s: T1 disconnected!\n", - card->devname); - card->front_end_status = FE_DISCONNECTED; - } - } else { - if (card->front_end_status != FE_CONNECTED) { - log(LOG_INFO, "%s: T1 connected!\n", - card->devname); - card->front_end_status = FE_CONNECTED; - } - } - } else { - if (IS_E1_ALARM(alarms)) { - if (!bit_test((u_int8_t*)&card->fe_te.te_critical, - TE_TIMER_RUNNING)) { - card->fe_te.te_timer_cmd = TE_LINKDOWN_TIMER; - sdla_te_enable_timer(card, POLLING_TE1_TIMER); - } - if (card->front_end_status != FE_DISCONNECTED) { - log(LOG_INFO, "%s: E1 disconnected!\n", - card->devname); - card->front_end_status = FE_DISCONNECTED; - } - } else { - if (card->front_end_status != FE_CONNECTED) { - log(LOG_INFO, "%s: E1 connected!\n", - card->devname); - card->front_end_status = FE_CONNECTED; - } - } - } -#if 0 - if (card->te_report_alarms) { - card->te_report_alarms(card, alarms); - } -#endif - -#if 0 - if (card->front_end_status == FE_CONNECTED) { - WRITE_REG(REG_CDRC_INT_EN, - (READ_REG(REG_CDRC_INT_EN) | BIT_CDRC_INT_EN_LOSE)); - } else { - WRITE_REG(REG_CDRC_INT_EN, - (READ_REG(REG_CDRC_INT_EN) & ~BIT_CDRC_INT_EN_LOSE)); - } -#endif - - return; -} - -/* - * Read Alram Status for T1/E1 modes. - * - * Arguments: - * Returns: bit 0 - ALOS (E1/T1) - * bit 1 - LOS (E1/T1) - * bit 2 - ALTLOS (E1/T1) - * bit 3 - OOF (E1/T1) - * bit 4 - RED (E1/T1) - * bit 5 - AIS (E1/T1) - * bit 6 - OOSMF (E1) - * bit 7 - OOCMF (E1) - * bit 8 - OOOF (E1) - * bit 9 - RAI (E1) - * bit A - YEL (T1) - */ -unsigned long -sdla_te_alarm(void *card_id, int manual_update) -{ - sdla_t *card = (sdla_t*)card_id; - unsigned long status = 0x00; - - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - /* Check common alarm for E1 and T1 configuration - * 1. ALOS alarm - * Reg 0xFA - * Reg 0xF8 (ALOSI = 1) - */ - if (READ_REG(REG_RLPS_ALOS_DET_PER) && - (READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) { - status |= BIT_ALOS_ALARM; - } - - /* 2. LOS alarm - * Reg 0x10 - * Reg 0xF8 (ALOSI = 1) - */ - if ((READ_REG(REG_CDRC_CFG) & (BIT_CDRC_CFG_LOS0|BIT_CDRC_CFG_LOS1)) && - (READ_REG(REG_CDRC_INT_STATUS) & BIT_CDRC_INT_STATUS_LOSV)) { - status |= BIT_LOS_ALARM; - } - - /* 3. ALTLOS alarm ?????????????????? - * Reg 0x13 - */ - if (READ_REG(REG_ALTLOS_STATUS) & BIT_ALTLOS_STATUS_ALTLOS) { - status |= BIT_ALTLOS_ALARM; - } - - /* Check specific E1 and T1 alarms */ - if (IS_E1(&card->fe_te.te_cfg)) { - /* 4. OOF alarm */ - if (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOFV) { - status |= BIT_OOF_ALARM; - } - /* 5. OOSMF alarm */ - if (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOSMFV) { - status |= BIT_OOSMF_ALARM; - } - /* 6. OOCMF alarm */ - if (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOCMFV) { - status |= BIT_OOCMF_ALARM; - } - /* 7. OOOF alarm */ - if (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOOFV) { - status |= BIT_OOOF_ALARM; - } - /* 8. RAI alarm */ - if (READ_REG(REG_E1_FRMR_MAINT_STATUS) & - BIT_E1_FRMR_MAINT_STATUS_RAIV) { - status |= BIT_RAI_ALARM; - } - /* 9. RED alarm - * Reg 0x97 (REDD) - */ - if (READ_REG(REG_E1_FRMR_MAINT_STATUS) & - BIT_E1_FRMR_MAINT_STATUS_RED) { - status |= BIT_RED_ALARM; - } - /* 10. AIS alarm - * Reg 0x91 (AISC) - * Reg 0x97 (AIS) - */ - if ((READ_REG(REG_E1_FRMR_MAINT_OPT) & - BIT_E1_FRMR_MAINT_OPT_AISC) && - (READ_REG(REG_E1_FRMR_MAINT_STATUS) & - BIT_E1_FRMR_MAINT_STATUS_AIS)) { - status |= BIT_AIS_ALARM; - } - } else { - /* 4. OOF alarm - * Reg 0x4A (INFR=0 T1 mode) - */ - if (!(READ_REG(REG_T1_FRMR_INT_STATUS) & - BIT_T1_FRMR_INT_STATUS_INFR)) { - status |= BIT_OOF_ALARM; - } - /* 5. AIS alarm - * Reg 0x62 (AIS) - * Reg 0x63 (AISD) - */ - if ((READ_REG(REG_T1_ALMI_INT_STATUS) & - BIT_T1_ALMI_INT_STATUS_AIS) && - (READ_REG(REG_T1_ALMI_DET_STATUS) & - BIT_T1_ALMI_DET_STATUS_AISD)) { - status |= BIT_AIS_ALARM; - } - /* 6. RED alarm - * Reg 0x63 (REDD) - */ - if (READ_REG(REG_T1_ALMI_DET_STATUS) & - BIT_T1_ALMI_DET_STATUS_REDD) { - status |= BIT_RED_ALARM; - } - /* 7. YEL alarm - * Reg 0x62 (YEL) - * Reg 0x63 (YELD) - */ - if ((READ_REG(REG_T1_ALMI_INT_STATUS) & - BIT_T1_ALMI_INT_STATUS_YEL) && - (READ_REG(REG_T1_ALMI_DET_STATUS) & - BIT_T1_ALMI_DET_STATUS_YELD)) { - status |= BIT_YEL_ALARM; - } - } - if (manual_update) { - sdla_te_set_status(card, status); - } - return status; -} - - -/* - * Read PMC performance monitoring counters - */ -void -sdla_te_pmon(void *card_id) -{ - sdla_t *card = (sdla_t*)card_id; - pmc_pmon_t *pmon = &card->fe_te.te_pmon; - - WAN_ASSERT1(card->write_front_end_reg == NULL); - WAN_ASSERT1(card->read_front_end_reg == NULL); - /* Update PMON counters */ - WRITE_REG(REG_PMON_BIT_ERROR, 0x00); - /* Framing bit for E1/T1 */ - pmon->frm_bit_error += - READ_REG(REG_PMON_BIT_ERROR) & BITS_PMON_BIT_ERROR; - - /* OOF Error for T1 or Far End Block Error for E1 */ - pmon->oof_errors += - ((READ_REG(REG_PMON_OOF_FEB_MSB_ERROR) & - BITS_PMON_OOF_FEB_MSB_ERROR) << 8) | - READ_REG(REG_PMON_OOF_FEB_LSB_ERROR); - - /* Bit Error for T1 or CRC Error for E1 */ - pmon->bit_errors += - ((READ_REG(REG_PMON_BIT_CRC_MSB_ERROR) & - BITS_PMON_BIT_CRC_MSB_ERROR) << 8) | - READ_REG(REG_PMON_BIT_CRC_LSB_ERROR); - - /* LCV Error for E1/T1 */ - pmon->lcv += ((READ_REG(REG_PMON_LCV_MSB_COUNT) & - BITS_PMON_LCV_MSB_COUNT) << 8) | READ_REG(REG_PMON_LCV_LSB_COUNT); - return; -} - -/* - * Flush PMC performance monitoring counters - */ -void -sdla_flush_te1_pmon(void *card_id) -{ - sdla_t *card = (sdla_t*)card_id; - pmc_pmon_t *pmon = &card->fe_te.te_pmon; - - pmon->pmon1 = 0; - pmon->pmon2 = 0; - pmon->pmon3 = 0; - pmon->pmon4 = 0; - - return; -} - -static int -SetLoopBackChannel(sdla_t *card, int channel, unsigned char mode) -{ - /* Set IND bit to 1 in TPSC to enable indirect access to TPSC - ** register */ - WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); - - /* Set LOOP to 1 for an IDLE code byte (the transmit data is - * overwritten with the corresponding channel data from the receive - * line. */ - if (mode == LINELB_ACTIVATE_CODE) { - WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, - ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) & - MASK_TPSC_DATA_CTRL_BYTE) | - BIT_TPSC_DATA_CTRL_BYTE_LOOP)); - } else { - WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, - ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) & - MASK_TPSC_DATA_CTRL_BYTE) & - ~BIT_TPSC_DATA_CTRL_BYTE_LOOP)); - } - - /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */ - WRITE_REG(REG_TPSC_CFG, - ((READ_REG(REG_TPSC_CFG) & MASK_TPSC_CFG) | BIT_TPSC_PCCE)); - - return 0; -} - -/* - * Check interrupt type. - * Arguments: card - pointer to device structure. - * Returns: None. - */ -void -sdla_te_intr(void *arg) -{ - sdla_t *card = (sdla_t*)arg; - - WAN_ASSERT1(card->write_front_end_reg == NULL); - WAN_ASSERT1(card->read_front_end_reg == NULL); - sdla_te_tx_intr(card); - sdla_te_rx_intr(card); - sdla_te_set_status(card, card->fe_te.te_alarm); -} - -/* - * Read tx interrupt. - * - * Arguments: card - pointer to device structure. - * Returns: None. - */ -static void -sdla_te_tx_intr(sdla_t *card) -{ - unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00; - - intr_src1 = READ_REG(REG_INT_SRC_1); - intr_src2 = READ_REG(REG_INT_SRC_2); - intr_src3 = READ_REG(REG_INT_SRC_3); - - if (intr_src1 == 0 && intr_src2 == 0 && intr_src3 == 0) { - log(LOG_DEBUG, "%s: Unknown %s interrupt!\n", - card->devname, - IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"); - } - if (!(intr_src1 & BITS_TX_INT_SRC_1 || - intr_src2 & BITS_TX_INT_SRC_2 || - intr_src3 & BITS_TX_INT_SRC_3)) { - return; - } - -#if 0 - if (intr_src1 & BIT_INT_SRC_1_TJAT) { - } - if (intr_src1 & BIT_INT_SRC_1_APRM) { - } - if (intr_src2 & BIT_INT_SRC_2_TX_ELST) { - } - if (intr_src2 & BIT_INT_SRC_2_TDPR_1) { - } - if (intr_src2 & BIT_INT_SRC_2_TDPR_2) { - } - if (intr_src2 & BIT_INT_SRC_2_TDPR_3) { - } - if (intr_src3 & BIT_INT_SRC_3_TRAN) { - } - if (intr_src3 & BIT_INT_SRC_3_XPDE) { - } - if (intr_src3 & BIT_INT_SRC_3_BTIF) { - } -#endif - return; -} - - -/* - * Read rx interrupt. - * - * Arguments: card - pointer to device structure. - * Returns: None. - */ -static void -sdla_te_rx_intr(sdla_t *card) -{ - if (IS_T1(&card->fe_te.te_cfg)) { - sdla_t1_rx_intr(card); - } else { - sdla_e1_rx_intr(card); - } - return; -} - -/* - * Read tx interrupt. - * - * Arguments: card - pointer to device structure. - * Returns: None. - */ -static void -sdla_t1_rx_intr(sdla_t *card) -{ - unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00; - unsigned char status = 0x00; - - intr_src1 = READ_REG(REG_INT_SRC_1); - intr_src2 = READ_REG(REG_INT_SRC_2); - intr_src3 = READ_REG(REG_INT_SRC_3); - - if (!(intr_src1 & BITS_RX_INT_SRC_1 || - intr_src2 & BITS_RX_INT_SRC_2 || - intr_src3 & BITS_RX_INT_SRC_3)) { - return; - } - - /* 3. PDVD */ - if (intr_src3 & BIT_INT_SRC_3_PDVD) { - status = READ_REG(REG_PDVD_INT_EN_STATUS); - if ((status & BIT_PDVD_INT_EN_STATUS_PDVE) && - (status & BIT_PDVD_INT_EN_STATUS_PDVI)) { - if (status & BIT_PDVD_INT_EN_STATUS_PDV) { - log(LOG_INFO, "%s: T1 pulse density " - "violation detected!\n", card->devname); - } - } - if ((status & BIT_PDVD_INT_EN_STATUS_Z16DE) && - (status & BIT_PDVD_INT_EN_STATUS_Z16DI)) { - log(LOG_INFO, "%s: T1 16 consecutive zeros detected!\n", - card->devname); - } - } - - /* 6. ALMI */ - if (intr_src3 & BIT_INT_SRC_3_ALMI) { - status = READ_REG(REG_T1_ALMI_INT_STATUS); - if (status & BIT_T1_ALMI_INT_STATUS_YELI) { - if (status & BIT_T1_ALMI_INT_STATUS_YEL) { - if (!(card->fe_te.te_alarm & BIT_YEL_ALARM)) { - log(LOG_INFO, "%s: T1 YELLOW ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_YEL_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_YEL_ALARM) { - log(LOG_INFO, "%s: T1 YELLOW OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_YEL_ALARM; - } - } - } - if (status & BIT_T1_ALMI_INT_STATUS_REDI) { - if (status & BIT_T1_ALMI_INT_STATUS_RED) { - if (!(card->fe_te.te_alarm & BIT_RED_ALARM)) { - log(LOG_INFO, "%s: T1 RED ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_RED_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_RED_ALARM) { - log(LOG_INFO, "%s: T1 RED OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_RED_ALARM; - } - } - } - if (status & BIT_T1_ALMI_INT_STATUS_AISI) { - if (status & BIT_T1_ALMI_INT_STATUS_AIS) { - if (!(card->fe_te.te_alarm & BIT_AIS_ALARM)) { - log(LOG_INFO, "%s: T1 AIS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_AIS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_AIS_ALARM) { - log(LOG_INFO, "%s: T1 AIS OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_AIS_ALARM; - } - } - } - -#if 0 - if (status & - (BIT_T1_ALMI_INT_STATUS_YELI | - BIT_T1_ALMI_INT_STATUS_REDI | - BIT_T1_ALMI_INT_STATUS_AISI)) { - if (status & (BIT_T1_ALMI_INT_STATUS_YEL | - BIT_T1_ALMI_INT_STATUS_RED | - BIT_T1_ALMI_INT_STATUS_AIS)) { - - /* Update T1/E1 alarm status */ - if (!(card->fe_te.te_alarm & BIT_YEL_ALARM) && - (status & BIT_T1_ALMI_INT_STATUS_YEL)) { - log(LOG_INFO, "%s: T1 YELLOW ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_YEL_ALARM; - } - if (!(card->fe_te.te_alarm & BIT_RED_ALARM) && - (status & BIT_T1_ALMI_INT_STATUS_RED)) { - log(LOG_INFO, "%s: T1 RED ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_RED_ALARM; - } - if (!(card->fe_te.te_alarm & BIT_AIS_ALARM) && - (status & BIT_T1_ALMI_INT_STATUS_AIS)) { - log(LOG_INFO, "%s: T1 AIS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_AIS_ALARM; - } - } else { - /* Update T1/E1 alarm status */ - if ((card->fe_te.te_alarm & BIT_YEL_ALARM) && - !(status & BIT_T1_ALMI_INT_STATUS_YEL)) { - log(LOG_INFO, "%s: T1 YELLOW OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_YEL_ALARM; - } - if ((card->fe_te.te_alarm & BIT_RED_ALARM) && - !(status & BIT_T1_ALMI_INT_STATUS_RED)) { - log(LOG_INFO, "%s: T1 RED OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_RED_ALARM; - } - if ((card->fe_te.te_alarm & BIT_AIS_ALARM) && - !(status & BIT_T1_ALMI_INT_STATUS_AIS)) { - log(LOG_INFO, "%s: T1 ALMI OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_AIS_ALARM; - } - } - } -#endif - } - - /* 8. RBOC */ - if (intr_src3 & BIT_INT_SRC_3_RBOC) { - status = READ_REG(REG_T1_RBOC_CODE_STATUS); - if (status & BIT_T1_RBOC_CODE_STATUS_BOCI) { - struct timeval tv; - unsigned long time; - - microtime(&tv); - time = tv.tv_sec / 1000; - status &= MASK_T1_RBOC_CODE_STATUS; - switch (status) { - case LINELB_ACTIVATE_CODE: - case LINELB_DEACTIVATE_CODE: - if (bit_test((u_int8_t *) - &card->fe_te.te_critical, LINELB_WAITING) && - bit_test((u_int8_t *) - &card->fe_te.te_critical, - LINELB_CODE_BIT)) { - bit_clear((u_int8_t *) - &card->fe_te.te_critical, - LINELB_CODE_BIT); - break; - } - - log(LOG_DEBUG, "%s: T1 LB %s code received.\n", - card->devname, - (status == LINELB_ACTIVATE_CODE) ? - "activation" : "deactivation"); - card->fe_te.te_rx_lb_cmd = status; - card->fe_te.te_rx_lb_time = time; - break; - - case LINELB_DS1LINE_ALL: - if (bit_test( - (u_int8_t *)&card->fe_te.te_critical, - LINELB_WAITING) && - bit_test( - (u_int8_t *)&card->fe_te.te_critical, - LINELB_CHANNEL_BIT)) { - bit_clear((u_int8_t *) - &card->fe_te.te_critical, - LINELB_CHANNEL_BIT); - bit_clear((u_int8_t*) - &card->fe_te.te_critical, - LINELB_WAITING); - break; - } - if (!card->fe_te.te_rx_lb_cmd) - break; - if ((time - card->fe_te.te_rx_lb_time) < - LINELB_TE1_TIMER) { - log(LOG_INFO, "%s: T1 LB %s cancel!\n", - card->devname, - (card->fe_te.te_rx_lb_cmd == - LINELB_ACTIVATE_CODE)? - "activatation": - "deactivation"); - } else { - unsigned char reg; - if (card->fe_te.te_rx_lb_cmd == - LINELB_ACTIVATE_CODE) { - log(LOG_INFO, - "%s: T1 LB activated.\n", - card->devname); - reg=READ_REG(REG_MASTER_DIAG); - reg|=BIT_MASTER_DIAG_LINELB; - WRITE_REG(REG_MASTER_DIAG,reg); - } else { - log(LOG_INFO, - "%s: T1 LB deactivated.\n", - card->devname); - reg=READ_REG(REG_MASTER_DIAG); - reg&=~BIT_MASTER_DIAG_LINELB; - WRITE_REG(REG_MASTER_DIAG,reg); - } - } - card->fe_te.te_rx_lb_cmd = 0x00; - card->fe_te.te_rx_lb_time = 0x00; - break; - - case LINELB_DS3LINE: - break; - - case LINELB_DS1LINE_1: - case LINELB_DS1LINE_2: - case LINELB_DS1LINE_3: - case LINELB_DS1LINE_4: - case LINELB_DS1LINE_5: - case LINELB_DS1LINE_6: - case LINELB_DS1LINE_7: - case LINELB_DS1LINE_8: - case LINELB_DS1LINE_9: - case LINELB_DS1LINE_10: - case LINELB_DS1LINE_11: - case LINELB_DS1LINE_12: - case LINELB_DS1LINE_13: - case LINELB_DS1LINE_14: - case LINELB_DS1LINE_15: - case LINELB_DS1LINE_16: - case LINELB_DS1LINE_17: - case LINELB_DS1LINE_18: - case LINELB_DS1LINE_19: - case LINELB_DS1LINE_20: - case LINELB_DS1LINE_21: - case LINELB_DS1LINE_22: - case LINELB_DS1LINE_23: - case LINELB_DS1LINE_24: - case LINELB_DS1LINE_25: - case LINELB_DS1LINE_26: - case LINELB_DS1LINE_27: - case LINELB_DS1LINE_28: - if (!card->fe_te.te_rx_lb_cmd) - break; - if ((time - card->fe_te.te_rx_lb_time) < - LINELB_TE1_TIMER) { - log(LOG_DEBUG, "%s: T1 LB %s cancel!\n", - card->devname, - (card->fe_te.te_rx_lb_cmd == - LINELB_ACTIVATE_CODE) ? - "activatation": "deactivation"); - } else { - int channel; - - channel = status & LINELB_DS1LINE_MASK; - log(LOG_INFO, "%s: T1 LB %s ts %d\n", - card->devname, - (card->fe_te.te_rx_lb_cmd == - LINELB_ACTIVATE_CODE) ? - "activated" : "deactivated", - channel); - SetLoopBackChannel(card, channel, - card->fe_te.te_rx_lb_cmd); - } - card->fe_te.te_rx_lb_cmd = 0x00; - card->fe_te.te_rx_lb_time = 0x00; - break; - - default: - log(LOG_DEBUG, "%s: Unknown signal (%02x).\n", - card->devname, status); - break; - } - } - } - - /* 7. FRMR */ - if (intr_src1 & BIT_INT_SRC_1_FRMR) { - status = READ_REG(REG_T1_FRMR_INT_STATUS); - if ((READ_REG(REG_T1_FRMR_INT_EN) & BIT_T1_FRMR_INT_EN_INFRE) && - (status & BIT_T1_FRMR_INT_STATUS_INFRI)) { - if (status & BIT_T1_FRMR_INT_STATUS_INFR) { - if (!(card->fe_te.te_alarm & BIT_OOF_ALARM)) { - log(LOG_INFO, "%s: T1 OOF ON!\n", - card->devname); - card->fe_te.te_alarm |= BIT_OOF_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_OOF_ALARM) { - log(LOG_INFO, "%s: T1 OOF OFF!\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_OOF_ALARM; - } - } - } - } - - /* 1. RLPS */ - if (intr_src3 & BIT_INT_SRC_3_RLPS) { - status = READ_REG(REG_RLPS_CFG_STATUS); - if ((status & BIT_RLPS_CFG_STATUS_ALOSE) && - (status & BIT_RLPS_CFG_STATUS_ALOSI)) { - if (status & BIT_RLPS_CFG_STATUS_ALOSV) { - if (!(card->fe_te.te_alarm & BIT_ALOS_ALARM)) { - log(LOG_INFO, "%s: T1 ALOS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_ALOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_ALOS_ALARM) { - log(LOG_INFO, "%s: T1 ALOS OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_ALOS_ALARM; - } - } - } - } - - /* 2. CDRC */ - if (intr_src1 & BIT_INT_SRC_1_CDRC) { - status = READ_REG(REG_CDRC_INT_STATUS); - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) && - (status & BIT_CDRC_INT_STATUS_LOSI)) { - if (status & BIT_CDRC_INT_STATUS_LOSV) { - if (!(card->fe_te.te_alarm & BIT_LOS_ALARM)) { - log(LOG_INFO, "%s: T1 LOS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_LOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_LOS_ALARM) { - log(LOG_INFO, "%s: T1 LOS OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_LOS_ALARM; - } - } - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) && - (status & BIT_CDRC_INT_STATUS_LCVI)) { - log(LOG_INFO, "%s: T1 line code violation!\n", - card->devname); - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) && - (status & BIT_CDRC_INT_STATUS_LCSDI)) { - log(LOG_INFO, "%s: T1 line code signature detected!\n", - card->devname); - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) && - (status & BIT_CDRC_INT_STATUS_ZNDI)) { - log(LOG_INFO, "%s: T1 consecutive zeros detected!\n", - card->devname); - } - status = READ_REG(REG_ALTLOS_STATUS); - if ((status & BIT_ALTLOS_STATUS_ALTLOSI) && - (status & BIT_ALTLOS_STATUS_ALTLOSE)) { - if (status & BIT_ALTLOS_STATUS_ALTLOS) { - if (!(card->fe_te.te_alarm & - BIT_ALTLOS_ALARM)) { - log(LOG_INFO, "%s: T1 ALTLOS ON\n", - card->devname); - card->fe_te.te_alarm |= - BIT_ALTLOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_ALTLOS_ALARM) { - log(LOG_INFO, "%s: T1 ALTLOS OFF\n", - card->devname); - card->fe_te.te_alarm &= - ~BIT_ALTLOS_ALARM; - } - } - } - } - - /* 14. PMON */ - if (intr_src1 & BIT_INT_SRC_1_PMON) { - status = READ_REG(REG_PMON_INT_EN_STATUS); - if (status & BIT_PMON_INT_EN_STATUS_XFER) { - log(LOG_DEBUG, "%s: T1 Updating PMON counters...\n", - card->devname); - sdla_te_pmon(card); - } - } - - /* 9. SIGX */ - if (intr_src1 & BIT_INT_SRC_1_SIGX) { - unsigned char SIGX_chg_30_25; - unsigned char SIGX_chg_24_17; - unsigned char SIGX_chg_16_9; - unsigned char SIGX_chg_8_1; - - SIGX_chg_30_25 = READ_REG(REG_SIGX_CFG); - SIGX_chg_24_17= READ_REG(REG_SIGX_TIMESLOT_IND_STATUS); - SIGX_chg_16_9 = READ_REG(REG_SIGX_TIMESLOT_IND_ACCESS); - SIGX_chg_8_1 = READ_REG(REG_SIGX_TIMESLOT_IND_DATA_BUFFER); - - } - - /* 5. IBCD */ - card->fe_te.te_alarm &= ~(BIT_LOOPUP_CODE|BIT_LOOPDOWN_CODE); - if (intr_src3 & BIT_INT_SRC_3_IBCD) { - status = READ_REG(REG_IBCD_INT_EN_STATUS); - if (status & BIT_IBCD_INT_EN_STATUS_LBAI) { - card->fe_te.te_alarm |= BIT_LOOPUP_CODE; - } - if (status & BIT_IBCD_INT_EN_STATUS_LBDI) { - card->fe_te.te_alarm |= BIT_LOOPDOWN_CODE; - } - } -#if 0 - /* 4. RJAT */ - if (intr_src1 & BIT_INT_SRC_1_RJAT) { - } - /* 10. RX-ELST */ - if (intr_src2 & BIT_INT_SRC_2_RX_ELST) { - } - /* 11. RDLC-1 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_1) { - } - /* 12. RDLC-2 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_2) { - } - /* 13. RDLC-3 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_3) { - } -#endif - - return; -} - - -/* - * Read tx interrupt. - * - * Arguments: card - pointer to device structure. - * Returns: None. - */ -static void -sdla_e1_rx_intr(sdla_t *card) -{ - unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00; - unsigned char int_status = 0x00, status = 0x00; - - intr_src1 = READ_REG(REG_INT_SRC_1); - intr_src2 = READ_REG(REG_INT_SRC_2); - intr_src3 = READ_REG(REG_INT_SRC_3); - if (!(intr_src1 & BITS_RX_INT_SRC_1 || - intr_src2 & BITS_RX_INT_SRC_2 || - intr_src3 & BITS_RX_INT_SRC_3)) - return; - - /* 4. FRMR */ - if (intr_src1 & BIT_INT_SRC_1_FRMR) { - /* Register 0x94h E1 FRMR */ - int_status = READ_REG(REG_E1_FRMR_FRM_STAT_INT_IND); - /* Register 0x96h E1 FRMR Status */ - status = READ_REG(REG_E1_FRMR_FR_STATUS); - if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) & - BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE) && - (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI)) { - if (status & BIT_E1_FRMR_FR_STATUS_OOFV) { - if (!(card->fe_te.te_alarm & BIT_OOF_ALARM)) { - log(LOG_INFO, "%s: E1 OOF ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_OOF_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_OOF_ALARM) { - log(LOG_INFO, "%s: E1 OOF OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_OOF_ALARM; - } - } - } - - if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) & - BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE) && - (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI)) { - if (status & BIT_E1_FRMR_FR_STATUS_OOSMFV) { - log(LOG_INFO, "%s: E1 OOSMF ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_OOSMF_ALARM; - } else { - log(LOG_INFO, "%s: E1 OOSMF OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_OOSMF_ALARM; - } - } - - if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) & - BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE) && - (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI)) { - if (status & BIT_E1_FRMR_FR_STATUS_OOCMFV) { - log(LOG_INFO, "%s: E1 OOCMF ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_OOCMF_ALARM; - } else { - log(LOG_INFO, "%s: E1 OOCMF OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_OOCMF_ALARM; - } - } - - /* Register 0x9Fh E1 FRMR */ - status = READ_REG(REG_E1_FRMR_P_A_INT_STAT); - if ((READ_REG(REG_E1_FRMR_P_A_INT_EN) & - BIT_E1_FRMR_P_A_INT_EN_OOOFE) && - (status & BIT_E1_FRMR_P_A_INT_STAT_OOOFI)) { - if (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOOFV) { - log(LOG_INFO, "%s: E1 OOOF ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_OOOF_ALARM; - } else { - log(LOG_INFO, "%s: E1 OOOF OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_OOOF_ALARM; - } - } - - /* Register 0x95h E1 FRMR */ - int_status = READ_REG(REG_E1_FRMR_M_A_INT_IND); - if (int_status & (BIT_E1_FRMR_M_A_INT_IND_REDI | - BIT_E1_FRMR_M_A_INT_IND_AISI)) { - status = READ_REG(REG_E1_FRMR_MAINT_STATUS); - if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) & - BIT_E1_FRMR_M_A_INT_EN_REDE) && - (int_status & BIT_E1_FRMR_M_A_INT_IND_REDI)) { - if (status & BIT_E1_FRMR_MAINT_STATUS_RED) { - log(LOG_INFO, "%s: E1 RED ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_RED_ALARM; - } else { - log(LOG_INFO, "%s: E1 RED OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_RED_ALARM; - } - } - if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) & - BIT_E1_FRMR_M_A_INT_EN_AISE) && - (int_status & BIT_E1_FRMR_M_A_INT_IND_AISI)) { - if (status & BIT_E1_FRMR_MAINT_STATUS_AIS) { - log(LOG_INFO, "%s: E1 AIS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_AIS_ALARM; - } else { - log(LOG_INFO, "%s: E1 AIS OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_AIS_ALARM; - } - } - if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) & - BIT_E1_FRMR_M_A_INT_EN_RAIE) && - (int_status & BIT_E1_FRMR_M_A_INT_IND_RAII)) { - if (status & BIT_E1_FRMR_MAINT_STATUS_RAIV) { - log(LOG_INFO, "%s: E1 RAI ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_RAI_ALARM; - } else { - log(LOG_INFO, "%s: E1 RAI OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_RAI_ALARM; - } - } - } - } - - /* 1. RLPS */ - if (intr_src3 & BIT_INT_SRC_3_RLPS) { - status = READ_REG(REG_RLPS_CFG_STATUS); - if ((status & BIT_RLPS_CFG_STATUS_ALOSE) && - (status & BIT_RLPS_CFG_STATUS_ALOSI)) { - if (status & BIT_RLPS_CFG_STATUS_ALOSV) { - if (!(card->fe_te.te_alarm & BIT_ALOS_ALARM)) { - log(LOG_INFO, "%s: E1 ALOS ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_ALOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_ALOS_ALARM) { - log(LOG_INFO, "%s: E1 ALOS is OFF\n", - card->devname); - card->fe_te.te_alarm &= - ~BIT_ALOS_ALARM; - } - } - } - } - - /* 2. CDRC */ - if (intr_src1 & BIT_INT_SRC_1_CDRC) { - status = READ_REG(REG_CDRC_INT_STATUS); - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) && - (status & BIT_CDRC_INT_STATUS_LOSI)) { - if (status & BIT_CDRC_INT_STATUS_LOSV) { - if (!(card->fe_te.te_alarm & BIT_LOS_ALARM)) { - log(LOG_INFO, "%s: E1 LOS is ON\n", - card->devname); - card->fe_te.te_alarm |= BIT_LOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_LOS_ALARM) { - log(LOG_INFO, "%s: E1 LOS is OFF\n", - card->devname); - card->fe_te.te_alarm &= ~BIT_LOS_ALARM; - } - } - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) && - (status & BIT_CDRC_INT_STATUS_LCVI)) { - log(LOG_INFO, "%s: E1 line code violation!\n", - card->devname); - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) && - (status & BIT_CDRC_INT_STATUS_LCSDI)) { - log(LOG_INFO, "%s: E1 line code signature detected!\n", - card->devname); - } - if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) && - (status & BIT_CDRC_INT_STATUS_ZNDI)) { - log(LOG_INFO, "%s: E1 consecutive zeros detected!\n", - card->devname); - } - status = READ_REG(REG_ALTLOS_STATUS); - if ((status & BIT_ALTLOS_STATUS_ALTLOSI) && - (status & BIT_ALTLOS_STATUS_ALTLOSE)) { - if (status & BIT_ALTLOS_STATUS_ALTLOS) { - if (!(card->fe_te.te_alarm & - BIT_ALTLOS_ALARM)) { - log(LOG_INFO, "%s: E1 ALTLOS is ON\n", - card->devname); - card->fe_te.te_alarm |= - BIT_ALTLOS_ALARM; - } - } else { - if (card->fe_te.te_alarm & BIT_ALTLOS_ALARM) { - log(LOG_INFO, "%s: E1 ALTLOS is OFF\n", - card->devname); - card->fe_te.te_alarm &= - ~BIT_ALTLOS_ALARM; - } - } - } - } - /* 11. PMON */ - if (intr_src1 & BIT_INT_SRC_1_PMON) { - status = READ_REG(REG_PMON_INT_EN_STATUS); - if (status & BIT_PMON_INT_EN_STATUS_XFER) { - sdla_te_pmon(card); - } - } -#if 0 - /* 3. RJAT */ - if (intr_src1 & BIT_INT_SRC_1_RJAT) { - } - /* 5. SIGX */ - if (intr_src1 & BIT_INT_SRC_1_SIGX) { - } - /* 6. RX-ELST */ - if (intr_src2 & BIT_INT_SRC_2_RX_ELST) { - } - /* 7. PRGD */ - if (intr_src1 & BIT_INT_SRC_1_PRGD) { - } - /* 8. RDLC-1 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_1) { - } - /* 9. RDLC-2 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_2) { - } - /* 10. RDLC-3 */ - if (intr_src2 & BIT_INT_SRC_2_RDLC_3) { - } -#endif - if (!(READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) { - card->fe_te.te_alarm &= ~BIT_ALOS_ALARM; - } - return; -} - -/* - * Set T1/E1 loopback modes. - */ -int -sdla_set_te1_lb_modes(void *arg, unsigned char type, unsigned char mode) -{ - sdla_t *card = (sdla_t*)arg; - int err = 1; - - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - switch (type) { - case WAN_TE1_LINELB_MODE: - err = sdla_te_linelb(card, mode); - break; - case WAN_TE1_PAYLB_MODE: - err = sdla_te_paylb(card, mode); - break; - case WAN_TE1_DDLB_MODE: - err = sdla_te_ddlb(card, mode); - break; - case WAN_TE1_TX_LB_MODE: - err = sdla_te_lb(card, mode); - break; - } - - return err; -} - -/* - * Activate/Deactivate Line Loopback mode. - */ -static int -sdla_te_linelb(sdla_t *card, unsigned char mode) -{ - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - if (mode == WAN_TE1_ACTIVATE_LB) { - log(LOG_INFO, "%s: %s Line Loopback mode activated.\n", - card->devname, - (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_LINELB); - } else { - log(LOG_INFO, "%s: %s Line Loopback mode deactivated.\n", - card->devname, - (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_LINELB); - } - return 0; -} - -/* - * Activate/Deactivate Payload loopback mode. - */ -static int -sdla_te_paylb(sdla_t *card, unsigned char mode) -{ - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - if (mode == WAN_TE1_ACTIVATE_LB) { - log(LOG_INFO, "%s: %s Payload Loopback mode activated.\n", - card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_PAYLB); - } else { - log(LOG_INFO, "%s: %s Payload Loopback mode deactivated.\n", - card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_PAYLB); - } - return 0; -} - -/* - * Description: Activate/Deactivate Diagnostic Digital loopback mode. - */ -static int -sdla_te_ddlb(sdla_t *card, unsigned char mode) -{ - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - if (mode == WAN_TE1_ACTIVATE_LB) { - log(LOG_INFO, "%s: %s Diagnostic Dig. LB mode activated.\n", - card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_DDLB); - } else { - log(LOG_INFO, "%s: %s Diagnostic Dig. LB mode deactivated.\n", - card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1")); - WRITE_REG(REG_MASTER_DIAG, - READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_DDLB); - } - return 0; -} - -void -sdla_te_timer(void *card_id) -{ - sdla_t *card = (sdla_t*)card_id; - - if (bit_test((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL)) { - bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_RUNNING); - return; - } - /*WAN_ASSERT1(card->te_enable_timer == NULL); */ - /* Enable hardware interrupt for TE1 */ - if (card->te_enable_timer) { - card->te_enable_timer(card); - } else { - sdla_te_polling(card); - } - - return; -} - -/* - * Enable software timer interrupt in delay ms. - */ -static void -sdla_te_enable_timer(sdla_t *card, unsigned long delay) -{ - - WAN_ASSERT1(card == NULL); - if (bit_test((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_KILL)) { - bit_clear((u_int8_t*)&card->fe_te.te_critical, - TE_TIMER_RUNNING); - return; - } - bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_RUNNING); - - timeout_add_msec(&card->fe_te.te_timer, delay); - return; -} - -/* - * Description: Process T1/E1 polling function. - */ -void -sdla_te_polling(void *card_id) -{ - sdla_t* card = (sdla_t*)card_id; - - WAN_ASSERT1(card->write_front_end_reg == NULL); - WAN_ASSERT1(card->read_front_end_reg == NULL); - bit_clear((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_RUNNING); - switch (card->fe_te.te_timer_cmd) { - case TE_LINELB_TIMER: - if (IS_T1(&card->fe_te.te_cfg)) { - /* Sending T1 activation/deactivation LB signal */ - if (card->fe_te.te_tx_lb_cnt > 10) { - WRITE_REG(REG_T1_XBOC_CODE, - (card->fe_te.te_tx_lb_cmd == - WAN_TE1_ACTIVATE_LB) ? - LINELB_ACTIVATE_CODE : - LINELB_DEACTIVATE_CODE); - } else { - WRITE_REG(REG_T1_XBOC_CODE, - LINELB_DS1LINE_ALL); - } - if (--card->fe_te.te_tx_lb_cnt) { - sdla_te_enable_timer(card, LINELB_TE1_TIMER); - } else { - log(LOG_DEBUG, "%s: TX T1 LB %s signal.\n", - card->devname, - (card->fe_te.te_tx_lb_cmd == - WAN_TE1_ACTIVATE_LB) ? - "activation" : "deactivation"); - card->fe_te.te_tx_lb_cmd = 0x00; - bit_clear((u_int8_t*)&card->fe_te.te_critical, - TE_TIMER_RUNNING); - } - } - break; - - case TE_SET_INTR: - sdla_te_set_intr(card); - break; - - case TE_LINKDOWN_TIMER: - if ((READ_REG(REG_RLPS_ALOS_DET_PER) && - (READ_REG(REG_RLPS_CFG_STATUS) & - BIT_RLPS_CFG_STATUS_ALOSV)) || - (IS_E1(&card->fe_te.te_cfg) && - (READ_REG(REG_E1_FRMR_FR_STATUS) & - BIT_E1_FRMR_FR_STATUS_OOFV)) || - (IS_T1(&card->fe_te.te_cfg) && - (READ_REG(REG_T1_FRMR_INT_STATUS) & - ~BIT_T1_FRMR_INT_STATUS_INFR))) { - sdla_te_enable_timer(card, POLLING_TE1_TIMER); - } else { - /* All other interrupt reports status changed - * through interrupts, we don't need to read - * these values here */ - sdla_te_set_status(card, card->fe_te.te_alarm); - if (card->front_end_status == FE_CONNECTED) { - card->fe_te.te_timer_cmd = TE_LINKUP_TIMER; - sdla_te_enable_timer(card, POLLING_TE1_TIMER); - } - } - break; - - case TE_LINKUP_TIMER: - /* ALEX: - * Do not update protocol front end state from - * TE_LINKDOWN_TIMER because it cause to stay - * more longer in interrupt handler (critical for XILINX - * code) */ - if (card->te_link_state) { - card->te_link_state(card); - } - break; - } - return; -} - -/* - * Description: Transmit loopback signal to remote side. - */ -static int -sdla_te_lb(sdla_t *card, unsigned char mode) -{ - WAN_ASSERT(card->write_front_end_reg == NULL); - WAN_ASSERT(card->read_front_end_reg == NULL); - - if (!IS_T1(&card->fe_te.te_cfg)) { - return 1; - } - if (card->front_end_status != FE_CONNECTED) { - return 1; - } - if (bit_test((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_RUNNING)) - return 1; - if (bit_test((u_int8_t*)&card->fe_te.te_critical,LINELB_WAITING)) { - log(LOG_DEBUG, "%s: Waiting for loopback signal!\n", - card->devname); - } - log(LOG_DEBUG, "%s: Sending %s loopback %s signal...\n", - card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"), - (mode == WAN_TE1_ACTIVATE_LB) ? "activation" : "deactivation"); - card->fe_te.te_tx_lb_cmd = mode; - card->fe_te.te_tx_lb_cnt = LINELB_CODE_CNT + LINELB_CHANNEL_CNT; - card->fe_te.te_timer_cmd = TE_LINELB_TIMER; - bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_WAITING); - bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CODE_BIT); - bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CHANNEL_BIT); - sdla_te_enable_timer(card, LINELB_TE1_TIMER); - - return 0; -} - -int -sdla_te_udp(void *card_id, void *cmd, unsigned char *data) -{ - sdla_t *card = (sdla_t*)card_id; - wan_cmd_t *udp_cmd = (wan_cmd_t*)cmd; - int err = 0; - - switch (udp_cmd->wan_cmd_command) { - case WAN_GET_MEDIA_TYPE: - data[0] = - IS_T1(&card->fe_te.te_cfg) ? WAN_MEDIA_T1 : - IS_E1(&card->fe_te.te_cfg) ? WAN_MEDIA_E1 : - WAN_MEDIA_NONE; - udp_cmd->wan_cmd_return_code = WAN_CMD_OK; - udp_cmd->wan_cmd_data_len = sizeof(unsigned char); - break; - - case WAN_FE_SET_LB_MODE: - /* Activate/Deactivate Line Loopback modes */ - err = sdla_set_te1_lb_modes(card, data[0], data[1]); - udp_cmd->wan_cmd_return_code = - (!err) ? WAN_CMD_OK : WAN_UDP_FAILED_CMD; - udp_cmd->wan_cmd_data_len = 0x00; - break; - - case WAN_FE_GET_STAT: - /* TE1_56K Read T1/E1/56K alarms */ - *(unsigned long *)&data[0] = sdla_te_alarm(card, 0); - /* TE1 Update T1/E1 perfomance counters */ - sdla_te_pmon(card); - memcpy(&data[sizeof(unsigned long)], - &card->fe_te.te_pmon, sizeof(pmc_pmon_t)); - udp_cmd->wan_cmd_return_code = WAN_CMD_OK; - udp_cmd->wan_cmd_data_len = - sizeof(unsigned long) + sizeof(pmc_pmon_t); - - break; - - case WAN_FE_FLUSH_PMON: - /* TE1 Flush T1/E1 pmon counters */ - sdla_flush_te1_pmon(card); - udp_cmd->wan_cmd_return_code = WAN_CMD_OK; - break; - - case WAN_FE_GET_CFG: - /* Read T1/E1 configuration */ - memcpy(&data[0], &card->fe_te.te_cfg, sizeof(sdla_te_cfg_t)); - udp_cmd->wan_cmd_return_code = WAN_CMD_OK; - udp_cmd->wan_cmd_data_len = sizeof(sdla_te_cfg_t); - break; - - default: - udp_cmd->wan_cmd_return_code = WAN_UDP_INVALID_CMD; - udp_cmd->wan_cmd_data_len = 0; - break; - } - return 0; -} - - -void -aft_green_led_ctrl(void *card_id, int mode) -{ - sdla_t *card = (sdla_t*)card_id; - unsigned char led; - - if (!card->read_front_end_reg || - !card->write_front_end_reg) { - return; - } - - led= READ_REG(REG_GLOBAL_CFG); - - if (mode == AFT_LED_ON) { - led&=~(BIT_GLOBAL_PIO); - } else if (mode == AFT_LED_OFF) { - led|=BIT_GLOBAL_PIO; - } else { - if (led&BIT_GLOBAL_PIO) { - led&=~(BIT_GLOBAL_PIO); - } else { - led|=BIT_GLOBAL_PIO; - } - } - - WRITE_REG(REG_GLOBAL_CFG,led); -} diff --git a/sys/dev/pci/if_san_te1.h b/sys/dev/pci/if_san_te1.h deleted file mode 100644 index 1bc988fbc9d..00000000000 --- a/sys/dev/pci/if_san_te1.h +++ /dev/null @@ -1,968 +0,0 @@ -/* $OpenBSD: if_san_te1.h,v 1.5 2005/04/01 21:42:36 canacar Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IF_SANTE1_H -# define __IF_SANTE1_H - -#ifdef SDLA_TE1 -# define EXTERN -#else -# define EXTERN extern -#endif - -# include - - -#define REG_GLOBAL_CFG 0x00 -#define BIT_GLOBAL_PIO_OE 0x80 -#define BIT_GLOBAL_PIO 0x40 -#define BIT_GLOBAL_TRKEN 0x04 -#define BIT_GLOBAL_E1 0x01 - -#define REG_RLPS_ALOS_DET_PER_0 0x01 - -#define REG_RECEIVE_OPT 0x02 -#define BIT_RECEIVE_OPT_UNF 0x40 - -#define REG_TX_TIMING_OPT 0x06 -#define BIT_TX_PLLREF1 0x08 -#define BIT_TX_PLLREF0 0x04 -#define BIT_TX_TXELSTBYP 0x01 - -#define REG_MASTER_DIAG 0x0A -#define BIT_MASTER_DIAG_PAYLB 0x20 -#define BIT_MASTER_DIAG_LINELB 0x10 -#define BIT_MASTER_DIAG_DDLB 0x04 - -#define REG_RESET 0x0E -#define BIT_RESET 0x01 - -#define REG_PRGD_CTRL 0x0F -#define BIT_PRGD_CTRL_HDLC3 0x80 -#define BIT_PRGD_CTRL_HDLC2 0x40 -#define BIT_PRGD_CTRL_HDLC1 0x20 -#define BIT_PRGD_CTRL_Nx56k_GEN 0x10 -#define BIT_PRGD_CTRL_Nx56k_DET 0x08 -#define BIT_PRGD_CTRL_RXPATGEN 0x04 -#define BIT_PRGD_CTRL_UNF_GEN 0x02 -#define BIT_PRGD_CTRL_UNF_DET 0x01 - -#define REG_CDRC_CFG 0x10 -#define BIT_CDRC_CFG_AMI 0x80 -#define BIT_CDRC_CFG_LOS1 0x40 -#define BIT_CDRC_CFG_LOS0 0x20 - -#define REG_CDRC_INT_STATUS 0x12 -#define BIT_CDRC_INT_STATUS_LCVI 0x80 -#define BIT_CDRC_INT_STATUS_LOSI 0x40 -#define BIT_CDRC_INT_STATUS_LCSDI 0x20 -#define BIT_CDRC_INT_STATUS_ZNDI 0x10 -#define BIT_CDRC_INT_STATUS_LOSV 0x01 - -#define REG_ALTLOS_STATUS 0x13 -#define BIT_ALTLOS_STATUS_ALTLOSE 0x80 -#define BIT_ALTLOS_STATUS_ALTLOSI 0x40 -#define BIT_ALTLOS_STATUS_ALTLOS 0x01 - -#define REG_RJAT_CFG 0x17 -#define BIT_RJAT_CENT 0x10 - -#define REG_TJAT_CFG 0x1B -#define BIT_TJAT_CENT 0x10 - -#define REG_RX_ELST_CFG 0x1C -#define MASK_RX_ELST_CFG 0x03 -#define BIT_RX_ELST_IR 0x02 -#define BIT_RX_ELST_OR 0x01 - -#define REG_TX_ELST_CFG 0x20 -#define MASK_TX_ELST_CFG 0x03 -#define BIT_TX_ELST_IR 0x02 -#define BIT_TX_ELST_OR 0x01 - -#define REG_BRIF_CFG 0x30 -#define BIT_BRIF_NXDS0_1 0x80 -#define BIT_BRIF_NXDS0_0 0x40 -#define BIT_BRIF_CMODE 0x20 -#define BIT_BRIF_RATE0 0x01 - -#define REG_BRIF_FR_PULSE_CFG 0x31 -#define BIT_BRIF_FPMODE 0x20 -#define BIT_BRIF_ROHM 0x08 - -#define REG_BRIF_DATA_CFG 0x32 -#define BIT_BRIF_DATA_TRI_0 0x01 - -#define REG_BTIF_CFG 0x40 -#define BIT_BTIF_NXDS0_1 0x80 -#define BIT_BTIF_NXDS0_0 0x40 -#define BIT_BTIF_CMODE 0x20 -#define BIT_BTIF_DE 0x10 -#define BIT_BTIF_FE 0x08 -#define BIT_BTIF_RATE0 0x01 - -#define REG_BTIF_FR_PULSE_CFG 0x41 -#define BIT_BTIF_FPMODE 0x01 - -#define REG_BTIF_CFG_STATUS 0x42 -#define BIT_BTIF_CFG_STATUS_TPTYP 0x80 -#define BIT_BTIF_CFG_STATUS_TPTYE 0x40 -#define BIT_BTIF_CFG_STATUS_TDI 0x20 -#define BIT_BTIF_CFG_STATUS_TSIGI 0x10 -#define BIT_BTIF_CFG_STATUS_PTY_EXTD 0x08 - -#define REG_BTIF_BIT_OFF 0x44 -#define BIT_BTIF_BIT_OFF_BOFF_EN 0x08 -#define BIT_BTIF_BIT_OFF_BOFF_2 0x04 -#define BIT_BTIF_BIT_OFF_BOFF_1 0x02 -#define BIT_BTIF_BIT_OFF_BOFF_0 0x01 - -#define REG_T1_FRMR_CFG 0x48 -#define BIT_T1_FRMR_ESF 0x20 -#define BIT_T1_FRMR_ESFFA 0x10 -#define BIT_T1_FRMR_FMS1 0x08 -#define BIT_T1_FRMR_FMS0 0x04 - -#define REG_SIGX_CFG 0x50 -#define BIT_SIGX_ESF 0x04 -#define BIT_SIGX_IND 0x02 -#define BIT_SIGX_PCCE 0x01 -#define BIT_SIGX_SIGE 0x20 -#define BIT_SIGX_COSS 0x40 -#define MASK_SIGX_COSS_30_25 0x3F - -#define REG_SIGX_TIMESLOT_IND_STATUS 0x51 -#define BIT_SIGX_BUSY 0x80 -#define REG_SIGX_TIMESLOT_IND_ACCESS 0x52 -#define BIT_SIGX_TS_IND_ACCESS_READ 0x80 -#define REG_SIGX_TIMESLOT_IND_DATA_BUFFER 0x53 -#define REG_SIGX_SIGDATA 0x20 -#define BIT_SIGX_SIGDATA_A 0x08 -#define BIT_SIGX_SIGDATA_B 0x04 -#define BIT_SIGX_SIGDATA_C 0x02 -#define BIT_SIGX_SIGDATA_D 0x01 - -#define REG_SIGX_CHANCFG 0x40 -#define BIT_SIGX_CHANCFG_RINV1 0x08 -#define BIT_SIGX_CHANCFG_RINV0 0x04 -#define BIT_SIGX_CHANCFG_RFIX 0x04 -#define BIT_SIGX_CHANCFG_RPOL 0x02 -#define BIT_SIGX_CHANCFG_RDEBE 0x01 - -#define REG_T1_XBAS_CFG 0x54 -#define BIT_T1_XBAS_ZCS0 0x01 -#define BIT_T1_XBAS_ZCS1 0x02 -#define BIT_T1_XBAS_B8ZS 0x20 -#define BIT_T1_XBAS_ESF 0x10 - -#define REG_T1_XBAS_ALARM_TX 0x55 -#define BIT_T1_XBAS_ALARM_TX_XYEL 0x02 -#define BIT_T1_XBAS_ALARM_TX_XAIS 0x01 - -/* PMON Framing Bit Error Count */ -#define REG_PMON_BIT_ERROR 0x59 -#define BITS_PMON_BIT_ERROR 0x7F -/* PMON OOF/COFA/Far End Block Error Count LSB */ -#define REG_PMON_OOF_FEB_LSB_ERROR 0x5A -/* PMON OOF/COFA/Far End Block Error Count MSB */ -#define REG_PMON_OOF_FEB_MSB_ERROR 0x5B -#define BITS_PMON_OOF_FEB_MSB_ERROR 0x03 -/* PMON Bit Error/CRC Error Count LSB */ -#define REG_PMON_BIT_CRC_LSB_ERROR 0x5C -/* PMON Bit Error/CRC Error Count MSB */ -#define REG_PMON_BIT_CRC_MSB_ERROR 0x5D -#define BITS_PMON_BIT_CRC_MSB_ERROR 0x03 -/* PMON LCV Count LSB */ -#define REG_PMON_LCV_LSB_COUNT 0x5E -/* PMON LCV Count MSB */ -#define REG_PMON_LCV_MSB_COUNT 0x5F -#define BITS_PMON_LCV_MSB_COUNT 0x1F - -#define REG_T1_ALMI_CFG 0x60 -#define BIT_T1_ALMI_CFG_ESF 0x10 -#define BIT_T1_ALMI_CFG_FMS1 0x08 -#define BIT_T1_ALMI_CFG_FMS0 0x04 - -#define REG_T1_ALMI_DET_STATUS 0x63 -#define BIT_T1_ALMI_DET_STATUS_REDD 0x04 -#define BIT_T1_ALMI_DET_STATUS_YELD 0x02 -#define BIT_T1_ALMI_DET_STATUS_AISD 0x01 - -/* T1 XBOC Code */ -#define REG_T1_XBOC_CODE 0x67 -#define MASK_T1_XBOC_CODE 0x3F - -/* T1 RBOC Enable */ -#define REG_T1_RBOC_ENABLE 0x6A -#define BIT_T1_RBOC_ENABLE_IDLE 0x04 -#define BIT_T1_RBOC_ENABLE_AVC 0x02 -#define BIT_T1_RBOC_ENABLE_BOCE 0x01 - -/* T1 RBOC Code Status */ -#define REG_T1_RBOC_CODE_STATUS 0x6B -#define BIT_T1_RBOC_CODE_STATUS_IDLEI 0x80 -#define BIT_T1_RBOC_CODE_STATUS_BOCI 0x40 -#define MASK_T1_RBOC_CODE_STATUS 0x3F - -/* TPSC Indirect Register Access */ -#define REG_TPSC_CFG 0x6C -#define MASK_TPSC_CFG 0x03 -#define BIT_TPSC_IND 0x02 -#define BIT_TPSC_PCCE 0x01 -#define REG_TPSC_MICRO_ACCESS_STATUS 0x6D -#define BIT_TPSC_BUSY 0x80 -#define REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL 0x6E -#define REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER 0x6F -#define REG_TPSC_DATA_CTRL_BYTE 0x20 -#define MASK_TPSC_DATA_CTRL_BYTE 0xFC -#define BIT_TPSC_DATA_CTRL_BYTE_INVERT 0x80 -#define BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0 0x40 -#define BIT_TPSC_DATA_CTRL_BYTE_SIGNINV 0x10 -#define BIT_TPSC_DATA_CTRL_BYTE_LOOP 0x04 -#define BIT_TPSC_DATA_CTRL_BYTE_ZCS0 0x02 -#define BIT_TPSC_DATA_CTRL_BYTE_ZCS1 0x01 -#define REG_TPSC_IDLE_CODE_BYTE 0x40 -#define REG_TPSC_SIGNALING_BYTE 0x60 -#define REG_TPSC_E1_CTRL_BYTE 0x60 -#define BIT_TPSC_E1_CTRL_BYTE_SUBS 0x80 -#define BIT_TPSC_E1_CTRL_BYTE_DS0 0x40 -#define BIT_TPSC_E1_CTRL_BYTE_DS1 0x20 -#define BIT_TPSC_E1_CTRL_BYTE_A 0x08 -#define BIT_TPSC_E1_CTRL_BYTE_B 0x04 -#define BIT_TPSC_E1_CTRL_BYTE_C 0x02 -#define BIT_TPSC_E1_CTRL_BYTE_D 0x01 -#define BIT_TPSC_SIGNALING_BYTE_SIGC_0 0x80 -#define BIT_TPSC_SIGNALING_BYTE_SIGC_1 0x40 -#define BIT_TPSC_SIGNALING_BYTE_DS1 0x20 -#define BIT_TPSC_SIGNALING_BYTE_A 0x08 -#define BIT_TPSC_SIGNALING_BYTE_B 0x04 -#define BIT_TPSC_SIGNALING_BYTE_C 0x02 -#define BIT_TPSC_SIGNALING_BYTE_D 0x01 - -/* RPSC Indirect Register Access */ -#define REG_RPSC_CFG 0x70 -#define MASK_RPSC_CFG 0x03 -#define BIT_RPSC_IND 0x02 -#define BIT_RPSC_PCCE 0x01 -#define REG_RPSC_MICRO_ACCESS_STATUS 0x71 -#define BIT_RPSC_BUSY 0x80 -#define REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL 0x72 -#define REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER 0x73 -#define REG_RPSC_DATA_CTRL_BYTE 0x20 -#define MASK_RPSC_DATA_CTRL_BYTE 0xFC -#define BIT_RPSC_DATA_CTRL_BYTE_DTRKC 0x40 -#define BIT_RPSC_DATA_CTRL_BYTE_SIGNINV 0x04 -#define REG_RPSC_DATA_COND_BYTE 0x40 -#define REG_RPSC_SIGNALING_BYTE 0x60 -#define BIT_RPSC_SIGNALING_BYTE_A 0x08 -#define BIT_RPSC_SIGNALING_BYTE_B 0x04 -#define BIT_RPSC_SIGNALING_BYTE_C 0x02 -#define BIT_RPSC_SIGNALING_BYTE_D 0x01 - -#define REG_E1_TRAN_CFG 0x80 -#define BIT_E1_TRAN_AMI 0x80 -#define BIT_E1_TRAN_GENCRC 0x10 -#define BIT_E1_TRAN_FDIS 0x08 -#define BIT_E1_TRAN_FEBEDIS 0x04 -#define BIT_E1_TRAN_INDIS 0x02 -#define BIT_E1_TRAN_XDIS 0x01 - -#define REG_E1_FRMR_CFG 0x90 -#define BIT_E1_FRMR_CRCEN 0x80 -#define BIT_E1_FRMR_CASDIS 0x40 -#define BIT_E1_FRMR_REFCRCEN 0x02 - -/* E1 FRMR Maintenance Mode Options */ -#define REG_E1_FRMR_MAINT_OPT 0x91 -#define BIT_E1_FRMR_MAINT_OPT_AISC 0x02 - -/* E1 FRMR framing status */ -#define REG_E1_FRMR_FR_STATUS 0x96 -#define BIT_E1_FRMR_FR_STATUS_C2NCIWV 0x80 -#define BIT_E1_FRMR_FR_STATUS_OOFV 0x40 -#define BIT_E1_FRMR_FR_STATUS_OOSMFV 0x20 -#define BIT_E1_FRMR_FR_STATUS_OOCMFV 0x10 -#define BIT_E1_FRMR_FR_STATUS_OOOFV 0x08 -#define BIT_E1_FRMR_FR_STATUS_RAICCRCV 0x04 -#define BIT_E1_FRMR_FR_STATUS_CFEBEV 0x02 -#define BIT_E1_FRMR_FR_STATUS_V52LINKV 0x01 - -/* E1 FRMR Maintenance/Alram Status */ -#define REG_E1_FRMR_MAINT_STATUS 0x97 -#define BIT_E1_FRMR_MAINT_STATUS_RAIV 0x80 -#define BIT_E1_FRMR_MAINT_STATUS_RED 0x08 -#define BIT_E1_FRMR_MAINT_STATUS_AIS 0x04 - - /* TDPR Configuration */ -#define REG_TDPR_CFG 0xA8 -#define BIT_TDPR_CFG_EN 0x01 - -/* TDPR Transmit Data */ -#define REG_TDPR_TX_DATA 0xAD - -/* RDLC Configuration */ -#define REG_RDLC_CFG 0xC0 -#define BIT_RDLC_CFG_EN 0x01 - -/* RDLC Interrupt Control */ -#define REG_RDLC_INT_CTRL 0xC1 -#define BIT_RDLC_INT_CTRL_INTE 0x80 - -/* RDLC Status */ -#define REG_RDLC_STATUS 0xC2 -#define BIT_RDLC_STATUS_PKIN 0x10 -#define BIT_RDLC_STATUS_INTR 0x01 - -/* RDLC Data */ -#define REG_RDLC_DATA 0xC3 - -#define REG_CSU_CFG 0xD6 -#define MASK_CSU_CFG 0xC7 -#define BIT_CSU_MODE2 0x04 -#define BIT_CSU_MODE1 0x02 -#define BIT_CSU_MODE0 0x01 - -/* RLPS Equalization Indirect Data (MSB) */ -#define REG_RLPS_IND_DATA_1 0xD8 -/* RLPS Equalization Indirect Data */ -#define REG_RLPS_IND_DATA_2 0xD9 -/* RLPS Equalization Indirect Data */ -#define REG_RLPS_IND_DATA_3 0xDA -/* RLPS Equalization Indirect Data (LSB) */ -#define REG_RLPS_IND_DATA_4 0xDB - -#define REG_EQ_VREF 0xDC - -#define REG_RLPS_FUSE_CTRL_STAT 0xDD - -#define REG_XLPG_LINE_CFG 0xF0 -#define REG_PRGD_INT_STATUS_EN 0xE1 -#define BIT_PRGD_INT_STATUS_EN_SYNCE 0x80 -#define BIT_PRGD_INT_STATUS_EN_BEE 0x40 -#define BIT_PRGD_INT_STATUS_EN_XFERE 0x20 -#define BIT_PRGD_INT_STATUS_EN_SYNCV 0x10 -#define BIT_PRGD_INT_STATUS_EN_SYNCI 0x08 -#define BIT_PRGD_INT_STATUS_EN_BEI 0x04 -#define BIT_PRGD_INT_STATUS_EN_XFERI 0x02 -#define BIT_PRGD_INT_STATUS_EN_OVR 0x01 - -#define REG_XLPG_WAVEFORM_ADDR 0xF2 - -#define REG_XLPG_WAVEFORM_DATA 0xF3 - -#define REG_XLPG_TPC 0xF4 -#define BIT_XLPG_TPC_0 0x01 - -#define REG_XLPG_TNC 0xF5 -#define BIT_XLPG_TNC_0 0x01 - -#define REG_RLPS_CFG_STATUS 0xF8 -#define BIT_RLPS_CFG_STATUS_ALOSI 0x80 -#define BIT_RLPS_CFG_STATUS_ALOSV 0x40 -#define BIT_RLPS_CFG_STATUS_ALOSE 0x20 -#define BIT_RLPS_CFG_STATUS_LONGE 0x01 - -#define REG_RLPS_ALOS_DET_CLR_THR 0xF9 -#define BIT_RLPS_ALOS_CLR_THR_2 0x40 -#define BIT_RLPS_ALOS_CLR_THR_1 0x20 -#define BIT_RLPS_ALOS_CLR_THR_0 0x10 -#define BIT_RLPS_ALOS_DET_THR_2 0x04 -#define BIT_RLPS_ALOS_DET_THR_1 0x02 -#define BIT_RLPS_ALOS_DET_THR_0 0x01 - -#define REG_RLPS_ALOS_DET_PER 0xFA - -#define REG_RLPS_ALOS_CLR_PER 0xFB -#define BIT_RLPS_ALOS_CLR_PER_0 0x01 - -/* RLPS Equalization Indirect Address */ -#define REG_RLPS_EQ_ADDR 0xFC - -/* RLPS Equalization Read/Write Select */ -#define REG_RLPS_EQ_RWB 0xFD -#define BIT_RLPS_EQ_RWB 0x80 - -#define REG_RLPS_EQ_STATUS 0xFE - -#define REG_RLPS_EQ_CFG 0xFF -#define MASK_RLPS_EQ_CFG 0xC7 -#define BIT_RLPS_EQ_RESERVED 0x08 -#define BIT_RLPS_EQ_FREQ_1 0x02 -#define BIT_RLPS_EQ_FREQ_0 0x01 - -/********************************************/ -/************ Interrupt Register ************/ -/********************************************/ -#define REG_INT_SRC_1 0x07 -#define BITS_TX_INT_SRC_1 0x0C -#define BITS_RX_INT_SRC_1 0xF3 -#define BIT_INT_SRC_1_PMON 0x80 -#define BIT_INT_SRC_1_PRGD 0x40 -#define BIT_INT_SRC_1_FRMR 0x20 -#define BIT_INT_SRC_1_SIGX 0x10 -#define BIT_INT_SRC_1_APRM 0x08 -#define BIT_INT_SRC_1_TJAT 0x04 -#define BIT_INT_SRC_1_RJAT 0x02 -#define BIT_INT_SRC_1_CDRC 0x01 - -#define REG_INT_SRC_2 0x08 -#define BITS_TX_INT_SRC_2 0x0F -#define BITS_RX_INT_SRC_2 0xF0 -#define BIT_INT_SRC_2_RX_ELST 0x80 -#define BIT_INT_SRC_2_RDLC_3 0x40 -#define BIT_INT_SRC_2_RDLC_2 0x20 -#define BIT_INT_SRC_2_RDLC_1 0x10 -#define BIT_INT_SRC_2_TX_ELST 0x08 -#define BIT_INT_SRC_2_TDPR_3 0x04 -#define BIT_INT_SRC_2_TDPR_2 0x02 -#define BIT_INT_SRC_2_TDPR_1 0x01 - -#define REG_INT_SRC_3 0x09 -#define BITS_TX_INT_SRC_3 0x15 -#define BITS_RX_INT_SRC_3 0xEA -#define BIT_INT_SRC_3_IBCD 0x80 -#define BIT_INT_SRC_3_PDVD 0x40 -#define BIT_INT_SRC_3_RBOC 0x20 -#define BIT_INT_SRC_3_XPDE 0x10 -#define BIT_INT_SRC_3_ALMI 0x08 -#define BIT_INT_SRC_3_TRAN 0x04 -#define BIT_INT_SRC_3_RLPS 0x02 -#define BIT_INT_SRC_3_BTIF 0x01 - -#define REG_CDRC_INT_EN 0x11 -#define BIT_CDRC_INT_EN_LCVE 0x80 -#define BIT_CDRC_INT_EN_LOSE 0x40 -#define BIT_CDRC_INT_EN_LCSDE 0x20 -#define BIT_CDRC_INT_EN_ZNDE 0x10 - -#define REG_CDRC_INT_STATUS 0x12 -#define BIT_CDRC_INT_STATUS_LCVI 0x80 -#define BIT_CDRC_INT_STATUS_LOSI 0x40 -#define BIT_CDRC_INT_STATUS_LCSDI 0x20 -#define BIT_CDRC_INT_STATUS_ZNDI 0x10 -#define BIT_CDRC_INT_STATUS_LOSV 0x01 - -#define REG_RJAT_INT_STATUS 0x14 -#define BIT_RJAT_INT_STATUS_OVRI 0x02 -#define BIT_RJAT_INT_STATUS_UNDI 0x01 - -#define REG_TJAT_INT_STATUS 0x18 -#define BIT_TJAT_INT_STATUS_OVRI 0x02 -#define BIT_TJAT_INT_STATUS_UNDI 0x01 - -#define REG_RX_ELST_INT_EN_STATUS 0x1D -#define BIT_RX_ELST_INT_EN_STATUS_SLIPE 0x04 -#define BIT_RX_ELST_INT_EN_STATUS_SLIPD 0x02 -#define BIT_RX_ELST_INT_EN_STATUS_SLIPI 0x01 - -#define REG_TX_ELST_INT_EN_STATUS 0x21 -#define BIT_TX_ELST_INT_EN_STATUS_SLIPE 0x04 -#define BIT_TX_ELST_INT_EN_STATUS_SLIPD 0x02 -#define BIT_TX_ELST_INT_EN_STATUS_SLIPI 0x01 - -#define REG_T1_FRMR_INT_EN 0x49 -#define BIT_T1_FRMR_INT_EN_COFAE 0x20 -#define BIT_T1_FRMR_INT_EN_FERE 0x10 -#define BIT_T1_FRMR_INT_EN_BEEE 0x08 -#define BIT_T1_FRMR_INT_EN_SFEE 0x04 -#define BIT_T1_FRMR_INT_EN_MFPE 0x02 -#define BIT_T1_FRMR_INT_EN_INFRE 0x01 - -#define REG_T1_FRMR_INT_STATUS 0x4A -#define BIT_T1_FRMR_INT_STATUS_COFAI 0x80 -#define BIT_T1_FRMR_INT_STATUS_FERI 0x40 -#define BIT_T1_FRMR_INT_STATUS_BEEI 0x20 -#define BIT_T1_FRMR_INT_STATUS_SFEI 0x10 -#define BIT_T1_FRMR_INT_STATUS_MFPI 0x08 -#define BIT_T1_FRMR_INT_STATUS_INFRI 0x04 -#define BIT_T1_FRMR_INT_STATUS_MFP 0x02 -#define BIT_T1_FRMR_INT_STATUS_INFR 0x01 - -#define REG_IBCD_CFG 0x4C -#define BIT_IBCD_CFG_DSEL1 0x08 -#define BIT_IBCD_CFG_DSEL0 0x04 -#define BIT_IBCD_CFG_ASEL1 0x02 -#define BIT_IBCD_CFG_ASEL0 0x01 - -#define REG_IBCD_INT_EN_STATUS 0x4D -#define BIT_IBCD_INT_EN_STATUS_LBACP 0x80 -#define BIT_IBCD_INT_EN_STATUS_LBDCP 0x40 -#define BIT_IBCD_INT_EN_STATUS_LBAE 0x20 -#define BIT_IBCD_INT_EN_STATUS_LBDE 0x10 -#define BIT_IBCD_INT_EN_STATUS_LBAI 0x08 -#define BIT_IBCD_INT_EN_STATUS_LBDI 0x04 -#define BIT_IBCD_INT_EN_STATUS_LBA 0x02 -#define BIT_IBCD_INT_EN_STATUS_LBD 0x01 - -#define REG_IBCD_ACTIVATE_CODE 0x4E -#define BIT_IBCD_ACTIVATE_CODE_ACT7 0x80 -#define BIT_IBCD_ACTIVATE_CODE_ACT6 0x40 -#define BIT_IBCD_ACTIVATE_CODE_ACT5 0x20 -#define BIT_IBCD_ACTIVATE_CODE_ACT4 0x10 -#define BIT_IBCD_ACTIVATE_CODE_ACT3 0x08 -#define BIT_IBCD_ACTIVATE_CODE_ACT2 0x04 -#define BIT_IBCD_ACTIVATE_CODE_ACT1 0x02 -#define BIT_IBCD_ACTIVATE_CODE_ACT0 0x01 - -#define REG_IBCD_DEACTIVATE_CODE 0x4F -#define BIT_IBCD_DEACTIVATE_CODE_DACT7 0x80 -#define BIT_IBCD_DEACTIVATE_CODE_DACT6 0x40 -#define BIT_IBCD_DEACTIVATE_CODE_DACT5 0x20 -#define BIT_IBCD_DEACTIVATE_CODE_DACT4 0x10 -#define BIT_IBCD_DEACTIVATE_CODE_DACT3 0x08 -#define BIT_IBCD_DEACTIVATE_CODE_DACT2 0x04 -#define BIT_IBCD_DEACTIVATE_CODE_DACT1 0x02 -#define BIT_IBCD_DEACTIVATE_CODE_DACT0 0x01 - -#define REG_PMON_INT_EN_STATUS 0x58 -#define BIT_PMON_INT_EN_STATUS_INTE 0x04 -#define BIT_PMON_INT_EN_STATUS_XFER 0x02 -#define BIT_PMON_INT_EN_STATUS_OVR 0x01 - -#define REG_T1_ALMI_INT_EN 0x61 -#define BIT_T1_ALMI_INT_EN_FASTD 0x10 -#define BIT_T1_ALMI_INT_EN_ACCEL 0x08 -#define BIT_T1_ALMI_INT_EN_YELE 0x04 -#define BIT_T1_ALMI_INT_EN_REDE 0x02 -#define BIT_T1_ALMI_INT_EN_AISE 0x01 - -#define REG_T1_ALMI_INT_STATUS 0x62 -#define BIT_T1_ALMI_INT_STATUS_YELI 0x20 -#define BIT_T1_ALMI_INT_STATUS_REDI 0x10 -#define BIT_T1_ALMI_INT_STATUS_AISI 0x08 -#define BIT_T1_ALMI_INT_STATUS_YEL 0x04 -#define BIT_T1_ALMI_INT_STATUS_RED 0x02 -#define BIT_T1_ALMI_INT_STATUS_AIS 0x01 - -#define REG_PDVD_INT_EN_STATUS 0x65 -#define BIT_PDVD_INT_EN_STATUS_PDV 0x10 -#define BIT_PDVD_INT_EN_STATUS_Z16DI 0x08 -#define BIT_PDVD_INT_EN_STATUS_PDVI 0x04 -#define BIT_PDVD_INT_EN_STATUS_Z16DE 0x02 -#define BIT_PDVD_INT_EN_STATUS_PDVE 0x01 - -#define REG_XPDE_INT_EN_STATUS 0x69 -#define BIT_XPDE_INT_EN_STATUS_STUFE 0x80 -#define BIT_XPDE_INT_EN_STATUS_STUFF 0x40 -#define BIT_XPDE_INT_EN_STATUS_STUFI 0x20 -#define BIT_XPDE_INT_EN_STATUS_PDV 0x10 -#define BIT_XPDE_INT_EN_STATUS_Z16DI 0x08 -#define BIT_XPDE_INT_EN_STATUS_PDVI 0x04 -#define BIT_XPDE_INT_EN_STATUS_Z16DE 0x02 -#define BIT_XPDE_INT_EN_STATUS_PDVE 0x01 - -#define REG_T1_APRM_INT_STATUS 0x7A -#define BIT_T1_APRM_INT_STATUS_INTR 0x01 - -#define REG_E1_TRAN_INT_EN 0x84 -#define BIT_E1_TRAN_INT_EN_SIGMFE 0x10 -#define BIT_E1_TRAN_INT_EN_NFASE 0x08 -#define BIT_E1_TRAN_INT_EN_MFE 0x04 -#define BIT_E1_TRAN_INT_EN_SMFE 0x02 -#define BIT_E1_TRAN_INT_EN_FRME 0x01 - -#define REG_E1_TRAN_INT_STATUS 0x85 -#define BIT_E1_TRAN_INT_STATUS_SIGMFI 0x10 -#define BIT_E1_TRAN_INT_STATUS_NFASI 0x08 -#define BIT_E1_TRAN_INT_STATUS_MFI 0x04 -#define BIT_E1_TRAN_INT_STATUS_SMFI 0x02 -#define BIT_E1_TRAN_INT_STATUS_FRMI 0x01 - -#define REG_E1_FRMR_FRM_STAT_INT_EN 0x92 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_C2NCIWE 0x80 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE 0x40 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE 0x20 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE 0x10 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_COFAE 0x08 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_FERE 0x04 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_SMFERE 0x02 -#define BIT_E1_FRMR_FRM_STAT_INT_EN_CMFERE 0x01 - -#define REG_E1_FRMR_M_A_INT_EN 0x93 -#define BIT_E1_FRMR_M_A_INT_EN_RAIE 0x80 -#define BIT_E1_FRMR_M_A_INT_EN_RMAIE 0x40 -#define BIT_E1_FRMR_M_A_INT_EN_AISDE 0x20 -#define BIT_E1_FRMR_M_A_INT_EN_REDE 0x08 -#define BIT_E1_FRMR_M_A_INT_EN_AISE 0x04 -#define BIT_E1_FRMR_M_A_INT_EN_FEBEE 0x02 -#define BIT_E1_FRMR_M_A_INT_EN_CRCEE 0x01 - -/* E1 FRMR Framing status Interrupt Indication */ -#define REG_E1_FRMR_FRM_STAT_INT_IND 0x94 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_C2NCIWI 0x80 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI 0x40 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI 0x20 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI 0x10 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_COFAI 0x08 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_FERI 0x04 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_SMFERI 0x02 -#define BIT_E1_FRMR_FRM_STAT_INT_IND_CMFERI 0x01 - -#define REG_E1_FRMR_M_A_INT_IND 0x95 -#define BIT_E1_FRMR_M_A_INT_IND_RAII 0x80 -#define BIT_E1_FRMR_M_A_INT_IND_FMAII 0x40 -#define BIT_E1_FRMR_M_A_INT_IND_AISDI 0x20 -#define BIT_E1_FRMR_M_A_INT_IND_REDI 0x08 -#define BIT_E1_FRMR_M_A_INT_IND_AISI 0x04 -#define BIT_E1_FRMR_M_A_INT_IND_FEBEI 0x02 -#define BIT_E1_FRMR_M_A_INT_IND_CRCEI 0x01 - -#define REG_E1_FRMR_P_A_INT_EN 0x9E -#define BIT_E1_FRMR_P_A_INT_EN_OOOFE 0x80 -#define BIT_E1_FRMR_P_A_INT_EN_RAICCRCE 0x40 -#define BIT_E1_FRMR_P_A_INT_EN_CFEBEE 0x20 -#define BIT_E1_FRMR_P_A_INT_EN_V52LINKE 0x10 -#define BIT_E1_FRMR_P_A_INT_EN_IFPE 0x08 -#define BIT_E1_FRMR_P_A_INT_EN_ICSMFPE 0x04 -#define BIT_E1_FRMR_P_A_INT_EN_ICMFPE 0x02 -#define BIT_E1_FRMR_P_A_INT_EN_ISMFPE 0x01 - -#define REG_E1_FRMR_P_A_INT_STAT 0x9F -#define BIT_E1_FRMR_P_A_INT_STAT_OOOFI 0x80 -#define BIT_E1_FRMR_P_A_INT_STAT_RAICCRCI 0x40 -#define BIT_E1_FRMR_P_A_INT_STAT_CFEBEI 0x20 -#define BIT_E1_FRMR_P_A_INT_STAT_V52LINKI 0x10 -#define BIT_E1_FRMR_P_A_INT_STAT_IFPI 0x08 -#define BIT_E1_FRMR_P_A_INT_STAT_ICSMFPI 0x04 -#define BIT_E1_FRMR_P_A_INT_STAT_ICMFPI 0x02 -#define BIT_E1_FRMR_P_A_INT_STAT_ISMFPI 0x01 - - -/*The line code */ -#define WAN_LC_AMI 0x01 -#define WAN_LC_B8ZS 0x02 -#define WAN_LC_HDB3 0x03 - -/* Framing mode (T1/E1)/Unframed */ -#define WAN_FR_ESF 0x01 -#define WAN_FR_D4 0x02 -#define WAN_FR_ESF_JAPAN 0x03 -#define WAN_FR_CRC4 0x04 -#define WAN_FR_NCRC4 0x05 -#define WAN_FR_UNFRAMED 0x06 - -/* For T1 only */ -#define WAN_T1_LBO_0_DB 0x01 -#define WAN_T1_LBO_75_DB 0x02 -#define WAN_T1_LBO_15_DB 0x03 -#define WAN_T1_LBO_225_DB 0x04 -#define WAN_T1_0_110 0x05 -#define WAN_T1_110_220 0x06 -#define WAN_T1_220_330 0x07 -#define WAN_T1_330_440 0x08 -#define WAN_T1_440_550 0x09 -#define WAN_T1_550_660 0x0A - -/* For E1 only */ -#define WAN_E1_120 0x0B -#define WAN_E1_75 0x0C - -/* Clocking Master/Normal */ -#define WAN_NORMAL_CLK 0x01 -#define WAN_MASTER_CLK 0x02 - -#define NUM_OF_T1_CHANNELS 24 -#define NUM_OF_E1_TIMESLOTS 31 -#define NUM_OF_E1_CHANNELS 32 -#define ENABLE_ALL_CHANNELS 0xFFFFFFFF - -#define E1_FRAMING_TIMESLOT 0 -#define E1_SIGNALING_TIMESLOT 16 - -/* Alram bit mask */ -#define BIT_ALOS_ALARM 0x0001 -#define BIT_LOS_ALARM 0x0002 -#define BIT_ALTLOS_ALARM 0x0004 -#define BIT_OOF_ALARM 0x0008 -#define BIT_RED_ALARM 0x0010 -#define BIT_AIS_ALARM 0x0020 -#define BIT_OOSMF_ALARM 0x0040 -#define BIT_OOCMF_ALARM 0x0080 -#define BIT_OOOF_ALARM 0x0100 -#define BIT_RAI_ALARM 0x0200 -#define BIT_YEL_ALARM 0x0400 -#define BIT_LOOPUP_CODE 0x2000 -#define BIT_LOOPDOWN_CODE 0x4000 -#define BIT_TE1_ALARM 0x8000 /* for Windows only */ - -/* Performamce monitor counter defines */ -#define frm_bit_error pmon1 /* E1/T1 */ -#define oof_errors pmon2 /* T1 only */ -#define far_end_blk_errors pmon2 /* E1 only */ -#define bit_errors pmon3 /* T1 only */ -#define crc_errors pmon3 /* E1 only */ -#define lcv pmon4 /* E1/T1 */ - -/* Line loopback modes */ -#define WAN_TE1_LINELB_MODE 0x01 -#define WAN_TE1_PAYLB_MODE 0x02 -#define WAN_TE1_DDLB_MODE 0x03 -#define WAN_TE1_TX_LB_MODE 0x04 - -/* Line loopback activate/deactive modes */ -#define WAN_TE1_ACTIVATE_LB 0x01 -#define WAN_TE1_DEACTIVATE_LB 0x02 - -/* Loopback commands (T1.107-1995 p.44) */ -#define LINELB_TE1_TIMER 40 /* 40ms */ -#define LINELB_CODE_CNT 10 /* no. of repetitions for lb_code */ -#define LINELB_CHANNEL_CNT 10 /* no. of repetitions for channel */ -#define LINELB_ACTIVATE_CODE 0x07 -#define LINELB_DEACTIVATE_CODE 0x1C -#define LINELB_DS3LINE 0x1B -#define LINELB_DS1LINE_1 0x21 -#define LINELB_DS1LINE_2 0x22 -#define LINELB_DS1LINE_3 0x23 -#define LINELB_DS1LINE_4 0x24 -#define LINELB_DS1LINE_5 0x25 -#define LINELB_DS1LINE_6 0x26 -#define LINELB_DS1LINE_7 0x27 -#define LINELB_DS1LINE_8 0x28 -#define LINELB_DS1LINE_9 0x29 -#define LINELB_DS1LINE_10 0x2A -#define LINELB_DS1LINE_11 0x2B -#define LINELB_DS1LINE_12 0x2C -#define LINELB_DS1LINE_13 0x2D -#define LINELB_DS1LINE_14 0x2E -#define LINELB_DS1LINE_15 0x2F -#define LINELB_DS1LINE_16 0x30 -#define LINELB_DS1LINE_17 0x31 -#define LINELB_DS1LINE_18 0x32 -#define LINELB_DS1LINE_19 0x33 -#define LINELB_DS1LINE_20 0x34 -#define LINELB_DS1LINE_21 0x35 -#define LINELB_DS1LINE_22 0x36 -#define LINELB_DS1LINE_23 0x37 -#define LINELB_DS1LINE_24 0x38 -#define LINELB_DS1LINE_25 0x39 -#define LINELB_DS1LINE_26 0x3A -#define LINELB_DS1LINE_27 0x3B -#define LINELB_DS1LINE_28 0x3C -#define LINELB_DS1LINE_ALL 0x13 -#define LINELB_DS1LINE_MASK 0x1F - -/* Interrupt polling delay */ -#define POLLING_TE1_TIMER 1000 /* 1 sec */ - -/* TE1 critical flag */ -#define TE_TIMER_RUNNING 0x01 -#define TE_TIMER_KILL 0x02 -#define LINELB_WAITING 0x03 -#define LINELB_CODE_BIT 0x04 -#define LINELB_CHANNEL_BIT 0x05 -#define TE_CONFIGURED 0x06 - -#if 0 -#define TE_TIMER_RUNNING 0x01 -#define TE_TIMER_KILL 0x02 -#define LINELB_WAITING 0x04 -#define LINELB_CODE_BIT 0x08 -#define LINELB_CHANNEL_BIT 0x10 -#endif - -/* TE1 timer flags */ -#define TE_LINELB_TIMER 0x01 -#define TE_LINKDOWN_TIMER 0x02 -#define TE_SET_INTR 0x03 -#define TE_ABCD_UPDATE 0x04 -#define TE_LINKUP_TIMER 0x05 - -/* TE1 T1/E1 interrupt setting delay */ -#define INTR_TE1_TIMER 150 /* 50 ms */ - -#define IS_T1(te_cfg) ((te_cfg)->media == WAN_MEDIA_T1) -#define IS_E1(te_cfg) ((te_cfg)->media == WAN_MEDIA_E1) - -#define IS_TE1(te_cfg) (IS_T1(te_cfg) || IS_E1(te_cfg)) - -#define IS_TE1_UNFRAMED(card) ((card)->te_cfg.frame == WAN_FR_UNFRAMED) - -#define GET_TE_CHANNEL_RANGE(card) \ - (IS_T1(&card->te_cfg) ? NUM_OF_T1_CHANNELS : \ - IS_E1(&card->te_cfg) ? NUM_OF_E1_CHANNELS :0) - -#define ALOS_ALARM(val) (val & BIT_ALOS_ALARM) ? "ON" : "OFF" -#define LOS_ALARM(val) (val & BIT_LOS_ALARM) ? "ON" : "OFF" -#define ALTLOS_ALARM(val) (val & BIT_ALTLOS_ALARM) ? "ON" : "OFF" -#define OOF_ALARM(val) (val & BIT_OOF_ALARM) ? "ON" : "OFF" -#define RED_ALARM(val) (val & BIT_RED_ALARM) ? "ON" : "OFF" -#define AIS_ALARM(val) (val & BIT_AIS_ALARM) ? "ON" : "OFF" -#define OOSMF_ALARM(val) (val & BIT_OOSMF_ALARM) ? "ON" : "OFF" -#define OOCMF_ALARM(val) (val & BIT_OOCMF_ALARM) ? "ON" : "OFF" -#define OOOF_ALARM(val) (val & BIT_OOOF_ALARM) ? "ON" : "OFF" -#define RAI_ALARM(val) (val & BIT_RAI_ALARM) ? "ON" : "OFF" -#define YEL_ALARM(val) (val & BIT_YEL_ALARM) ? "ON" : "OFF" - -#define MEDIA_DECODE(val) (val == WAN_MEDIA_T1) ? "T1" : \ - (val == WAN_MEDIA_E1) ? "E1" : "Unknown" - -#define LCODE_DECODE(val) (val == WAN_LC_AMI) ? "AMI" : \ - (val == WAN_LC_B8ZS) ? "B8ZS" : \ - (val == WAN_LC_HDB3) ? "HDB3" : "Unknown" - -#define FRAME_DECODE(val) (val == WAN_FR_ESF) ? "ESF" : \ - (val == WAN_FR_D4) ? "D4" : \ - (val == WAN_FR_CRC4) ? "CRC4" : \ - (val == WAN_FR_NCRC4) ? "non-CRC4" : \ - (val == WAN_FR_UNFRAMED) ? \ - "Unframed" : "Unknown" - -#define TECLK_DECODE(val) (val == WAN_NORMAL_CLK) ? "Normal" : \ - (val == WAN_MASTER_CLK) ? "Master" : \ - "Unknown" - -#define LBO_DECODE(val) \ - (val == WAN_T1_LBO_0_DB) ? "0db" : \ - (val == WAN_T1_LBO_75_DB) ? "7.5db" : \ - (val == WAN_T1_LBO_15_DB) ? "15dB" : \ - (val == WAN_T1_LBO_225_DB) ? "22.5dB" : \ - (val == WAN_T1_0_110) ? "0-110ft" : \ - (val == WAN_T1_110_220) ? "110-220ft" : \ - (val == WAN_T1_220_330) ? "220-330ft" : \ - (val == WAN_T1_330_440) ? "330-440ft" : \ - (val == WAN_T1_440_550) ? "440-550ft" : \ - (val == WAN_T1_550_660) ? "550-660ft" : "Unknown" - - -/* - * T1/E1 configuration structures. - */ -typedef struct sdla_te_cfg { - unsigned char media; - unsigned char lcode; - unsigned char frame; - unsigned char lbo; - unsigned char te_clock; - unsigned long active_ch; - unsigned char high_impedance_mode; -} sdla_te_cfg_t; - -/* Performamce monitor counters */ -typedef struct pmc_pmon { - unsigned long pmon1; - unsigned long pmon2; - unsigned long pmon3; - unsigned long pmon4; -} pmc_pmon_t; - -#ifdef _KERNEL - -/* - * Constants for the SET_T1_E1_SIGNALING_CFG/READ_T1_E1_SIGNALING_CFG commands - */ - -/* the structure for setting the signaling permission */ -#pragma pack(1) -typedef struct { - unsigned char time_slot[32]; -} te_signaling_perm_t; -#pragma pack() - -/* settings for the signaling permission structure */ -#define TE_SIG_DISABLED 0x00 /* signaling is disabled */ -#define TE_RX_SIG_ENABLED 0x01 /* receive signaling is enabled */ -#define TE_TX_SIG_ENABLED 0x02 /* transmit signaling is enabled */ -#define TE_SET_TX_SIG_BITS 0x80 /* a flag indicating that outgoing - signaling bits should be set */ - -/* the structure used for the - * SET_T1_E1_SIGNALING_CFG/READ_T1_E1_SIGNALING_CFG command - */ -#pragma pack(1) -typedef struct { - /* signaling permission structure */ - te_signaling_perm_t sig_perm; - /* loop signaling processing counter */ - unsigned char sig_processing_counter; - /* pointer to the signaling permission structure */ - unsigned long ptr_te_sig_perm_struct; - /* pointer to the receive signaling structure */ - unsigned long ptr_te_Rx_sig_struct; - /* pointer to the transmit signaling structure */ - unsigned long ptr_te_Tx_sig_struct; -} te_signaling_cfg_t; -#pragma pack() - -/* the structure used for reading and setting the signaling bits */ -#pragma pack(1) -typedef struct { - unsigned char time_slot[32]; -} te_signaling_status_t; -#pragma pack() - -typedef struct { - unsigned char SIGX_chg_30_25; - unsigned char SIGX_chg_24_17; - unsigned char SIGX_chg_16_9; - unsigned char SIGX_chg_8_1; - - unsigned long ptr_te_sig_perm_off; - unsigned long ptr_te_Rx_sig_off; - unsigned long ptr_te_Tx_sig_off; - - sdla_te_cfg_t te_cfg; /* TE1 hw configuration */ - unsigned long te_alarm; /* TE1 alarm */ - pmc_pmon_t te_pmon; /* TE PMON counters */ - unsigned char te_rx_lb_cmd; /* Received LB cmd */ - unsigned long te_rx_lb_time; /* Time when LB cmd received */ - - unsigned char te_tx_lb_cmd; /* Received LB cmd */ - unsigned long te_tx_lb_cnt; /* Time when LB cmd received */ - unsigned char te_critical; /* T1/E1 critical flag */ - struct timeout te_timer; /* Timer */ - unsigned char te_timer_cmd; -} sdla_te_softc_t; - - -EXTERN int sdla_te_defcfg(void *); -EXTERN int sdla_te_setcfg(struct ifnet *, struct ifmedia *); -EXTERN void sdla_te_settimeslot(void *, unsigned long); -EXTERN unsigned long sdla_te_gettimeslot(void *); -EXTERN short sdla_te_config(void *); -EXTERN void sdla_te_unconfig(void *); -EXTERN unsigned long sdla_te_alarm(void *, int); -EXTERN void sdla_te_alarm_print(void *); -EXTERN void sdla_te_pmon(void *); -EXTERN void sdla_flush_te1_pmon(void *); -EXTERN void sdla_te_intr(void *); -EXTERN int sdla_set_te1_lb_modes(void *, unsigned char, unsigned char); -EXTERN void sdla_te_polling(void *); -EXTERN void sdla_te_timer(void *); -EXTERN int sdla_te_udp(void *, void *, unsigned char *); -EXTERN void aft_green_led_ctrl(void *, int); -#endif /* _KERNEL */ - -#undef EXTERN - -#endif /* __IF_SANTE1_H */ diff --git a/sys/dev/pci/if_san_xilinx.c b/sys/dev/pci/if_san_xilinx.c deleted file mode 100644 index b30ab5131e8..00000000000 --- a/sys/dev/pci/if_san_xilinx.c +++ /dev/null @@ -1,3562 +0,0 @@ -/* $OpenBSD: if_san_xilinx.c,v 1.33 2015/03/14 03:38:48 jsg Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Nenad Corbic and - * Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - - -/* Private critical flags */ -enum { - POLL_CRIT = PRIV_CRIT, - TX_BUSY, - RX_BUSY, - TASK_POLL, - CARD_DOWN -}; - -enum { - LINK_DOWN, - DEVICE_DOWN -}; - -#define MAX_IP_ERRORS 10 - -#define PORT(x) (x == 0 ? "PRIMARY" : "SECONDARY" ) -#define MAX_TX_BUF 10 -#define MAX_RX_BUF 10 - -#undef DEB_XILINX - -#if 1 -# define TRUE_FIFO_SIZE 1 -#else -# undef TRUE_FIFO_SIZE -# define HARD_FIFO_CODE 0x01 -#endif - -static int aft_rx_copyback = MHLEN; - - -struct xilinx_rx_buffer { - SIMPLEQ_ENTRY(xilinx_rx_buffer) entry; - struct mbuf *mbuf; - bus_dmamap_t dma_map; - wp_rx_element_t rx_el; -}; - -SIMPLEQ_HEAD(xilinx_rx_head, xilinx_rx_buffer); - -/* - * This structure is placed in the private data area of the device structure. - * The card structure used to occupy the private area but now the following - * structure will incorporate the card structure along with Protocol specific - * data - */ -typedef struct { - wanpipe_common_t common; - - struct ifqueue wp_tx_pending_list; - struct ifqueue wp_tx_complete_list; - struct xilinx_rx_head wp_rx_free_list; - struct xilinx_rx_head wp_rx_complete_list; - struct xilinx_rx_buffer *wp_rx_buffers; - struct xilinx_rx_buffer *wp_rx_buffer_last; - struct xilinx_rx_buffer *rx_dma_buf; - - bus_dma_tag_t dmatag; - bus_dmamap_t tx_dmamap; - struct mbuf *tx_dma_mbuf; - u_int8_t tx_dma_cnt; - - unsigned long time_slot_map; - unsigned char num_of_time_slots; - long logic_ch_num; - - unsigned char dma_status; - unsigned char ignore_modem; - struct ifqueue udp_queue; - - unsigned long router_start_time; - - unsigned long tick_counter; /* For 5s timeout counter */ - unsigned long router_up_time; - - unsigned char mc; /* Mulitcast support on/off */ - unsigned char udp_pkt_src; /* udp packet processing */ - unsigned short timer_int_enabled; - - unsigned char interface_down; - - u_int8_t gateway; - u_int8_t true_if_encoding; - - char if_name[IFNAMSIZ+1]; - - u_int8_t idle_flag; - u_int16_t max_idle_size; - u_int8_t idle_start; - - u_int8_t pkt_error; - u_int8_t rx_fifo_err_cnt; - - int first_time_slot; - - unsigned long tx_dma_addr; - unsigned int tx_dma_len; - unsigned char rx_dma; - unsigned char pci_retry; - - unsigned char fifo_size_code; - unsigned char fifo_base_addr; - unsigned char fifo_size; - - int dma_mtu; - - void *prot_ch; - wan_trace_t trace_info; -}xilinx_softc_t; -#define WAN_IFP_TO_SOFTC(ifp) (xilinx_softc_t *)((ifp)->if_softc) - -/* Route Status options */ -#define NO_ROUTE 0x00 -#define ADD_ROUTE 0x01 -#define ROUTE_ADDED 0x02 -#define REMOVE_ROUTE 0x03 - -#define WP_WAIT 0 -#define WP_NO_WAIT 1 - -/* variable for keeping track of enabling/disabling FT1 monitor status */ -/* static int rCount; */ - -extern void disable_irq(unsigned int); -extern void enable_irq(unsigned int); - -extern int ticks; - -/**SECTOIN************************************************** - * - * Function Prototypes - * - ***********************************************************/ - -/* WAN link driver entry points. These are called by the WAN router module. */ -static int wan_xilinx_release(sdla_t*, struct ifnet *); - -/* Network device interface */ -static int wan_xilinx_up(struct ifnet *); -static int wan_xilinx_down(struct ifnet *); -static int wan_xilinx_ioctl(struct ifnet *, u_long cmd, struct ifreq *); -static int wan_xilinx_send(struct mbuf *, struct ifnet *); - -static void handle_front_end_state(void *); -static void enable_timer(void *); - -/* Miscellaneous Functions */ -static void port_set_state (sdla_t *, int); - -/* Interrupt handlers */ -static void wp_xilinx_isr (sdla_t *); - -/* Miscellaneous functions */ -static int process_udp_mgmt_pkt(sdla_t *, struct ifnet *, - xilinx_softc_t *, int); -/* Bottom half handlers */ -static void xilinx_process_packet(xilinx_softc_t *); - -static int xilinx_chip_configure(sdla_t *); -static int xilinx_chip_unconfigure(sdla_t *); -static int xilinx_dev_configure(sdla_t *, xilinx_softc_t *); -static void xilinx_dev_unconfigure(sdla_t *, xilinx_softc_t *); -static int xilinx_dma_rx(sdla_t *, xilinx_softc_t *); -static void xilinx_dev_enable(sdla_t *, xilinx_softc_t *); -static void xilinx_dev_close(sdla_t *, xilinx_softc_t *); -static int xilinx_dma_tx (sdla_t *, xilinx_softc_t *); -static void xilinx_dma_tx_complete (sdla_t *, xilinx_softc_t *); -static void xilinx_dma_rx_complete (sdla_t *, xilinx_softc_t *); -static void xilinx_dma_max_logic_ch(sdla_t *); -static int xilinx_init_rx_dev_fifo(sdla_t *, xilinx_softc_t *, - unsigned char); -static void xilinx_init_tx_dma_descr(sdla_t *, xilinx_softc_t *); -static int xilinx_init_tx_dev_fifo(sdla_t *, xilinx_softc_t *, - unsigned char); -static void xilinx_tx_post_complete(sdla_t *, xilinx_softc_t *, - struct mbuf *); -static void xilinx_rx_post_complete(sdla_t *, xilinx_softc_t *, - struct xilinx_rx_buffer *, struct mbuf **, u_char *); - - -static char request_xilinx_logical_channel_num(sdla_t *, xilinx_softc_t *, - long *); -static void free_xilinx_logical_channel_num (sdla_t *, int); - - -static unsigned char read_cpld(sdla_t *, unsigned short); -static unsigned char write_cpld(sdla_t *, unsigned short, unsigned char); - -static void front_end_interrupt(sdla_t *, unsigned long); -static void enable_data_error_intr(sdla_t *); -static void disable_data_error_intr(sdla_t *, unsigned char); - -static void xilinx_tx_fifo_under_recover(sdla_t *, xilinx_softc_t *); - -static int xilinx_write_ctrl_hdlc(sdla_t *, u_int32_t, - u_int8_t, u_int32_t); - -static int set_chan_state(sdla_t*, struct ifnet*, int); - -static int fifo_error_interrupt(sdla_t *, unsigned long); -static int request_fifo_baddr_and_size(sdla_t *, xilinx_softc_t *); -static int map_fifo_baddr_and_size(sdla_t *, - unsigned char, unsigned char *); -static int free_fifo_baddr_and_size(sdla_t *, xilinx_softc_t *); - -static void aft_red_led_ctrl(sdla_t *, int); -static void aft_led_timer(void *); - -static int aft_core_ready(sdla_t *); -static int aft_alloc_rx_buffers(xilinx_softc_t *); -static void aft_release_rx_buffers(xilinx_softc_t *); -static int aft_alloc_rx_dma_buff(xilinx_softc_t *, int); -static void aft_reload_rx_dma_buff(xilinx_softc_t *, - struct xilinx_rx_buffer *); -static void aft_release_rx_dma_buff(xilinx_softc_t *, - struct xilinx_rx_buffer *); - - -/* TE1 Control registers */ -static WRITE_FRONT_END_REG_T write_front_end_reg; -static READ_FRONT_END_REG_T read_front_end_reg; - -static void wan_ifmedia_sts(struct ifnet *, struct ifmediareq *); -static int wan_ifmedia_upd(struct ifnet *); - -static void -xilinx_delay(int sec) -{ -#if 0 - unsigned long timeout = ticks; - while ((ticks - timeout) < (sec * hz)) { - schedule(); - } -#endif -} - -void * -wan_xilinx_init(sdla_t *card) -{ - xilinx_softc_t *sc; - struct ifnet *ifp; - - /* Verify configuration ID */ - bit_clear((u_int8_t *)&card->critical, CARD_DOWN); - - card->u.xilinx.num_of_ch = 0; - card->u.xilinx.mru_trans = 1500; - card->u.xilinx.dma_per_ch = 10; - - /* TE1 Make special hardware initialization for T1/E1 board */ - - if (IS_TE1(&card->fe_te.te_cfg)) { - card->write_front_end_reg = write_front_end_reg; - card->read_front_end_reg = read_front_end_reg; - card->te_enable_timer = enable_timer; - card->te_link_state = handle_front_end_state; - } else - card->front_end_status = FE_CONNECTED; - - /* WARNING: After this point the init function - * must return with 0. The following bind - * functions will cause problems if structures - * below are not initialized */ - - card->del_if = &wan_xilinx_release; - card->iface_up = &wan_xilinx_up; - card->iface_down = &wan_xilinx_down; - card->iface_send = &wan_xilinx_send; - card->iface_ioctl= &wan_xilinx_ioctl; - - write_cpld(card, LED_CONTROL_REG, 0x0E); - - sdla_getcfg(card->hw, SDLA_BASEADDR, &card->u.xilinx.bar); - - xilinx_delay(1); - - timeout_set(&card->u.xilinx.led_timer, aft_led_timer, (void *)card); - - /* allocate and initialize private data */ - sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); - if (sc == NULL) - return (NULL); - - ifp = (struct ifnet *)&sc->common.ifp; - ifp->if_softc = sc; - sc->common.card = card; - if (wanpipe_generic_register(card, ifp, card->devname)) { - free(sc, M_DEVBUF, 0); - return (NULL); - } - - strlcpy(sc->if_name, ifp->if_xname, IFNAMSIZ); - sc->first_time_slot = -1; - sc->time_slot_map = 0; - sdla_getcfg(card->hw, SDLA_DMATAG, &sc->dmatag); - - IFQ_SET_MAXLEN(&sc->wp_tx_pending_list, MAX_TX_BUF); - IFQ_SET_MAXLEN(&sc->wp_tx_complete_list, MAX_TX_BUF); - - aft_alloc_rx_buffers(sc); - - xilinx_delay(1); - - ifmedia_init(&sc->common.ifm, 0, wan_ifmedia_upd, wan_ifmedia_sts); - - if (IS_TE1(&card->fe_te.te_cfg)) { - ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_T1, 0, NULL); - ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_T1_AMI, 0, NULL); - ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_E1, 0, NULL); - ifmedia_add(&sc->common.ifm, IFM_TDM|IFM_TDM_E1_AMI, 0, NULL); - - ifmedia_add(&sc->common.ifm, - IFM_TDM|IFM_TDM_T1|IFM_TDM_PPP, 0, NULL); - ifmedia_add(&sc->common.ifm, - IFM_TDM|IFM_TDM_T1_AMI|IFM_TDM_PPP, 0, NULL); - ifmedia_add(&sc->common.ifm, - IFM_TDM|IFM_TDM_E1|IFM_TDM_PPP, 0, NULL); - ifmedia_add(&sc->common.ifm, - IFM_TDM|IFM_TDM_E1_AMI|IFM_TDM_PPP, 0, NULL); - - ifmedia_set(&sc->common.ifm, IFM_TDM|IFM_TDM_T1); - } else { - /* Currently we not support ifmedia types for other - * front end types. - */ - } - - return (sc); -} - -static int -wan_xilinx_release(sdla_t* card, struct ifnet* ifp) -{ - xilinx_softc_t *sc = ifp->if_softc; - - IF_PURGE(&sc->wp_tx_pending_list); - - if (sc->tx_dma_addr && sc->tx_dma_len) { - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - } - - if (sc->tx_dma_mbuf) { - log(LOG_INFO, "freeing tx dma mbuf\n"); - bus_dmamap_unload(sc->dmatag, sc->tx_dmamap); - m_freem(sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - } - -#if 0 - bus_dmamap_destroy(sc->dmatag, sc->tx_dmamap); -#endif - if (sc->rx_dma_buf) { - SIMPLEQ_INSERT_TAIL(&sc->wp_rx_free_list, - sc->rx_dma_buf, entry); - sc->rx_dma_buf = NULL; - } - - aft_release_rx_buffers(sc); - - wanpipe_generic_unregister(ifp); - ifp->if_softc = NULL; - free(sc, M_DEVBUF, 0); - - return (0); -} - -static void -wan_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmreq) -{ - wanpipe_common_t *common = (wanpipe_common_t *)ifp->if_softc; - struct ifmedia *ifm; - - WAN_ASSERT1(common == NULL); - ifm = &common->ifm; - ifmreq->ifm_active = ifm->ifm_cur->ifm_media; -} - -static int -wan_ifmedia_upd(struct ifnet *ifp) -{ - wanpipe_common_t *common = (wanpipe_common_t *)ifp->if_softc; - sdla_t *card; - - WAN_ASSERT(common == NULL); - WAN_ASSERT(common->card == NULL); - card = (sdla_t *)common->card; - - if (IS_TE1(&card->fe_te.te_cfg)) - return (sdla_te_setcfg(ifp, &common->ifm)); - - return (EINVAL); -} - - -/* - * KERNEL Device Entry Interfaces - */ - -static int -wan_xilinx_up(struct ifnet *ifp) -{ - xilinx_softc_t *sc = ifp->if_softc; - sdla_t *card = NULL; - struct timeval tv; - int err = 0; - - WAN_ASSERT(sc == NULL); - WAN_ASSERT(sc->common.card == NULL); - card = (sdla_t *)sc->common.card; - - if (card->state != WAN_DISCONNECTED) - return (0); - - sc->time_slot_map = card->fe_te.te_cfg.active_ch; - sc->dma_mtu = xilinx_valid_mtu(ifp->if_mtu+100); - - if (!sc->dma_mtu) { - log(LOG_INFO, "%s:%s: Error invalid MTU %u\n", - card->devname, sc->if_name, ifp->if_mtu); - return (EINVAL); - } - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Allocating %d dma mbuf len=%d\n", - card->devname, card->u.xilinx.dma_per_ch, sc->dma_mtu); -#endif - if (aft_alloc_rx_dma_buff(sc, card->u.xilinx.dma_per_ch) == 0) - return (ENOMEM); - - if (bus_dmamap_create(sc->dmatag, sc->dma_mtu, 1, sc->dma_mtu, - 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->tx_dmamap)) { - log(LOG_INFO, "%s: Failed to allocate tx dmamap\n", - sc->if_name); - return (ENOMEM); - } - - err = xilinx_chip_configure(card); - if (err) - return (EINVAL); - - card->isr = &wp_xilinx_isr; - - err = xilinx_dev_configure(card, sc); - if (err) { - xilinx_chip_unconfigure(card); - return (EINVAL); - } - xilinx_delay(1); - - /* Initialize the router start time. - * Used by wanpipemon debugger to indicate - * how long has the interface been up */ - microtime(&tv); - sc->router_start_time = tv.tv_sec; - - xilinx_init_tx_dma_descr(card, sc); - xilinx_dev_enable(card, sc); - - sc->ignore_modem = 0x0F; - bit_clear((u_int8_t *)&card->critical, CARD_DOWN); - port_set_state(card, WAN_CONNECTING); - - return (err); -} - -static int -wan_xilinx_down(struct ifnet *ifp) -{ - xilinx_softc_t *sc = ifp->if_softc; - sdla_t *card = (sdla_t *)sc->common.card; - struct xilinx_rx_buffer *buf; - int s; - - if (card->state == WAN_DISCONNECTED) - return (0); - - xilinx_dev_close(card, sc); - - /* Disable DMA ENGINE before we perform - * core reset. Otherwise, we will receive - * rx fifo errors on subsequent resetart. */ - disable_data_error_intr(card, DEVICE_DOWN); - - bit_set((u_int8_t *)&card->critical, CARD_DOWN); - - timeout_del(&card->u.xilinx.led_timer); - - /* TE1 - Unconfiging, only on shutdown */ - if (IS_TE1(&card->fe_te.te_cfg)) - sdla_te_unconfig(card); - - s = splnet(); - - card->isr = NULL; - - if (sc->tx_dma_addr && sc->tx_dma_len) { - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - } - - if (sc->tx_dma_mbuf) { - bus_dmamap_unload(sc->dmatag, sc->tx_dmamap); - m_freem(sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - } - - bus_dmamap_destroy(sc->dmatag, sc->tx_dmamap); - - /* If there is something left in rx_dma_buf, then move it to - * rx_free_list. - */ - if (sc->rx_dma_buf) { - aft_reload_rx_dma_buff(sc, sc->rx_dma_buf); - sc->rx_dma_buf = NULL; - } - - while ((buf = SIMPLEQ_FIRST(&sc->wp_rx_free_list)) != NULL) { - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_free_list, entry); - aft_release_rx_dma_buff(sc, buf); - } - - while ((buf = SIMPLEQ_FIRST(&sc->wp_rx_complete_list)) != NULL) { - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_complete_list, entry); - aft_release_rx_dma_buff(sc, buf); - } - - splx(s); - - DELAY(10); - - xilinx_dev_unconfigure(card, sc); - xilinx_chip_unconfigure(card); - - port_set_state(card, WAN_DISCONNECTED); - sc->ignore_modem = 0x00; - return (0); -} - -static int -wan_xilinx_send(struct mbuf* m, struct ifnet* ifp) -{ - - xilinx_softc_t *sc = ifp->if_softc; - sdla_t *card = (sdla_t *)sc->common.card; - - /* Mark interface as busy. The kernel will not - * attempt to send any more packets until we clear - * this condition */ - - if (m == NULL) - /* This should never happen. Just a sanity check. - */ - return (EINVAL); - - if (card->state != WAN_CONNECTED) { - /* - * The card is still not ready to transmit... - * drop this packet! - */ - m_freem(m); - return (EINVAL); - - } else { - if (IF_QFULL(&sc->wp_tx_pending_list)) { - int err; -#ifdef DEBUG_TX - log(LOG_INFO, "%s: Tx pending queue FULL\n", - ifp->if_xname); -#endif - /* - * TX pending queue is full. Try to send packet - * from tx_pending queue (first) - */ - err = xilinx_dma_tx(card, sc); - if (!err && !IF_QFULL(&sc->wp_tx_pending_list)) - /* - * On success, we have place for the new - * tx packet, try to send it now! - */ - goto wan_xilinx_dma_tx_try; - - /* - * Tx pedning queue is full. I can't accept new - * tx packet, drop this packet and set interface - * queue to OACTIVE - */ - m_freem(m); - ifp->if_flags |= IFF_OACTIVE; - - return (EBUSY); - } else { -wan_xilinx_dma_tx_try: - IF_ENQUEUE(&sc->wp_tx_pending_list, m); - xilinx_dma_tx(card, sc); - } - } - - return (0); -} - -static int -wan_xilinx_ioctl(struct ifnet *ifp, u_long cmd, struct ifreq *ifr) -{ - xilinx_softc_t *sc = (xilinx_softc_t *)ifp->if_softc; - struct mbuf *m; - sdla_t *card; - wan_udp_pkt_t *wan_udp_pkt; - int err = 0; - - if (!sc) - return (ENODEV); - - card = (sdla_t *)sc->common.card; - - switch (cmd) { - case SIOC_WANPIPE_PIPEMON: - - if ((err = suser(curproc, 0)) != 0) - break; - - if (IF_QFULL(&sc->udp_queue)) - return (EBUSY); - - /* - * For performance reasons test the critical - * here before spin lock - */ - if (bit_test((u_int8_t *)&card->in_isr, 0)) - return (EBUSY); - - m = wan_mbuf_alloc(sizeof(wan_udp_pkt_t)); - if (m == NULL) - return (ENOMEM); - - wan_udp_pkt = mtod(m, wan_udp_pkt_t *); - if (copyin(ifr->ifr_data, &wan_udp_pkt->wan_udp_hdr, - sizeof(wan_udp_hdr_t))) { - m_freem(m); - return (EFAULT); - } - IF_ENQUEUE(&sc->udp_queue, m); - - process_udp_mgmt_pkt(card, ifp, sc, 1); - - if (copyout(&wan_udp_pkt->wan_udp_hdr, ifr->ifr_data, - sizeof(wan_udp_hdr_t))) { - m_freem(m); - return (EFAULT); - } - - IF_DEQUEUE(&sc->udp_queue, m); - m_freem(m); - return (0); - - default: - if (card->ioctl) - err = card->ioctl(ifp, cmd, ifr); - break; - } - - return (err); -} - -/* - * Process all "wanpipemon" debugger commands. This function - * performs all debugging tasks: - * - * Line Tracing - * Line/Hardware Statistics - * Protocol Statistics - * - * "wanpipemon" utility is a user-space program that - * is used to debug the WANPIPE product. - */ -static int -process_udp_mgmt_pkt(sdla_t* card, struct ifnet* ifp, - xilinx_softc_t* sc, int local_dev ) -{ - struct mbuf *m; - unsigned short buffer_length; - wan_udp_pkt_t *wan_udp_pkt; - wan_trace_t *trace_info = NULL; - struct timeval tv; - - IF_POLL(&sc->udp_queue, m); - if (m == NULL) - return (EINVAL); - - wan_udp_pkt = mtod(m, wan_udp_pkt_t *); - trace_info=&sc->trace_info; - - { - struct mbuf *m0; - - wan_udp_pkt->wan_udp_opp_flag = 0; - - switch (wan_udp_pkt->wan_udp_command) { - - case READ_CONFIGURATION: - case READ_CODE_VERSION: - wan_udp_pkt->wan_udp_return_code = 0; - wan_udp_pkt->wan_udp_data_len = 0; - break; - - - case ENABLE_TRACING: - - wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK; - wan_udp_pkt->wan_udp_data_len = 0; - - if (!bit_test((u_int8_t *) - &trace_info->tracing_enabled, 0)) { - - trace_info->trace_timeout = ticks; - - IF_PURGE(&trace_info->ifq); - if (wan_udp_pkt->wan_udp_data[0] == 0) { - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 1); - log(LOG_INFO, "%s: ADSL L3 " - "trace enabled!\n", card->devname); - } else if (wan_udp_pkt->wan_udp_data[0] == 1) { - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 2 ); - bit_set((u_int8_t *) - &trace_info->tracing_enabled, 1); - log(LOG_INFO, "%s: ADSL L2 " - "trace enabled!\n", card->devname); - } else { - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 1); - bit_set((u_int8_t *) - &trace_info->tracing_enabled, 2); - log(LOG_INFO, "%s: ADSL L1 " - "trace enabled!\n", card->devname); - } - bit_set((u_int8_t *)& - trace_info->tracing_enabled, 0); - - } else { - log(LOG_INFO, "%s: Error: AFT " - "trace running!\n", card->devname); - wan_udp_pkt->wan_udp_return_code = 2; - } - - break; - - case DISABLE_TRACING: - wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK; - - if (bit_test((u_int8_t *) - &trace_info->tracing_enabled, 0)) { - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 0); - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 1); - bit_clear((u_int8_t *) - &trace_info->tracing_enabled, 2); - IF_PURGE(&trace_info->ifq); - log(LOG_INFO, "%s: Disabling ADSL trace\n", - card->devname); - } else { - /* - * set return code to line trace already - * disabled - */ - wan_udp_pkt->wan_udp_return_code = 1; - } - - break; - - case GET_TRACE_INFO: - if (bit_test((u_int8_t *) - &trace_info->tracing_enabled, 0)) { - trace_info->trace_timeout = ticks; - } else { - log(LOG_INFO, "%s: Error AFT trace " - "not enabled\n", card->devname); - /* set return code */ - wan_udp_pkt->wan_udp_return_code = 1; - break; - } - - buffer_length = 0; - wan_udp_pkt->wan_udp_aft_num_frames = 0; - wan_udp_pkt->wan_udp_aft_ismoredata = 0; - - while (!IF_IS_EMPTY(&trace_info->ifq)) { - IF_POLL(&trace_info->ifq, m0); - if (m0 == NULL) { - log(LOG_INFO, "%s: No more " - "trace packets in trace queue!\n", - card->devname); - break; - } - if ((WAN_MAX_DATA_SIZE - buffer_length) < - m0->m_pkthdr.len) { - /* - * indicate there are more frames - * on board & exit - */ - wan_udp_pkt->wan_udp_aft_ismoredata - = 0x01; - break; - } - - m_copydata(m0, 0, m0->m_pkthdr.len, - &wan_udp_pkt->wan_udp_data[buffer_length]); - buffer_length += m0->m_pkthdr.len; - IF_DEQUEUE(&trace_info->ifq, m0); - if (m0) - m_freem(m0); - wan_udp_pkt->wan_udp_aft_num_frames++; - } - /* set the data length and return code */ - wan_udp_pkt->wan_udp_data_len = buffer_length; - wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK; - break; - - case ROUTER_UP_TIME: - microtime(&tv); - sc->router_up_time = tv.tv_sec; - sc->router_up_time -= sc->router_start_time; - *(unsigned long *)&wan_udp_pkt->wan_udp_data = - sc->router_up_time; - wan_udp_pkt->wan_udp_data_len = sizeof(unsigned long); - wan_udp_pkt->wan_udp_return_code = 0; - break; - - case WAN_GET_MEDIA_TYPE: - case WAN_FE_GET_STAT: - case WAN_FE_SET_LB_MODE: - case WAN_FE_FLUSH_PMON: - case WAN_FE_GET_CFG: - - if (IS_TE1(&card->fe_te.te_cfg)) { - sdla_te_udp(card, - &wan_udp_pkt->wan_udp_cmd, - &wan_udp_pkt->wan_udp_data[0]); - } else { - if (wan_udp_pkt->wan_udp_command == - WAN_GET_MEDIA_TYPE) { - wan_udp_pkt->wan_udp_data_len = - sizeof(unsigned char); - wan_udp_pkt->wan_udp_return_code = - WAN_CMD_OK; - } else { - wan_udp_pkt->wan_udp_return_code = - WAN_UDP_INVALID_CMD; - } - } - break; - - case WAN_GET_PROTOCOL: - wan_udp_pkt->wan_udp_aft_num_frames = WANCONFIG_AFT; - wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK; - wan_udp_pkt->wan_udp_data_len = 1; - break; - - case WAN_GET_PLATFORM: - wan_udp_pkt->wan_udp_data[0] = WAN_PLATFORM_ID; - wan_udp_pkt->wan_udp_return_code = WAN_CMD_OK; - wan_udp_pkt->wan_udp_data_len = 1; - break; - - default: - wan_udp_pkt->wan_udp_data_len = 0; - wan_udp_pkt->wan_udp_return_code = 0xCD; - - log(LOG_INFO, "%s: Warning, Illegal UDP " - "command attempted from network: %x\n", - card->devname, wan_udp_pkt->wan_udp_command); - break; - } - } - - wan_udp_pkt->wan_udp_request_reply = UDPMGMT_REPLY; - return (1); -} - -/* - * FIRMWARE Specific Interface Functions - */ - -static int -xilinx_chip_configure(sdla_t *card) -{ - u_int32_t reg, tmp; - int err = 0; - u_int16_t adapter_type, adptr_security; - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "Xilinx Chip Configuration. -- \n"); -#endif - xilinx_delay(1); - - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - - /* Configure for T1 or E1 front end */ - if (IS_T1(&card->fe_te.te_cfg)) { - card->u.xilinx.num_of_time_slots = NUM_OF_T1_CHANNELS; - bit_clear((u_int8_t *)®, INTERFACE_TYPE_T1_E1_BIT); - bit_set((u_int8_t *)®, FRONT_END_FRAME_FLAG_ENABLE_BIT); - } else if (IS_E1(&card->fe_te.te_cfg)) { - card->u.xilinx.num_of_time_slots = NUM_OF_E1_CHANNELS; - bit_set((u_int8_t *)®, INTERFACE_TYPE_T1_E1_BIT); - bit_set((u_int8_t *)®, FRONT_END_FRAME_FLAG_ENABLE_BIT); - } else { - log(LOG_INFO, "%s: Error: Xilinx doesn't " - "support non T1/E1 interface!\n", card->devname); - return (EINVAL); - } - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - DELAY(10000); - - /* Reset PMC */ - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - bit_clear((u_int8_t *)®, FRONT_END_RESET_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - DELAY(1000); - - bit_set((u_int8_t *)®, FRONT_END_RESET_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - DELAY(100); - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "--- Chip Reset. -- \n"); -#endif - - /* Reset Chip Core */ - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - bit_set((u_int8_t *)®, CHIP_RESET_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - DELAY(100); - - /* Disable the chip/hdlc reset condition */ - bit_clear((u_int8_t *)®, CHIP_RESET_BIT); - - /* Disable ALL chip interrupts */ - bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT); - bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT); - bit_clear((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT); - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - xilinx_delay(1); - - sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type); - DELAY(100); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Hardware Adapter Type 0x%X\n", - card->devname, adapter_type); -#endif - - adptr_security = read_cpld(card, SECURITY_CPLD_REG); - adptr_security = adptr_security >> SECURITY_CPLD_SHIFT; - adptr_security = adptr_security & SECURITY_CPLD_MASK; - -#ifdef DEBUG_INIT - switch (adptr_security) { - case SECURITY_1LINE_UNCH: - log(LOG_INFO, "%s: Security 1 Line UnCh\n", card->devname); - break; - case SECURITY_1LINE_CH: - log(LOG_INFO, "%s: Security 1 Line Ch\n", card->devname); - break; - case SECURITY_2LINE_UNCH: - log(LOG_INFO, "%s: Security 2 Line UnCh\n", card->devname); - break; - case SECURITY_2LINE_CH: - log(LOG_INFO, "%s: Security 2 Line Ch\n", card->devname); - break; - default: - log(LOG_INFO, "%s: Error Invalid Security ID = 0x%X\n", - card->devname, adptr_security); - /* return EINVAL;*/ - } -#endif - - /* Turn off Onboard RED LED */ - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - bit_set((u_int8_t *)®, XILINX_RED_LED); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - DELAY(10); - - err = aft_core_ready(card); - if (err != 0) - log(LOG_INFO, "%s: WARNING: HDLC Core Not Ready: B4 TE CFG!\n", - card->devname); - - log(LOG_INFO, "%s: Configuring A101 PMC T1/E1/J1 Front End\n", - card->devname); - - if (sdla_te_config(card)) { - log(LOG_INFO, "%s: Failed %s configuration!\n", card->devname, - IS_T1(&card->fe_te.te_cfg)?"T1":"E1"); - return (EINVAL); - } - - xilinx_delay(1); - - err = aft_core_ready(card); - if (err != 0) { - log(LOG_INFO, "%s: Error: HDLC Core Not Ready!\n", - card->devname); - - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - - /* Disable the chip/hdlc reset condition */ - bit_set((u_int8_t *)®, CHIP_RESET_BIT); - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - return (err); - } - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: HDLC Core Ready 0x%08X\n", - card->devname, reg); -#endif - - xilinx_delay(1); - - /* Setup global DMA parameters */ - reg = 0; - reg|=(XILINX_DMA_SIZE << DMA_SIZE_BIT_SHIFT); - reg|=(XILINX_DMA_FIFO_UP << DMA_FIFO_HI_MARK_BIT_SHIFT); - reg|=(XILINX_DMA_FIFO_LO << DMA_FIFO_LO_MARK_BIT_SHIFT); - - /* - * Enable global DMA engine and set to default - * number of active channels. Note: this value will - * change in dev configuration - */ - reg|=(XILINX_DEFLT_ACTIVE_CH << DMA_ACTIVE_CHANNEL_BIT_SHIFT); - bit_set((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT); - -#ifdef DEBUG_INIT - log(LOG_INFO, "--- Setup DMA control Reg. -- \n"); -#endif - - sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg); - -#ifdef DEBUG_INIT - log(LOG_INFO, "--- Tx/Rx global enable. -- \n"); -#endif - - xilinx_delay(1); - - reg = 0; - sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg); - - /* Clear interrupt pending registers befor first interrupt enable */ - sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, &tmp); - sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, &tmp); - sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, &tmp); - sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, &tmp); - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, (u_int32_t *)®); - if (bit_test((u_int8_t *)®, DMA_INTR_FLAG)) { - log(LOG_INFO, "%s: Error: Active DMA Interrupt Pending. !\n", - card->devname); - - reg = 0; - /* Disable the chip/hdlc reset condition */ - bit_set((u_int8_t *)®, CHIP_RESET_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - return (err); - } - if (bit_test((u_int8_t *)®, ERROR_INTR_FLAG)) { - log(LOG_INFO, "%s: Error: Active Error Interrupt Pending. !\n", - card->devname); - - reg = 0; - /* Disable the chip/hdlc reset condition */ - bit_set((u_int8_t *)®, CHIP_RESET_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - return (err); - } - - - /* Alawys disable global data and error interrupts */ - bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT); - bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT); - - /* Always enable the front end interrupt */ - bit_set((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT); - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "--- Set Global Interrupts (0x%X)-- \n", reg); -#endif - - xilinx_delay(1); - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - return (err); -} - -static int -xilinx_chip_unconfigure(sdla_t *card) -{ - u_int32_t reg = 0; - - sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, reg); - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - /* Enable the chip/hdlc reset condition */ - reg = 0; - bit_set((u_int8_t *)®, CHIP_RESET_BIT); - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - return (0); -} - -static int -xilinx_dev_configure(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg; - long free_logic_ch, i; - - sc->logic_ch_num=-1; - - if (!IS_TE1(&card->fe_te.te_cfg)) - return (EINVAL); - - if (IS_E1(&card->fe_te.te_cfg)) { - log(LOG_DEBUG, "%s: Time Slot Orig 0x%lX Shifted 0x%lX\n", - sc->if_name, sc->time_slot_map, sc->time_slot_map << 1); - sc->time_slot_map = sc->time_slot_map << 1; - bit_clear((u_int8_t *)&sc->time_slot_map, 0); - } - - /* - * Channel definition section. If not channels defined - * return error - */ - if (sc->time_slot_map == 0) { - log(LOG_INFO, "%s: Invalid Channel Selection 0x%lX\n", - card->devname, sc->time_slot_map); - return (EINVAL); - } - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s:%s: Active channels = 0x%lX\n", card->devname, - sc->if_name, sc->time_slot_map); -#endif - xilinx_delay(1); - - /* - * Check that the time slot is not being used. If it is - * stop the interface setup. Notice, though we proceed - * to check for all timeslots before we start binding - * the channels in. This way, we don't have to go back - * and clean the time_slot_map - */ - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&sc->time_slot_map, i)) { - - if (sc->first_time_slot == -1) { -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting first time " - "slot to %ld\n", card->devname, i); -#endif - sc->first_time_slot = i; - } - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "%s: Configuring %s for timeslot %ld\n", - card->devname, sc->if_name, - IS_E1(&card->fe_te.te_cfg)?i:i+1); -#endif - if (bit_test((u_int8_t *) - &card->u.xilinx.time_slot_map, i)) { - log(LOG_INFO, "%s: Channel/Time Slot " - "resource conflict!\n", card->devname); - log(LOG_INFO, "%s: %s: Channel/Time Slot " - "%ld, aready in use!\n", - card->devname, sc->if_name, (i+1)); - - return (EEXIST); - } - - /* Calculate the number of timeslots for this if */ - ++sc->num_of_time_slots; - } - } - - xilinx_delay(1); - - sc->logic_ch_num = request_xilinx_logical_channel_num(card, - sc, &free_logic_ch); - if (sc->logic_ch_num == -1) - return (EBUSY); - - xilinx_delay(1); - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&sc->time_slot_map, i)) { - - bit_set((u_int8_t *)&card->u.xilinx.time_slot_map, i); - - sdla_bus_read_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - reg &= ~TIMESLOT_BIT_MASK; - - /* FIXME do not hardcode !*/ - reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits*/ - - /* Select a Timeslot for configuration */ - sdla_bus_write_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (i << TIMESLOT_BIT_SHIFT))); - - reg = sc->logic_ch_num & CONTROL_RAM_DATA_MASK; - -#ifdef TRUE_FIFO_SIZE - reg |= (sc->fifo_size_code & HDLC_FIFO_SIZE_MASK) << - HDLC_FIFO_SIZE_SHIFT; -#else - reg |= (HARD_FIFO_CODE & - HDLC_FIFO_SIZE_MASK) << HDLC_FIFO_SIZE_SHIFT; -#endif /* TRUE_FIFO_SIZE */ - - reg |= (sc->fifo_base_addr & HDLC_FIFO_BASE_ADDR_MASK) - << HDLC_FIFO_BASE_ADDR_SHIFT; - -#ifdef DEBUG_INIT - log(LOG_INFO, "Setting Timeslot %ld to logic " - "ch %ld Reg=0x%X\n", i, sc->logic_ch_num, reg); -#endif - xilinx_write_ctrl_hdlc(card, i, - XILINX_CONTROL_RAM_ACCESS_BUF, reg); - } - } - - if (free_logic_ch != -1) { - - char free_ch_used = 0; - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (!bit_test((u_int8_t *) - &card->u.xilinx.time_slot_map, i)) { - - sdla_bus_read_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - - reg &= ~TIMESLOT_BIT_MASK; - /* mask not valid bits */ - reg &= HDLC_LCH_TIMESLOT_MASK; - - /* Select a Timeslot for configuration */ - sdla_bus_write_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (i << TIMESLOT_BIT_SHIFT))); - - reg = free_logic_ch&CONTROL_RAM_DATA_MASK; - - /* For the rest of the unused logic channels - * bind them to timeslot 31 and set the fifo - * size to 32 byte = Code = 0x00 */ - reg |= (FIFO_32B & HDLC_FIFO_SIZE_MASK) - << HDLC_FIFO_SIZE_SHIFT; - - reg |= (free_logic_ch & - HDLC_FIFO_BASE_ADDR_MASK) << - HDLC_FIFO_BASE_ADDR_SHIFT; - -#ifdef DEBUG_INIT - log(LOG_INFO, "Setting Timeslot " - "%ld to free logic ch %ld Reg=0x%X\n", - i, free_logic_ch, reg); -#endif - xilinx_write_ctrl_hdlc(card, i, - XILINX_CONTROL_RAM_ACCESS_BUF, reg); - - free_ch_used = 1; - } - } - - /* We must check if the free logic has been bound - * to any timeslots */ - if (free_ch_used) { -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting Free CH %ld to idle\n", - sc->if_name, free_logic_ch); -#endif - xilinx_delay(1); - - /* Setup the free logic channel as IDLE */ - - sdla_bus_read_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - - reg &= ~HDLC_LOGIC_CH_BIT_MASK; - - /* mask not valid bits */ - reg &= HDLC_LCH_TIMESLOT_MASK; - - sdla_bus_write_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg|(free_logic_ch&HDLC_LOGIC_CH_BIT_MASK))); - - reg = 0; - bit_clear((u_int8_t *)®, HDLC_RX_PROT_DISABLE_BIT); - bit_clear((u_int8_t *)®, HDLC_TX_PROT_DISABLE_BIT); - - bit_set((u_int8_t *)®, HDLC_RX_ADDR_RECOGN_DIS_BIT); - - xilinx_write_ctrl_hdlc(card, sc->first_time_slot, - XILINX_HDLC_CONTROL_REG, reg); - } - } - - /* Select an HDLC logic channel for configuration */ - sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - - reg &= ~HDLC_LOGIC_CH_BIT_MASK; - reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */ - - sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK))); - - reg = 0; - - /* HDLC engine is enabled on the above logical channels */ - bit_clear((u_int8_t *)®, HDLC_RX_PROT_DISABLE_BIT); - bit_clear((u_int8_t *)®, HDLC_TX_PROT_DISABLE_BIT); - - bit_set((u_int8_t *)®, HDLC_TX_CHAN_ENABLE_BIT); - bit_set((u_int8_t *)®, HDLC_RX_ADDR_RECOGN_DIS_BIT); - - xilinx_write_ctrl_hdlc(card, sc->first_time_slot, - XILINX_HDLC_CONTROL_REG, reg); - - return (0); -} - -static void -xilinx_dev_unconfigure(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg; - int i, s; - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "\n-- Unconfigure Xilinx. --\n"); -#endif - - /* Select an HDLC logic channel for configuration */ - if (sc->logic_ch_num != -1) { - - sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - reg &= ~HDLC_LOGIC_CH_BIT_MASK; - reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */ - - sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK))); - - reg = 0x00020000; - xilinx_write_ctrl_hdlc(card, sc->first_time_slot, - XILINX_HDLC_CONTROL_REG, reg); - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&sc->time_slot_map, i)) { - sdla_bus_read_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - reg &= ~TIMESLOT_BIT_MASK; - - /* mask not valid bits */ - reg &= HDLC_LCH_TIMESLOT_MASK; - - /* Select a Timeslot for configuration */ - sdla_bus_write_4(card->hw, - XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (i<logic_ch_num); - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) - if (bit_test((u_int8_t *)&sc->time_slot_map, i)) - --sc->num_of_time_slots; - - free_fifo_baddr_and_size(card, sc); - splx(s); - - sc->logic_ch_num = -1; - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) - if (bit_test((u_int8_t *)&sc->time_slot_map, i)) - bit_clear((u_int8_t *) - &card->u.xilinx.time_slot_map, i); - } -} - -#define FIFO_RESET_TIMEOUT_CNT 1000 -#define FIFO_RESET_TIMEOUT_US 10 -static int -xilinx_init_rx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait) -{ - u_int32_t reg; - u_int32_t dma_descr; - u_int8_t timeout = 1; - u_int16_t i; - - /* Clean RX DMA fifo */ - dma_descr = (unsigned long)(sc->logic_ch_num << 4) + - XILINX_RxDMA_DESCRIPTOR_HI; - reg = 0; - bit_set((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT); - -#ifdef DEBUG_INIT - log(LOG_DEBUG, - "%s: Clearing RX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n", - sc->if_name, dma_descr, reg, __FUNCTION__); -#endif - - sdla_bus_write_4(card->hw, dma_descr, reg); - - if (wait == WP_WAIT) { - for (i = 0; i < FIFO_RESET_TIMEOUT_CNT; i++) { - sdla_bus_read_4(card->hw, dma_descr, ®); - if (bit_test((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT)) { - DELAY(FIFO_RESET_TIMEOUT_US); - continue; - } - timeout = 0; - break; - } - -#ifdef DEBUG_INIT - if (timeout) - log(LOG_INFO, "%s:%s: Error: Rx fifo reset " - "timedout %u us\n", card->devname, - sc->if_name, i * FIFO_RESET_TIMEOUT_US); - else - log(LOG_INFO, "%s:%s: Rx Fifo reset " - "successful %u us\n", card->devname, sc->if_name, - i * FIFO_RESET_TIMEOUT_US); -#endif - } else - timeout = 0; - - return (timeout); -} - -static int -xilinx_init_tx_dev_fifo(sdla_t *card, xilinx_softc_t *sc, unsigned char wait) -{ - u_int32_t reg; - u_int32_t dma_descr; - u_int8_t timeout = 1; - u_int16_t i; - - /* Clean TX DMA fifo */ - dma_descr = (unsigned long)(sc->logic_ch_num << 4) + - XILINX_TxDMA_DESCRIPTOR_HI; - reg = 0; - bit_set((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT); - -#ifdef DEBUG_INIT - log(LOG_DEBUG, - "%s: Clearing TX Fifo DmaDescr=(0x%X) Reg=(0x%X) (%s)\n", - sc->if_name, dma_descr, reg, __FUNCTION__); -#endif - sdla_bus_write_4(card->hw, dma_descr, reg); - - if (wait == WP_WAIT) { - for (i = 0; i < FIFO_RESET_TIMEOUT_CNT; i++) { - sdla_bus_read_4(card->hw, dma_descr, ®); - if (bit_test((u_int8_t *)®, INIT_DMA_FIFO_CMD_BIT)) { - DELAY(FIFO_RESET_TIMEOUT_US); - continue; - } - timeout = 0; - break; - } - -#ifdef DEBUG_INIT - if (timeout) - log(LOG_INFO, "%s:%s: Error: Tx fifo reset " - "timedout %u us\n", card->devname, sc->if_name, - i * FIFO_RESET_TIMEOUT_US); - else - log(LOG_INFO, "%s:%s: Tx Fifo reset " - "successful %u us\n", card->devname, sc->if_name, - i * FIFO_RESET_TIMEOUT_US); -#endif - } else - timeout = 0; - - return (timeout); -} - - -static void -xilinx_dev_enable(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg; - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Enabling Global Inter Mask !\n", sc->if_name); -#endif - /* Enable Logic Channel Interrupts for DMA and fifo */ - sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®); - bit_set((u_int8_t *)®, sc->logic_ch_num); - - sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg); - - bit_set((u_int8_t *)&card->u.xilinx.active_ch_map, sc->logic_ch_num); -} - -static void -xilinx_dev_close(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg; - unsigned long dma_descr; - int s; - -#ifdef DEBUG_INIT - log(LOG_DEBUG, "-- Close Xilinx device. --\n"); -#endif - /* Disable Logic Channel Interrupts for DMA and fifo */ - sdla_bus_read_4(card->hw, XILINX_GLOBAL_INTER_MASK, ®); - - bit_clear((u_int8_t *)®, sc->logic_ch_num); - bit_clear((u_int8_t *)&card->u.xilinx.active_ch_map, sc->logic_ch_num); - - /* - * We are masking the sc interrupt. - * Lock to make sure that the interrupt is - * not running - */ - s = splnet(); - sdla_bus_write_4(card->hw, XILINX_GLOBAL_INTER_MASK, reg); - splx(s); - - reg = 0; - - /* Select an HDLC logic channel for configuration */ - sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - - reg &= ~HDLC_LOGIC_CH_BIT_MASK; - reg &= HDLC_LCH_TIMESLOT_MASK; /* mask not valid bits */ - - sdla_bus_write_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, - (reg | (sc->logic_ch_num & HDLC_LOGIC_CH_BIT_MASK))); - - - reg = 0; - xilinx_write_ctrl_hdlc(card, sc->first_time_slot, - XILINX_HDLC_CONTROL_REG, reg); - - /* Clear descriptors */ - reg = 0; - dma_descr=(sc->logic_ch_num<<4) + XILINX_RxDMA_DESCRIPTOR_HI; - sdla_bus_write_4(card->hw, dma_descr, reg); - dma_descr=(sc->logic_ch_num<<4) + XILINX_TxDMA_DESCRIPTOR_HI; - sdla_bus_write_4(card->hw, dma_descr, reg); - - /* FIXME: Cleanp up Tx and Rx buffers */ -} - -static int -xilinx_dma_rx(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg; - unsigned long dma_descr; - unsigned long bus_addr; - wp_rx_element_t *rx_el; - - /* sanity check: make sure that DMA is in ready state */ -#if 0 - dma_descr=(sc->logic_ch_num<<4) + XILINX_RxDMA_DESCRIPTOR_HI; - sdla_bus_read_4(card->hw, dma_descr, ®); - - if (bit_test((u_int8_t *)®, RxDMA_HI_DMA_GO_READY_BIT)) { - log(LOG_INFO, "%s: Error: RxDMA GO Ready bit set on dma Rx\n", - card->devname); - return (EFAULT); - } -#endif - - if (sc->rx_dma_buf) { - log(LOG_INFO, "%s: Critial Error: Rx Dma Buf busy!\n", - sc->if_name); - return (EINVAL); - } - - sc->rx_dma_buf = SIMPLEQ_FIRST(&sc->wp_rx_free_list); - - if (sc->rx_dma_buf == NULL) { - if (aft_alloc_rx_dma_buff(sc, 1) == 0) { - log(LOG_INFO, "%s: Critical Error no rx dma buf!", - sc->if_name); - return (ENOMEM); - } - sc->rx_dma_buf = SIMPLEQ_FIRST(&sc->wp_rx_free_list); - } - - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_free_list, entry); - - bus_dmamap_sync(sc->dmatag, sc->rx_dma_buf->dma_map, 0, sc->dma_mtu, - BUS_DMASYNC_PREREAD); - - rx_el = &sc->rx_dma_buf->rx_el; - memset(rx_el, 0, sizeof(*rx_el)); - - bus_addr = sc->rx_dma_buf->dma_map->dm_segs[0].ds_addr; - rx_el->dma_addr = bus_addr; - - /* Write the pointer of the data packet to the - * DMA address register */ - reg = bus_addr; - - /* Set the 32bit alignment of the data length. - * Since we are setting up for rx, set this value - * to Zero */ - reg &= ~(RxDMA_LO_ALIGNMENT_BIT_MASK); - - dma_descr = (sc->logic_ch_num<<4) + XILINX_RxDMA_DESCRIPTOR_LO; - -#ifdef DEBUG_RX - log(LOG_INFO, "%s: RxDMA_LO = 0x%X, BusAddr=0x%lX " - "DmaDescr=0x%lX (%s)\n", card->devname, reg, bus_addr, - dma_descr, __FUNCTION__); -#endif - sdla_bus_write_4(card->hw, dma_descr, reg); - - dma_descr=(unsigned long)(sc->logic_ch_num << 4) + - XILINX_RxDMA_DESCRIPTOR_HI; - - reg = 0; - - reg |= (sc->dma_mtu >> 2) & RxDMA_HI_DMA_DATA_LENGTH_MASK; - -#ifdef TRUE_FIFO_SIZE - reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) << - DMA_FIFO_SIZE_SHIFT; -#else - - reg |= (HARD_FIFO_CODE & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT; -#endif - reg |= (sc->fifo_base_addr&DMA_FIFO_BASE_ADDR_MASK) << - DMA_FIFO_BASE_ADDR_SHIFT; - - bit_set((u_int8_t *)®, RxDMA_HI_DMA_GO_READY_BIT); - -#ifdef DEBUG_RX - log(LOG_INFO, "%s: RXDMA_HI = 0x%X, BusAddr=0x%lX DmaDescr=0x%lX " - "(%s)\n", sc->if_name, reg, bus_addr, dma_descr, __FUNCTION__); -#endif - - sdla_bus_write_4(card->hw, dma_descr, reg); - - bit_set((u_int8_t *)&sc->rx_dma, 0); - - return (0); -} - - -static int -xilinx_dma_tx(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg = 0; - struct mbuf *m; - unsigned long dma_descr; - unsigned char len_align = 0; - int len = 0; - -#ifdef DEBUG_TX - log(LOG_INFO, "------ Setup Tx DMA descriptor. --\n"); -#endif - - if (bit_test((u_int8_t *)&sc->dma_status, TX_BUSY)) { -#ifdef DEBUG_TX - log(LOG_INFO, "%s: TX_BUSY set (%s:%d)!\n", - sc->if_name, __FUNCTION__, __LINE__); -#endif - return EBUSY; - } - bit_set((u_int8_t *)&sc->dma_status, TX_BUSY); - - - /* - * Free the previously skb dma mapping. - * In this case the tx interrupt didn't finish and we must re-transmit. - */ - if (sc->tx_dma_addr && sc->tx_dma_len) { - log(LOG_INFO, "%s: Unmaping tx_dma_addr in %s\n", - sc->if_name, __FUNCTION__); - - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - } - - /* Free the previously sent tx packet. To - * minimize tx isr, the previously transmitted - * packet is deallocated here */ - if (sc->tx_dma_mbuf) { - bus_dmamap_unload(sc->dmatag, sc->tx_dmamap); - m_freem(sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - } - - /* check queue pointers before starting transmission */ - - /* sanity check: make sure that DMA is in ready state */ - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI; - -#ifdef DEBUG_TX - log(LOG_INFO, "%s: sc logic ch=%ld dma_descr=0x%lx set (%s:%d)!\n", - sc->if_name, sc->logic_ch_num, dma_descr, __FUNCTION__, __LINE__); -#endif - - sdla_bus_read_4(card->hw, dma_descr, ®); - - if (bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT)) { - log(LOG_INFO, "%s: Error: TxDMA GO Ready bit set " - "on dma Tx 0x%X\n", card->devname, reg); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (EFAULT); - } - - IF_DEQUEUE(&sc->wp_tx_pending_list, m); - - if (!m) { - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (ENOBUFS); - } - - len = m->m_len; - if (len > MAX_XILINX_TX_DMA_SIZE) { - /* FIXME: We need to split this frame into - * multiple parts. For now though - * just drop it :) */ - log(LOG_INFO, "%s: Tx len %d > %d (MAX TX DMA LEN)\n", - sc->if_name, len, MAX_XILINX_TX_DMA_SIZE); - m_freem(m); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (EINVAL); - } - - if (ADDR_MASK(mtod(m, caddr_t), 0x03)) { - /* The mbuf should already be aligned */ - log(LOG_INFO, "%s: TX packet not aligned!\n", - sc->if_name); - m_freem(m); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (EINVAL); - } - - if (bus_dmamap_load(sc->dmatag, sc->tx_dmamap, - mtod(m, void *), len, NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE)) { - log(LOG_INFO, "%s: Failed to load TX mbuf for DMA!\n", - sc->if_name); - m_freem(m); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (EINVAL); - } - - sc->tx_dma_addr = sc->tx_dmamap->dm_segs[0].ds_addr; - sc->tx_dma_len = len; - - if (sc->tx_dma_addr & 0x03) { - log(LOG_INFO, "%s: Error: Tx Ptr not aligned " - "to 32bit boundary!\n", card->devname); - m_freem(m); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return (EINVAL); - } - - sc->tx_dma_mbuf = m; - - /* WARNING: Do not use the "skb" pointer from - * here on. The skb pointer might not exist if - * we are in transparent mode */ - - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_LO; - - /* Write the pointer of the data packet to the - * DMA address register */ - reg = sc->tx_dma_addr; - - bus_dmamap_sync(sc->dmatag, sc->tx_dmamap, 0, len, - BUS_DMASYNC_PREWRITE); - - /* Set the 32bit alignment of the data length. - * Used to pad the tx packet to the 32 bit - * boundary */ - reg &= ~(TxDMA_LO_ALIGNMENT_BIT_MASK); - reg |= (len & 0x03); - - if (len & 0x03) - len_align = 1; - -#ifdef DEBUG_TX - log(LOG_INFO, "%s: TXDMA_LO=0x%X PhyAddr=0x%lX DmaDescr=0x%lX (%s)\n", - sc->if_name, reg, sc->tx_dma_addr, dma_descr, __FUNCTION__); -#endif - - sdla_bus_write_4(card->hw, dma_descr, reg); - - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI; - - reg = 0; - reg |= (((len >> 2) + len_align) & TxDMA_HI_DMA_DATA_LENGTH_MASK); - -#ifdef TRUE_FIFO_SIZE - reg |= (sc->fifo_size_code & DMA_FIFO_SIZE_MASK) << - DMA_FIFO_SIZE_SHIFT; -#else - - reg |= (HARD_FIFO_CODE & DMA_FIFO_SIZE_MASK) << DMA_FIFO_SIZE_SHIFT; -#endif - reg |= (sc->fifo_base_addr & DMA_FIFO_BASE_ADDR_MASK) << - DMA_FIFO_BASE_ADDR_SHIFT; - - /* - * Only enable the Frame Start/Stop on - * non-transparent hdlc configuration - */ - bit_set((u_int8_t *)®, TxDMA_HI_DMA_FRAME_START_BIT); - bit_set((u_int8_t *)®, TxDMA_HI_DMA_FRAME_END_BIT); - - bit_set((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT); - -#ifdef DEBUG_TX - log(LOG_INFO, "%s: TXDMA_HI=0x%X DmaDescr=0x%lX (%s)\n", - sc->if_name, reg, dma_descr, __FUNCTION__); -#endif - - sdla_bus_write_4(card->hw, dma_descr, reg); - - return (0); - -} - -static void -xilinx_dma_tx_complete(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg = 0; - unsigned long dma_descr; - -#ifdef DEBUG_TX - log(LOG_INFO, "%s: TX DMA complete\n", card->devname); -#endif - /* DEBUGTX */ -/* sdla_bus_read_4(card->hw, 0x78, &tmp1); */ - - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI; - sdla_bus_read_4(card->hw, dma_descr, ®); - - if (sc->tx_dma_mbuf == NULL) { - log(LOG_INFO, - "%s: Critical Error: Tx DMA intr: no tx mbuf !\n", - card->devname); - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - return; - } - - bus_dmamap_sync(sc->dmatag, sc->tx_dmamap, 0, sc->tx_dma_len, - BUS_DMASYNC_POSTWRITE); - - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - - /* Do not free the packet here, - * copy the packet dma info into csum - * field and let the bh handler analyze - * the transmitted packet. - */ - - if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) { - log(LOG_INFO, "%s:%s: PCI Error: 'Retry' " - "exceeds maximum (64k): Reg=0x%X!\n", - card->devname, sc->if_name, reg); - - if (++sc->pci_retry < 3) { - bit_set((u_int8_t *)®, - TxDMA_HI_DMA_GO_READY_BIT); - - log(LOG_INFO, "%s: Retry: TXDMA_HI=0x%X " - "DmaDescr=0x%lX (%s)\n", - sc->if_name, reg, dma_descr, __FUNCTION__); - - sdla_bus_write_4(card->hw, dma_descr, reg); - return; - } - } - - sc->pci_retry = 0; - sc->tx_dma_mbuf->m_pkthdr.csum_flags = reg & 0xFFFF; - sc->tx_dma_mbuf->m_pkthdr.ether_vtag = (reg >> 16) & 0xFFFF; - IF_ENQUEUE(&sc->wp_tx_complete_list, sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - - xilinx_process_packet(sc); -} - -static void -xilinx_tx_post_complete(sdla_t *card, xilinx_softc_t *sc, struct mbuf *m) -{ - struct ifnet *ifp; - u_int32_t reg; - - WAN_ASSERT1(sc == NULL); - reg = (m->m_pkthdr.ether_vtag << 16) + m->m_pkthdr.csum_flags; - ifp = (struct ifnet *)&sc->common.ifp; - if ((bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT)) || - (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK) || - (reg & TxDMA_HI_DMA_PCI_ERROR_MASK)) { - -#ifdef DEBUG_TX - log(LOG_INFO, "%s:%s: Tx DMA Descriptor=0x%lX\n", - card->devname, sc->if_name, reg); -#endif - - /* Checking Tx DMA Go bit. Has to be '0' */ - if (bit_test((u_int8_t *)®, TxDMA_HI_DMA_GO_READY_BIT)) - log(LOG_INFO, "%s:%s: Error: TxDMA Intr: " - "GO bit set on Tx intr\n", - card->devname, sc->if_name); - - if (reg & TxDMA_HI_DMA_DATA_LENGTH_MASK) - log(LOG_INFO, "%s:%s: Error: TxDMA Length " - "not equal 0 \n", card->devname, sc->if_name); - - /* Checking Tx DMA PCI error status. Has to be '0's */ - if (reg & TxDMA_HI_DMA_PCI_ERROR_MASK) { - - if (reg & TxDMA_HI_DMA_PCI_ERROR_M_ABRT) - log(LOG_INFO, "%s:%s: Tx Error: " - "Abort from Master: pci fatal error!\n", - card->devname, sc->if_name); - - if (reg & TxDMA_HI_DMA_PCI_ERROR_T_ABRT) - log(LOG_INFO, "%s:%s: Tx Error: " - "Abort from Target: pci fatal error!\n", - card->devname, sc->if_name); - - if (reg & TxDMA_HI_DMA_PCI_ERROR_DS_TOUT) { - log(LOG_INFO, "%s:%s: Tx Warning: " - "PCI Latency Timeout!\n", - card->devname, sc->if_name); - goto tx_post_ok; - } - if (reg & TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) - log(LOG_INFO, "%s:%s: Tx Error: 'Retry' " - "exceeds maximum (64k): pci fatal error!\n", - card->devname, sc->if_name); - } - goto tx_post_exit; - } - -tx_post_ok: - - if (ifp) - ifp->if_opackets++; - - /* Indicate that the first tx frame went - * out on the transparent link */ - bit_set((u_int8_t *)&sc->idle_start, 0); - -tx_post_exit: - - if (!xilinx_dma_tx(card, sc)) { - /* - * If we were able to transmit and the interface is set to - * OACTIVE remove this flag and let kernel try to transmit. - */ - if (ifp->if_flags & IFF_OACTIVE) - ifp->if_flags &= ~IFF_OACTIVE; - } - return; -} - -static void -xilinx_dma_rx_complete(sdla_t *card, xilinx_softc_t *sc) -{ - struct xilinx_rx_buffer *buf; - unsigned long dma_descr; - wp_rx_element_t *rx_el; - - bit_clear((u_int8_t *)&sc->rx_dma, 0); - - if (sc->rx_dma_buf == NULL) { - log(LOG_INFO, - "%s: Critical Error: rx_dma_mbuf\n", sc->if_name); - return; - } - - rx_el = &sc->rx_dma_buf->rx_el; - - /* Reading Rx DMA descriptor information */ - dma_descr=(sc->logic_ch_num << 4) + XILINX_RxDMA_DESCRIPTOR_LO; - sdla_bus_read_4(card->hw, dma_descr, &rx_el->align); - rx_el->align &= RxDMA_LO_ALIGNMENT_BIT_MASK; - - dma_descr = (sc->logic_ch_num << 4) + XILINX_RxDMA_DESCRIPTOR_HI; - sdla_bus_read_4(card->hw, dma_descr, &rx_el->reg); - - rx_el->pkt_error = sc->pkt_error; - sc->pkt_error = 0; - -#ifdef DEBUG_RX - log(LOG_INFO, "%s: RX HI=0x%X LO=0x%X DMA=0x%lX (%s:%d)\n", - sc->if_name, rx_el->reg, rx_el->align, rx_el->dma_addr, - __FUNCTION__, __LINE__); -#endif - - buf = sc->rx_dma_buf; - sc->rx_dma_buf = NULL; - - xilinx_dma_rx(card, sc); - - SIMPLEQ_INSERT_TAIL(&sc->wp_rx_complete_list, buf, entry); - - xilinx_process_packet(sc); - -/* sdla_bus_read_4(card->hw, 0x80, &rx_empty); */ -} - - -static void -xilinx_rx_post_complete(sdla_t *card, xilinx_softc_t *sc, - struct xilinx_rx_buffer *buf, struct mbuf **new_m, u_char *pkt_error) -{ - struct ifnet *ifp; - unsigned int len, data_error = 0; - wp_rx_element_t *rx_el = &buf->rx_el; - struct mbuf *m = buf->mbuf; - - WAN_ASSERT1(sc == NULL); - ifp = (struct ifnet *)&sc->common.ifp; /*m->m_pkthdr.rcvif;*/ - -#ifdef DEBUG_RX - log(LOG_INFO, "%s: RX HI=0x%X LO=0x%X DMA=0x%lX (%s:%d)\n", - sc->if_name, rx_el->reg, rx_el->align, rx_el->dma_addr, - __FUNCTION__, __LINE__); -#endif - rx_el->align &= RxDMA_LO_ALIGNMENT_BIT_MASK; - *pkt_error = 0; - *new_m = NULL; - - - /* Checking Rx DMA Go bit. Has to be '0' */ - if (bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_GO_READY_BIT)) { - log(LOG_INFO, "%s: Error: RxDMA Intr: GO bit set on Rx intr\n", - card->devname); - ifp->if_ierrors++; - goto rx_comp_error; - } - - /* Checking Rx DMA PCI error status. Has to be '0's */ - if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_MASK) { -#ifdef DEBUG_ERR - if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_M_ABRT) - log(LOG_INFO, "%s: Rx Error: Abort from Master: " - "pci fatal error!\n", card->devname); - - if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_T_ABRT) - log(LOG_INFO, "%s: Rx Error: Abort from Target: " - "pci fatal error!\n", card->devname); - - if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_DS_TOUT) - log(LOG_INFO, "%s: Rx Error: No 'DeviceSelect' " - "from target: pci fatal error!\n", card->devname); - - if (rx_el->reg & RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT) - log(LOG_INFO, "%s: Rx Error: 'Retry' exceeds maximum " - "(64k): pci fatal error!\n", card->devname); - - log(LOG_INFO, "%s: RXDMA PCI ERROR = 0x%x\n", - card->devname, rx_el->reg); -#endif - if (ifp) - ifp->if_ierrors++; - - goto rx_comp_error; - } - - /* Checking Rx DMA Frame start bit. (information for api) */ - if (!bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_FRAME_START_BIT)) { -#ifdef DEBUG_ERR - log(LOG_INFO, "%s: RxDMA Intr: Start flag missing: " - "MTU Mismatch! Reg=0x%X\n", card->devname, rx_el->reg); -#endif - if (ifp) - ifp->if_ierrors++; - goto rx_comp_error; - } - - /* Checking Rx DMA Frame end bit. (information for api) */ - if (!bit_test((u_int8_t *)&rx_el->reg, RxDMA_HI_DMA_FRAME_END_BIT)) { -#ifdef DEBUG_ERR - log(LOG_INFO, "%s: RxDMA Intr: End flag missing: " - "MTU Mismatch! Reg=0x%X\n", card->devname, rx_el->reg); -#endif - if (ifp) - ifp->if_ierrors++; - goto rx_comp_error; - - } else { /* Check CRC error flag only if this is the end of Frame */ - - if (bit_test((u_int8_t *)&rx_el->reg, - RxDMA_HI_DMA_CRC_ERROR_BIT)) { -#ifdef DEBUG_ERR - log(LOG_INFO, "%s: RxDMA Intr: CRC Error! Reg=0x%X\n", - card->devname, rx_el->reg); -#endif - if (ifp) - ifp->if_ierrors++; - - bit_set((u_int8_t *)&rx_el->pkt_error, - WP_CRC_ERROR_BIT); - data_error = 1; - } - - /* Check if this frame is an abort, if it is - * drop it and continue receiving */ - if (bit_test((u_int8_t *)&rx_el->reg, - RxDMA_HI_DMA_FRAME_ABORT_BIT)) { -#ifdef DEBUG_ERR - log(LOG_INFO, "%s: RxDMA Intr: Abort! Reg=0x%X\n", - card->devname, rx_el->reg); -#endif - if (ifp) - ifp->if_ierrors++; - - bit_set((u_int8_t *)&rx_el->pkt_error, - WP_ABORT_ERROR_BIT); - data_error = 1; - } - - if (data_error) - goto rx_comp_error; - } - - len = rx_el->reg & RxDMA_HI_DMA_DATA_LENGTH_MASK; - - /* In HDLC mode, calculate rx length based - * on alignment value, received from DMA */ - len = (((sc->dma_mtu >> 2) - len) << 2) - - (~(rx_el->align) & RxDMA_LO_ALIGNMENT_BIT_MASK); - - *pkt_error = rx_el->pkt_error; - - /* After a RX FIFO overflow, we must mark max 7 - * subsequent frames since firmware, cannot - * guarantee the contents of the fifo */ - - if (bit_test((u_int8_t *)&rx_el->pkt_error, WP_FIFO_ERROR_BIT)) { - if (++sc->rx_fifo_err_cnt >= WP_MAX_FIFO_FRAMES) { - sc->rx_fifo_err_cnt = 0; - } - bit_set((u_int8_t *)pkt_error, WP_FIFO_ERROR_BIT); - } else { - if (sc->rx_fifo_err_cnt) { - if (++sc->rx_fifo_err_cnt >= WP_MAX_FIFO_FRAMES) { - sc->rx_fifo_err_cnt = 0; - } - bit_set((u_int8_t *)pkt_error, WP_FIFO_ERROR_BIT); - } - } - - bus_dmamap_sync(sc->dmatag, sc->rx_dma_buf->dma_map, 0, len, - BUS_DMASYNC_POSTREAD); - - m->m_len = m->m_pkthdr.len = len; - - if (len > aft_rx_copyback) { - /* The rx size is big enough, thus - * send this buffer up the stack - * and allocate another one */ - *new_m = m; - buf->mbuf = NULL; - } else { - struct mbuf *m0; - /* The rx packet is very - * small thus, allocate a new - * buffer and pass it up */ - if ((m0 = m_copym2(m, 0, len, M_NOWAIT)) == NULL) { - log(LOG_INFO, "%s: Failed to allocate mbuf!\n", - sc->if_name); - if (ifp) - ifp->if_ierrors++; - } else - *new_m = m0; - } - - rx_comp_error: - aft_reload_rx_dma_buff(sc, buf); - - return; -} - - -static char -request_xilinx_logical_channel_num(sdla_t *card, xilinx_softc_t *sc, - long *free_ch) -{ - char logic_ch = -1, free_logic_ch = -1; - int i, err; - - *free_ch = -1; - -#ifdef DEBUG_INIT - log(LOG_INFO, "-- Request_Xilinx_logic_channel_num:--\n"); - log(LOG_INFO, "%s: Global Num Timeslots=%d " - "Global Logic ch Map 0x%lX (%s:%d)\n", - sc->if_name, card->u.xilinx.num_of_time_slots, - card->u.xilinx.logic_ch_map, __FUNCTION__, __LINE__); -#endif - - err = request_fifo_baddr_and_size(card, sc); - if (err) - return (-1); - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) { - bit_set((u_int8_t *)&card->u.xilinx.logic_ch_map, i); - logic_ch = i; - break; - } - } - - if (logic_ch == -1) - return (logic_ch); - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) { - free_logic_ch = HDLC_FREE_LOGIC_CH; - break; - } - } - - if (card->u.xilinx.dev_to_ch_map[(unsigned char)logic_ch]) { - log(LOG_INFO, "%s: Error, request logical ch=%d map busy\n", - card->devname, logic_ch); - return (-1); - } - - *free_ch = free_logic_ch; - - card->u.xilinx.dev_to_ch_map[(unsigned char)logic_ch] = (void *)sc; - - if (logic_ch > card->u.xilinx.top_logic_ch) { - card->u.xilinx.top_logic_ch = logic_ch; - xilinx_dma_max_logic_ch(card); - } - - return (logic_ch); -} - -static void -free_xilinx_logical_channel_num(sdla_t *card, int logic_ch) -{ - bit_clear((u_int8_t *)&card->u.xilinx.logic_ch_map, logic_ch); - card->u.xilinx.dev_to_ch_map[logic_ch] = NULL; - - if (logic_ch >= card->u.xilinx.top_logic_ch) { - int i; - - card->u.xilinx.top_logic_ch = XILINX_DEFLT_ACTIVE_CH; - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (card->u.xilinx.dev_to_ch_map[logic_ch]) - card->u.xilinx.top_logic_ch = i; - } - - xilinx_dma_max_logic_ch(card); - } - -} - -static void -xilinx_dma_max_logic_ch(sdla_t *card) -{ - u_int32_t reg; - -#ifdef DEBUG_INIT - log(LOG_INFO, "-- Xilinx_dma_max_logic_ch :--\n"); -#endif - - sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®); - - /* Set up the current highest active logic channel */ - - reg &= DMA_ACTIVE_CHANNEL_BIT_MASK; - reg |= (card->u.xilinx.top_logic_ch << DMA_ACTIVE_CHANNEL_BIT_SHIFT); - - sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg); -} - -static int -aft_alloc_rx_buffers(xilinx_softc_t *sc) -{ - struct xilinx_rx_buffer *buf; - - SIMPLEQ_INIT(&sc->wp_rx_free_list); - SIMPLEQ_INIT(&sc->wp_rx_complete_list); - - /* allocate receive buffers in one cluster */ - buf = malloc(sizeof(*buf) * MAX_RX_BUF, M_DEVBUF, M_NOWAIT | M_ZERO); - if (buf == NULL) - return (1); - - sc->wp_rx_buffers = buf; - sc->wp_rx_buffer_last = buf; - - return (0); -} - -static void -aft_release_rx_buffers(xilinx_softc_t *sc) -{ - struct xilinx_rx_buffer *buf; - - if (sc->wp_rx_buffers == NULL) - return; - - while ((buf = SIMPLEQ_FIRST(&sc->wp_rx_free_list)) != NULL) { - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_free_list, entry); - aft_release_rx_dma_buff(sc, buf); - } - - while ((buf = SIMPLEQ_FIRST(&sc->wp_rx_complete_list)) != NULL) { - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_complete_list, entry); - aft_release_rx_dma_buff(sc, buf); - } - - free(sc->wp_rx_buffers, M_DEVBUF, 0); - - sc->wp_rx_buffers = NULL; - sc->wp_rx_buffer_last = NULL; -} - -/* Allocate an mbuf and setup dma_map. */ -static int -aft_alloc_rx_dma_buff(xilinx_softc_t *sc, int num) -{ - struct xilinx_rx_buffer *buf, *ebuf; - int n; - - ebuf = sc->wp_rx_buffers + MAX_RX_BUF; - buf = sc->wp_rx_buffer_last; - - for (n = 0; n < num; n++) { - int i; - for (i = 0; i < MAX_RX_BUF; i++) { - if (buf->mbuf == NULL) - break; - if (++buf == ebuf) - buf = sc->wp_rx_buffers; - } - - if (buf->mbuf != NULL) - break; - - sc->wp_rx_buffer_last = buf; - - buf->mbuf = wan_mbuf_alloc(sc->dma_mtu); - if (buf->mbuf == NULL) - break; - - if (bus_dmamap_create(sc->dmatag, sc->dma_mtu, 1, sc->dma_mtu, - 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &buf->dma_map)) { - m_freem(buf->mbuf); - buf->mbuf = NULL; - break; - } - - if (bus_dmamap_load(sc->dmatag, buf->dma_map, - mtod(buf->mbuf, void *), sc->dma_mtu, NULL, - BUS_DMA_NOWAIT | BUS_DMA_READ)) { - aft_release_rx_dma_buff(sc, buf); - break; - } - - SIMPLEQ_INSERT_TAIL(&sc->wp_rx_free_list, buf, entry); - } - - return (n); -} - -static void -aft_reload_rx_dma_buff(xilinx_softc_t *sc, struct xilinx_rx_buffer *buf) -{ - bus_dmamap_unload(sc->dmatag, buf->dma_map); - if (buf->mbuf == NULL) { - buf->mbuf = wan_mbuf_alloc(sc->dma_mtu); - if (buf->mbuf == NULL) { - bus_dmamap_destroy(sc->dmatag, buf->dma_map); - return; - } - } - if (bus_dmamap_load(sc->dmatag, buf->dma_map, mtod(buf->mbuf, void *), - sc->dma_mtu, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ)) { - aft_release_rx_dma_buff(sc, buf); - return; - } - - SIMPLEQ_INSERT_TAIL(&sc->wp_rx_free_list, buf, entry); -} - -static void -aft_release_rx_dma_buff(xilinx_softc_t *sc, struct xilinx_rx_buffer *buf) -{ - bus_dmamap_destroy(sc->dmatag, buf->dma_map); - m_freem(buf->mbuf); - buf->mbuf = NULL; -} - -static void -enable_timer(void *card_id) -{ - sdla_t *card = (sdla_t *)card_id; - int s; - - s = splnet(); - sdla_te_polling(card); - splx(s); - - return; -} - -static void -xilinx_process_packet(xilinx_softc_t *sc) -{ - struct ifnet *ifp; - struct mbuf *new_m, *m; - unsigned char pkt_error; - - WAN_ASSERT1(sc == NULL); - for (;;) { - struct xilinx_rx_buffer *buf; - buf = SIMPLEQ_FIRST(&sc->wp_rx_complete_list); - if (buf == NULL) - break; - - SIMPLEQ_REMOVE_HEAD(&sc->wp_rx_complete_list, entry); - - new_m = NULL; - pkt_error = 0; - - xilinx_rx_post_complete(sc->common.card, sc, buf, &new_m, - &pkt_error); - if (new_m) { - ifp = (struct ifnet *)&sc->common.ifp; -#ifdef DEBUG_RX - log(LOG_INFO, "%s: Receiving packet %d bytes!\n", - ifp->if_xname, new_m->m_len); -#endif - wanpipe_generic_input(ifp, new_m); - } - } - - for (;;) { - IF_DEQUEUE(&sc->wp_tx_complete_list, m); - if (m == NULL) - break; - xilinx_tx_post_complete(sc->common.card, sc, m); - m_freem(m); - } - - return; -} - -static int -fifo_error_interrupt(sdla_t *card, unsigned long reg) -{ - u_int32_t rx_status, tx_status; - u_int32_t err = 0; - u_int32_t i; - xilinx_softc_t *sc; - -#ifdef DEBUG_ERR - log(LOG_INFO, "%s: Fifo error interrupt!\n", card->devname); -#endif - - /* Clear HDLC pending registers */ - sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, &tx_status); - sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, &rx_status); - - if (card->state != WAN_CONNECTED) { - log(LOG_INFO, "%s: Warning: Ignoring Error Intr: link disc!\n", - card->devname); - return (0); - } - - tx_status &= card->u.xilinx.active_ch_map; - rx_status &= card->u.xilinx.active_ch_map; - - if (tx_status != 0) { - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&tx_status, i) && - bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, - i)) { - struct ifnet *ifp; - - sc = (xilinx_softc_t *) - card->u.xilinx.dev_to_ch_map[i]; - if (!sc) { - log(LOG_INFO, "Warning: ignoring tx " - "error intr: no dev!\n"); - continue; - } - - ifp = (struct ifnet *)&sc->common.ifp; -#if 0 - if (!(ifp->if_flags & IFF_UP)) { - log(LOG_INFO, "%s: Warning: ignoring " - "tx error intr: dev down 0x%X " - "UP=0x%X!\n", ifp->if_xname, - sc->common.state, - sc->ignore_modem); - continue; - } -#endif - - if (card->state != WAN_CONNECTED) { - log(LOG_INFO, "%s: Warning: ignoring " - "tx error intr: dev disc!\n", - ifp->if_xname); - continue; - } - -#ifdef DEBUG_ERR - log(LOG_INFO, "%s:%s: Warning TX Fifo Error " - "on LogicCh=%ld Slot=%d!\n", - card->devname, sc->if_name, - sc->logic_ch_num, i); -#endif - xilinx_tx_fifo_under_recover(card, sc); - err=EINVAL; - } - } - } - - - if (rx_status != 0) { - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&rx_status, i) && - bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, - i)) { - struct ifnet *ifp; - sc = (xilinx_softc_t *) - card->u.xilinx.dev_to_ch_map[i]; - if (!sc) - continue; - - ifp = (struct ifnet *)&sc->common.ifp; -#if 0 - if (!(ifp->if_flags & IFF_UP)) { - log(LOG_INFO, "%s: Warning: ignoring " - "rx error intr: dev down " - "0x%X UP=0x%X!\n", ifp->if_xname, - sc->common.state, - sc->ignore_modem); - continue; - } -#endif - - if (card->state != WAN_CONNECTED) { - log(LOG_INFO, "%s: Warning: ignoring " - "rx error intr: dev disc!\n", - ifp->if_xname); - continue; - } - -#ifdef DEBUG_ERR - log(LOG_INFO, "%s:%s: Warning RX Fifo Error " - "on LCh=%ld Slot=%d RxDMA=%d\n", - card->devname, sc->if_name, - sc->logic_ch_num, i, - sc->rx_dma); -#endif - -#if 0 -{ - unsigned long dma_descr; - unsigned int reg; - dma_descr = (sc->logic_ch_num << 4) + - XILINX_RxDMA_DESCRIPTOR_HI; - sdla_bus_read_4(card->hw, dma_descr, ®); - log(LOG_INFO, "%s: Hi Descriptor 0x%X\n", - sc->if_name, reg); -} -#endif - - bit_set((u_int8_t *)&sc->pkt_error, - WP_FIFO_ERROR_BIT); - err = EINVAL; - } - } - } - - return (err); -} - - -static void -front_end_interrupt(sdla_t *card, unsigned long reg) -{ - sdla_te_intr(card); - handle_front_end_state(card); - return; -} - -/* - * HARDWARE Interrupt Handlers - */ - - -/* - * Main interrupt service routine. - * Determine the interrupt received and handle it. - */ -static void -wp_xilinx_isr(sdla_t* card) -{ - int i; - u_int32_t reg; - u_int32_t dma_tx_reg, dma_rx_reg; - xilinx_softc_t *sc; - - if (bit_test((u_int8_t *)&card->critical, CARD_DOWN)) { - log(LOG_INFO, "%s: Card down, ignoring interrupt !!!!!!!!\n", - card->devname); - return; - } - - bit_set((u_int8_t *)&card->in_isr, 0); - -/* write_cpld(card, LED_CONTROL_REG, 0x0F);*/ - - /* - * Disable all chip Interrupts (offset 0x040) - * -- "Transmit/Receive DMA Engine" interrupt disable - * -- "FiFo/Line Abort Error" interrupt disable - */ - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - - if (bit_test((u_int8_t *)®, SECURITY_STATUS_FLAG)) { - log(LOG_INFO, "%s: Critical: Chip Security Compromised!\n", - card->devname); - log(LOG_INFO, "%s: Disabling Driver!\n", - card->devname); - - port_set_state(card, WAN_DISCONNECTED); - disable_data_error_intr(card, CARD_DOWN); - goto isr_end; - } - - /* - * Note: If interrupts are received without pending flags, it usually - * indicates that the interrupt * is being shared. - */ - if (bit_test((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT)) { - if (bit_test((u_int8_t *)®, FRONT_END_INTR_FLAG)) { - front_end_interrupt(card, reg); - if (card->u.xilinx.state_change_exit_isr) { - card->u.xilinx.state_change_exit_isr = 0; - /* - * The state change occured, skip all - * other interrupts - */ - goto isr_end; - } - } - } - - /* - * Test Fifo Error Interrupt - * If set shutdown all interfaces and reconfigure - */ - if (bit_test((u_int8_t *)®, ERROR_INTR_ENABLE_BIT)) - if (bit_test((u_int8_t *)®, ERROR_INTR_FLAG)) - fifo_error_interrupt(card, reg); - - /* - * Checking for Interrupt source: - * 1. Receive DMA Engine - * 2. Transmit DMA Engine - * 3. Error conditions. - */ - if (bit_test((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT) && - bit_test((u_int8_t *)®, DMA_INTR_FLAG)) { - - /* Receive DMA Engine */ - sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, - &dma_rx_reg); - - dma_rx_reg &= card->u.xilinx.active_ch_map; - - if (dma_rx_reg == 0) - goto isr_rx; - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&dma_rx_reg, i) && - bit_test((u_int8_t *) - &card->u.xilinx.logic_ch_map, i)) { - sc = (xilinx_softc_t *) - card->u.xilinx.dev_to_ch_map[i]; - if (!sc) { - log(LOG_INFO, "%s: Error: No Dev for " - "Rx logical ch=%d\n", - card->devname, i); - continue; - } - - xilinx_dma_rx_complete(card, sc); - } - } -isr_rx: - - /* Transmit DMA Engine */ - sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, - &dma_tx_reg); - - dma_tx_reg &= card->u.xilinx.active_ch_map; - - if (dma_tx_reg == 0) - goto isr_tx; - - for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) { - if (bit_test((u_int8_t *)&dma_tx_reg, i) && - bit_test((u_int8_t *) - &card->u.xilinx.logic_ch_map, i)) { - sc = (xilinx_softc_t *) - card->u.xilinx.dev_to_ch_map[i]; - if (!sc) { - log(LOG_INFO, "%s: Error: No Dev for " - "Tx logical ch=%d\n", - card->devname, i); - continue; - } - - xilinx_dma_tx_complete(card, sc); - } - } - } - -isr_tx: - -isr_end: - -/* write_cpld(card, LED_CONTROL_REG, 0x0E); */ - - bit_clear((u_int8_t *)&card->in_isr, 0); - return; -} - - -/* - * TASK Functions and Triggers - */ - -/* - * port_set_state - * - * Set PORT state. - * - */ -static void -port_set_state(sdla_t *card, int state) -{ - wanpipe_common_t *common; - - if (card->state != state) { - switch (state) { - case WAN_CONNECTED: - log(LOG_INFO, "%s: Link connected!\n", card->devname); - aft_red_led_ctrl(card, AFT_LED_OFF); - aft_green_led_ctrl(card, AFT_LED_ON); - break; - - case WAN_CONNECTING: - log(LOG_INFO, "%s: Link connecting...\n", - card->devname); - aft_red_led_ctrl(card, AFT_LED_ON); - aft_green_led_ctrl(card, AFT_LED_OFF); - break; - - case WAN_DISCONNECTED: - log(LOG_INFO, "%s: Link disconnected!\n", - card->devname); - aft_red_led_ctrl(card, AFT_LED_ON); - aft_green_led_ctrl(card, AFT_LED_OFF); - break; - } - card->state = state; - LIST_FOREACH(common, &card->dev_head, next) { - struct ifnet *ifp = (struct ifnet *)&common->ifp; - if (ifp) - set_chan_state(card, ifp, state); - } - } -} - - -/* - * handle_front_end_state - */ - -static void -handle_front_end_state(void *card_id) -{ - sdla_t *card = (sdla_t *)card_id; - - if (card->front_end_status == FE_CONNECTED) { - enable_data_error_intr(card); - port_set_state(card, WAN_CONNECTED); - card->u.xilinx.state_change_exit_isr = 1; - } else { - port_set_state(card, WAN_CONNECTING); - disable_data_error_intr(card, LINK_DOWN); - card->u.xilinx.state_change_exit_isr = 1; - } -} - -static unsigned char -read_cpld(sdla_t *card, unsigned short cpld_off) -{ - u_int16_t org_off; - u_int8_t tmp; - - cpld_off &= ~BIT_DEV_ADDR_CLEAR; - cpld_off |= BIT_DEV_ADDR_CPLD; - - /* Save the current address. */ - sdla_bus_read_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, &org_off); - - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, cpld_off); - - sdla_bus_read_1(card->hw, XILINX_MCPU_INTERFACE, &tmp); - - /* Restore original address */ - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off); - - return (tmp); -} - -static unsigned char -write_cpld(sdla_t *card, unsigned short off, unsigned char data) -{ - u_int16_t org_off; - - off &= ~BIT_DEV_ADDR_CLEAR; - off |= BIT_DEV_ADDR_CPLD; - - /* Save the current original address */ - sdla_bus_read_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, &org_off); - - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off); - - /* This delay is required to avoid bridge optimization - * (combining two writes together)*/ - DELAY(5); - - sdla_bus_write_1(card->hw, XILINX_MCPU_INTERFACE, data); - - /* This delay is required to avoid bridge optimization - * (combining two writes together)*/ - DELAY(5); - - /* Restore the original address */ - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, org_off); - - return (0); -} - -static unsigned char -write_front_end_reg(void *card1, unsigned short off, unsigned char value) -{ - sdla_t *card = (sdla_t *)card1; - - off &= ~BIT_DEV_ADDR_CLEAR; - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off); - /* - * These delays are required to avoid bridge optimization - * (combining two writes together) - */ - DELAY(5); - sdla_bus_write_1(card->hw, XILINX_MCPU_INTERFACE, value); - DELAY(5); - - return (0); -} - - -/* - * Read TE1/56K Front end registers - */ -static unsigned char -read_front_end_reg(void *card1, unsigned short off) -{ - sdla_t* card = (sdla_t *)card1; - u_int8_t tmp; - - off &= ~BIT_DEV_ADDR_CLEAR; - sdla_bus_write_2(card->hw, XILINX_MCPU_INTERFACE_ADDR, off); - sdla_bus_read_1(card->hw, XILINX_MCPU_INTERFACE, &tmp); - DELAY(5); - - return (tmp); -} - - -/* - * Run only after the front end comes up from down state. - * - * Clean the DMA Tx/Rx pending interrupts. - * (Ignore since we will reconfigure - * all dma descriptors. DMA controler - * was already disabled on link down) - * - * For all channels clean Tx/Rx Fifo - * - * Enable DMA controler - * (This starts the fifo cleaning - * process) - * - * For all channels reprogram Tx/Rx DMA - * descriptors. - * - * Clean the Tx/Rx Error pending interrupts. - * (Since dma fifo's are now empty) - * - * Enable global DMA and Error interrutps. - * - */ - -static void -enable_data_error_intr(sdla_t *card) -{ - wanpipe_common_t *common; - struct ifnet *ifp; - u_int32_t reg; - - /* Clean Tx/Rx DMA interrupts */ - sdla_bus_read_4(card->hw, XILINX_DMA_RX_INTR_PENDING_REG, ®); - sdla_bus_read_4(card->hw, XILINX_DMA_TX_INTR_PENDING_REG, ®); - - /* For all channels clean Tx/Rx fifos */ - LIST_FOREACH(common, &card->dev_head, next) { - xilinx_softc_t *sc; - - ifp = (struct ifnet *)&common->ifp; - if (!ifp || !ifp->if_softc) - continue; - sc = ifp->if_softc; -#if 0 - if (!(ifp->if_flags & IFF_UP)) - continue; -#endif - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Init interface fifo no wait %s\n", - sc->if_name, __FUNCTION__); -#endif - xilinx_init_rx_dev_fifo(card, sc, WP_NO_WAIT); - xilinx_init_tx_dev_fifo(card, sc, WP_NO_WAIT); - } - - /* - * Enable DMA controler, in order to start the - * fifo cleaning - */ - sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®); - bit_set((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT); - sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg); - - /* For all channels clean Tx/Rx fifos */ - LIST_FOREACH(common, &card->dev_head, next) { - xilinx_softc_t *sc; - - ifp = (struct ifnet *)&common->ifp; - if (!ifp || ifp->if_softc == NULL) - continue; - sc = ifp->if_softc; -#if 0 - if (!(ifp->if_flags & IFF_UP)) - continue; -#endif - - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Init interface fifo %s\n", - sc->if_name, __FUNCTION__); -#endif - - xilinx_init_rx_dev_fifo(card, sc, WP_WAIT); - xilinx_init_tx_dev_fifo(card, sc, WP_WAIT); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Clearing Fifo and idle_flag %s\n", - card->devname, sc->if_name); -#endif - bit_clear((u_int8_t *)&sc->idle_start, 0); - } - - /* For all channels, reprogram Tx/Rx DMA descriptors. - * For Tx also make sure that the BUSY flag is clear - * and previoulsy Tx packet is deallocated */ - LIST_FOREACH(common, &card->dev_head, next) { - xilinx_softc_t *sc; - - ifp = (struct ifnet *)&common->ifp; - if (!ifp || !ifp->if_softc) - continue; - sc = ifp->if_softc; -#if 0 - if (!(ifp->if_flags & IFF_UP)) { - continue; - } -#endif - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Init interface %s\n", - sc->if_name, __FUNCTION__); -#endif - - if (sc->rx_dma_buf) { - aft_reload_rx_dma_buff(sc, sc->rx_dma_buf); - sc->rx_dma_buf = NULL; - } - - xilinx_dma_rx(card, sc); - - if (sc->tx_dma_addr && sc->tx_dma_len) { - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - } - - if (sc->tx_dma_mbuf) { - bus_dmamap_unload(sc->dmatag, sc->tx_dmamap); - m_freem(sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - } - - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - bit_clear((u_int8_t *)&sc->idle_start, 0); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Clearing Fifo and idle_flag %s\n", - card->devname, sc->if_name); -#endif - } - - /* - * Clean Tx/Rx Error interrupts, since fifos are now - * empty, and Tx fifo may generate an underrun which - * we want to ignore :) - */ - sdla_bus_read_4(card->hw, XILINX_HDLC_RX_INTR_PENDING_REG, ®); - sdla_bus_read_4(card->hw, XILINX_HDLC_TX_INTR_PENDING_REG, ®); - - /* Enable Global DMA and Error Interrupts */ - reg = 0; - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - bit_set((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT); - bit_set((u_int8_t *)®, ERROR_INTR_ENABLE_BIT); - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - return; -} - -static void -disable_data_error_intr(sdla_t *card, unsigned char event) -{ - u_int32_t reg; - - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - bit_clear((u_int8_t *)®, GLOBAL_INTR_ENABLE_BIT); - bit_clear((u_int8_t *)®, ERROR_INTR_ENABLE_BIT); - if (event == DEVICE_DOWN) - bit_clear((u_int8_t *)®, FRONT_END_INTR_ENABLE_BIT); - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, reg); - - sdla_bus_read_4(card->hw, XILINX_DMA_CONTROL_REG, ®); - bit_clear((u_int8_t *)®, DMA_ENGINE_ENABLE_BIT); - sdla_bus_write_4(card->hw, XILINX_DMA_CONTROL_REG, reg); - -} - -static void -xilinx_init_tx_dma_descr(sdla_t *card, xilinx_softc_t *sc) -{ - unsigned long dma_descr; - unsigned long reg = 0; - - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI; - sdla_bus_write_4(card->hw, dma_descr, reg); -} - - - -static void -xilinx_tx_fifo_under_recover(sdla_t *card, xilinx_softc_t *sc) -{ - struct ifnet *ifp = (struct ifnet *)&sc->common.ifp; - u_int32_t reg = 0; - unsigned long dma_descr; - -#ifdef DEBUG_ERR - log(LOG_INFO, "%s:%s: Tx Fifo Recovery \n", - card->devname, sc->if_name); -#endif - - /* Initialize Tx DMA descriptor: Stop DMA */ - dma_descr = (sc->logic_ch_num << 4) + XILINX_TxDMA_DESCRIPTOR_HI; - sdla_bus_write_4(card->hw, dma_descr, reg); - - /* Clean the TX FIFO */ - xilinx_init_tx_dev_fifo(card, sc, WP_WAIT); - if (sc->tx_dma_addr && sc->tx_dma_len) { - sc->tx_dma_addr = 0; - sc->tx_dma_len = 0; - } - - /* Requeue the current tx packet, for re-transmission */ - if (sc->tx_dma_mbuf) { - IF_PREPEND(&sc->wp_tx_pending_list, - (struct mbuf *)sc->tx_dma_mbuf); - sc->tx_dma_mbuf = NULL; - } - - /* - * Wake up the stack, because tx dma interrupt failed - */ - if (ifp) - ifp->if_oerrors++; - -#ifdef DEBUG_ERR - log(LOG_INFO, "%s:%s: Tx Fifo Recovery: Restarting Transmission \n", - card->devname, sc->if_name); -#endif - - /* Re-start transmission */ - bit_clear((u_int8_t *)&sc->dma_status, TX_BUSY); - if (!xilinx_dma_tx(card, sc)) { - /* If we was able to transmit and the interface is set - * to OACTIVE remove this flag and let kernel try to - * transmit. - */ - if (ifp->if_flags & IFF_OACTIVE) - ifp->if_flags &= ~IFF_OACTIVE; - } - return; -} - -static int -xilinx_write_ctrl_hdlc(sdla_t *card, u_int32_t timeslot, - u_int8_t reg_off, u_int32_t data) -{ - u_int32_t reg; - u_int32_t ts_orig = timeslot; - unsigned long timeout = ticks; - - if (timeslot == 0) - timeslot = card->u.xilinx.num_of_time_slots - 2; - else if (timeslot == 1) - timeslot = card->u.xilinx.num_of_time_slots - 1; - else - timeslot -= 2; - - timeslot = timeslot << XILINX_CURRENT_TIMESLOT_SHIFT; - timeslot &= XILINX_CURRENT_TIMESLOT_MASK; - - for (;;) { - sdla_bus_read_4(card->hw, XILINX_TIMESLOT_HDLC_CHAN_REG, ®); - reg &= XILINX_CURRENT_TIMESLOT_MASK; - - if (reg == timeslot) { - sdla_bus_write_4(card->hw, reg_off, data); - return (0); - } - - if ((ticks-timeout) > 1) { - log(LOG_INFO, "%s: Error: Access to timeslot %d " - "timed out!\n", card->devname, ts_orig); - return (EIO); - } - } - - return (EIO); -} - -static int -set_chan_state(sdla_t *card, struct ifnet *ifp, int state) -{ - xilinx_softc_t *sc = ifp->if_softc; - - if (sc == NULL) - return (0); - - if (state == WAN_CONNECTED) { -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Setting idle_start to 0\n", sc->if_name); -#endif - bit_clear((u_int8_t *)&sc->idle_start, 0); - sc->common.ifp.pp_up(&sc->common.ifp); - } else if (state == WAN_DISCONNECTED) - sc->common.ifp.pp_down(&sc->common.ifp); - - return (0); -} - - -static char fifo_size_vector[] = {1, 2, 4, 8, 16, 32}; -static char fifo_code_vector[] = {0, 1, 3, 7, 0xF, 0x1F}; - -static int -request_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc) -{ - unsigned char req_fifo_size, fifo_size; - int i; - - /* - * Calculate the optimal fifo size based - * on the number of time slots requested - */ - - if (IS_T1(&card->fe_te.te_cfg)) { - if (sc->num_of_time_slots == NUM_OF_T1_CHANNELS) - req_fifo_size = 32; - else if (sc->num_of_time_slots == 1) - req_fifo_size = 1; - else if (sc->num_of_time_slots == 2 || - sc->num_of_time_slots == 3) - req_fifo_size = 2; - else if (sc->num_of_time_slots >= 4 && - sc->num_of_time_slots <= 7) - req_fifo_size = 4; - else if (sc->num_of_time_slots >= 8 && - sc->num_of_time_slots <= 15) - req_fifo_size = 8; - else if (sc->num_of_time_slots >= 16 && - sc->num_of_time_slots <= 23) - req_fifo_size = 16; - else { - log(LOG_INFO, "%s: Invalid number of timeslots %d\n", - card->devname, sc->num_of_time_slots); - return (EINVAL); - } - } else { - if (sc->num_of_time_slots == (NUM_OF_E1_CHANNELS-1)) - req_fifo_size = 32; - else if (sc->num_of_time_slots == 1) - req_fifo_size = 1; - else if (sc->num_of_time_slots == 2 || - sc->num_of_time_slots == 3) - req_fifo_size = 2; - else if (sc->num_of_time_slots >= 4 && - sc->num_of_time_slots <= 7) - req_fifo_size = 4; - else if (sc->num_of_time_slots >= 8 && - sc->num_of_time_slots <= 15) - req_fifo_size = 8; - else if (sc->num_of_time_slots >= 16 && - sc->num_of_time_slots <= 31) - req_fifo_size = 16; - else { - log(LOG_INFO, - "%s:%s: Invalid number of timeslots %d\n", - card->devname, sc->if_name, sc->num_of_time_slots); - return (EINVAL); - } - } - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s:%s: Optimal Fifo Size =%d Timeslots=%d \n", - card->devname, sc->if_name, req_fifo_size, sc->num_of_time_slots); -#endif - fifo_size = map_fifo_baddr_and_size(card, req_fifo_size, - &sc->fifo_base_addr); - - if (fifo_size == 0 || sc->fifo_base_addr == 31) { - log(LOG_INFO, "%s:%s: Error: Failed to obtain fifo size %d " - "or addr %d\n", card->devname, sc->if_name, fifo_size, - sc->fifo_base_addr); - return (EINVAL); - } - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s:%s: Optimal Fifo Size =%d TS=%d New Fifo Size=%d\n", - card->devname, sc->if_name, req_fifo_size, sc->num_of_time_slots, - fifo_size); -#endif - - for (i = 0; i < sizeof(fifo_size_vector); i++) { - if (fifo_size_vector[i] == fifo_size) { - sc->fifo_size_code = fifo_code_vector[i]; - break; - } - } - - if (fifo_size != req_fifo_size) - log(LOG_INFO, "%s:%s: WARN: Failed to obtain the req " - "fifo %d got %d\n", card->devname, sc->if_name, - req_fifo_size, fifo_size); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: %s:Fifo Size=%d TS=%d Fifo Code=%d Addr=%d\n", - card->devname, sc->if_name, fifo_size, sc->num_of_time_slots, - sc->fifo_size_code, sc->fifo_base_addr); -#endif - sc->fifo_size = fifo_size; - - return (0); -} - - -static int -map_fifo_baddr_and_size(sdla_t *card, unsigned char fifo_size, - unsigned char *addr) -{ - u_int32_t reg = 0; - int i; - - for (i = 0; i < fifo_size; i++) - bit_set((u_int8_t *)®, i); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Trying to MAP 0x%X to 0x%lX\n", - card->devname, reg, card->u.xilinx.fifo_addr_map); -#endif - for (i = 0; i < 32; i += fifo_size) { - if (card->u.xilinx.fifo_addr_map & (reg << i)) - continue; - card->u.xilinx.fifo_addr_map |= reg << i; - *addr = i; - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Card fifo Map 0x%lX Addr =%d\n", - card->devname, card->u.xilinx.fifo_addr_map, i); -#endif - return (fifo_size); - } - - if (fifo_size == 1) - return (0); - - fifo_size = fifo_size >> 1; - - return map_fifo_baddr_and_size(card, fifo_size, addr); -} - - -static int -free_fifo_baddr_and_size(sdla_t *card, xilinx_softc_t *sc) -{ - u_int32_t reg = 0; - int i; - - for (i = 0; i < sc->fifo_size; i++) - bit_set((u_int8_t *)®, i); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: Unmapping 0x%X from 0x%lX\n", card->devname, - reg << sc->fifo_base_addr, card->u.xilinx.fifo_addr_map); -#endif - card->u.xilinx.fifo_addr_map &= ~(reg << sc->fifo_base_addr); - -#ifdef DEBUG_INIT - log(LOG_INFO, "%s: New Map is 0x%lX\n", - card->devname, card->u.xilinx.fifo_addr_map); -#endif - - sc->fifo_size = 0; - sc->fifo_base_addr = 0; - - return (0); -} - -static void -aft_red_led_ctrl(sdla_t *card, int mode) -{ - unsigned int led; - - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, &led); - - if (mode == AFT_LED_ON) - bit_clear((u_int8_t *)&led, XILINX_RED_LED); - else if (mode == AFT_LED_OFF) - bit_set((u_int8_t *)&led, XILINX_RED_LED); - else { - if (bit_test((u_int8_t *)&led, XILINX_RED_LED)) - bit_clear((u_int8_t *)&led, XILINX_RED_LED); - else - bit_set((u_int8_t *)&led, XILINX_RED_LED); - } - - sdla_bus_write_4(card->hw, XILINX_CHIP_CFG_REG, led); -} - -static void -aft_led_timer(void *data) -{ - sdla_t *card=(sdla_t *)data; - unsigned int te_alarm; - - if (bit_test((u_int8_t *)&card->critical, CARD_DOWN)) - return; - - if (IS_TE1(&card->fe_te.te_cfg)) { - int s = splnet(); - - te_alarm = sdla_te_alarm(card, 0); - te_alarm &= ~(BIT_OOSMF_ALARM|BIT_OOCMF_ALARM); - - if (!te_alarm) { - if (card->state == WAN_CONNECTED) { - aft_red_led_ctrl(card, AFT_LED_OFF); - aft_green_led_ctrl(card, AFT_LED_ON); - } else { - aft_red_led_ctrl(card, AFT_LED_OFF); - aft_green_led_ctrl(card, AFT_LED_TOGGLE); - } - - } else if (te_alarm & (BIT_RED_ALARM|BIT_LOS_ALARM)) { - /* Red or LOS Alarm solid RED */ - aft_red_led_ctrl(card, AFT_LED_ON); - aft_green_led_ctrl(card, AFT_LED_OFF); - } else if (te_alarm & BIT_OOF_ALARM) { - /* OOF Alarm flashing RED */ - aft_red_led_ctrl(card, AFT_LED_TOGGLE); - aft_green_led_ctrl(card, AFT_LED_OFF); - } else if (te_alarm & BIT_AIS_ALARM) { - /* AIS - Blue Alarm flasing RED and GREEN */ - aft_red_led_ctrl(card, AFT_LED_TOGGLE); - aft_green_led_ctrl(card, AFT_LED_TOGGLE); - } else if (te_alarm & BIT_YEL_ALARM) { - /* Yellow Alarm */ - aft_red_led_ctrl(card, AFT_LED_ON); - aft_green_led_ctrl(card, AFT_LED_ON); - } else { - - /* Default case shouldn't happen */ - log(LOG_INFO, "%s: Unknown Alarm 0x%X\n", - card->devname, te_alarm); - aft_red_led_ctrl(card, AFT_LED_ON); - aft_green_led_ctrl(card, AFT_LED_ON); - } - - splx(s); - timeout_add_sec(&card->u.xilinx.led_timer, 1); - } -} - - -int -aft_core_ready(sdla_t *card) -{ - u_int32_t reg; - volatile unsigned char cnt = 0; - - for (;;) { - sdla_bus_read_4(card->hw, XILINX_CHIP_CFG_REG, ®); - if (!bit_test((u_int8_t *)®, HDLC_CORE_READY_FLAG_BIT)) { - /* The HDLC Core is not ready! we have - ** an error. */ - if (++cnt > 5) - return (EINVAL); - else - DELAY(500); - /* WARNING: we cannot do this while in - * critical area */ - } else - return (0); - } - - return (EINVAL); -} diff --git a/sys/dev/pci/if_san_xilinx.h b/sys/dev/pci/if_san_xilinx.h deleted file mode 100644 index bc498952774..00000000000 --- a/sys/dev/pci/if_san_xilinx.h +++ /dev/null @@ -1,443 +0,0 @@ -/* $OpenBSD: if_san_xilinx.h,v 1.4 2004/07/16 15:11:45 alex Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Nenad Corbic for SAN. - * The code is derived from permitted modifications to software created - * by Alex Feldman (al.feldman@sangoma.com). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IF_SAN_XILINX_H -#define __IF_SAN_XILINX_H - -#define XILINX_CHIP_CFG_REG 0x40 - -#define XILINX_MCPU_INTERFACE 0x44 -#define XILINX_MCPU_INTERFACE_ADDR 0x46 - -#define XILINX_GLOBAL_INTER_MASK 0x4C - - -#define XILINX_HDLC_TX_INTR_PENDING_REG 0x50 -#define XILINX_HDLC_RX_INTR_PENDING_REG 0x54 - -enum { - WP_FIFO_ERROR_BIT, - WP_CRC_ERROR_BIT, - WP_ABORT_ERROR_BIT, -}; - -#define WP_MAX_FIFO_FRAMES 7 - -#define XILINX_DMA_TX_INTR_PENDING_REG 0x58 -#define XILINX_DMA_RX_INTR_PENDING_REG 0x5C - -#define XILINX_TIMESLOT_HDLC_CHAN_REG 0x60 - -#define AFT_T3_RXTX_ADDR_SELECT_REG 0x60 - -#define XILINX_CURRENT_TIMESLOT_MASK 0x00001F00 -#define XILINX_CURRENT_TIMESLOT_SHIFT 8 - -#define XILINX_HDLC_CONTROL_REG 0x64 -#define XILINX_HDLC_ADDR_REG 0x68 - -#define XILINX_CONTROL_RAM_ACCESS_BUF 0x6C - - - -#define XILINX_DMA_CONTROL_REG 0x70 -#define XILINX_DMA_TX_STATUS_REG 0x74 -#define AFT_TE3_TX_WDT_CTRL_REG 0x74 -#define XILINX_DMA_RX_STATUS_REG 0x78 -#define AFT_TE3_RX_WDT_CTRL_REG 0x78 -#define XILINX_DMA_DATA_REG 0x7C - -#define AFT_TE3_CRNT_DMA_DESC_ADDR_REG 0x80 - -#define XILINX_TxDMA_DESCRIPTOR_LO 0x100 -#define XILINX_TxDMA_DESCRIPTOR_HI 0x104 -#define XILINX_RxDMA_DESCRIPTOR_LO 0x108 -#define XILINX_RxDMA_DESCRIPTOR_HI 0x10C - - -#define INTERFACE_TYPE_T1_E1_BIT 0 -#define INTERFACE_TYPE_T3_E3_BIT 0 - -#define XILINX_RED_LED 1 -#define AFT_T3_HDLC_TRANS_MODE 1 -#define FRONT_END_FRAME_FLAG_ENABLE_BIT 2 -#define AFT_T3_CLOCK_MODE 2 -#define SIGNALLING_ENABLE_BIT 3 -#define FRONT_END_RESET_BIT 4 -#define CHIP_RESET_BIT 5 -#define HDLC_CORE_RESET_BIT 6 -#define HDLC_CORE_READY_FLAG_BIT 7 -#define GLOBAL_INTR_ENABLE_BIT 8 -#define ERROR_INTR_ENABLE_BIT 9 -#define FRONT_END_INTR_ENABLE_BIT 10 - -#define CHIP_ERROR_MASK 0x00FF0000 - -#define AFT_TE3_TX_WDT_INTR_PND 26 -#define AFT_TE3_RX_WDT_INTR_PND 27 - -#define FRONT_END_INTR_FLAG 28 -#define SECURITY_STATUS_FLAG 29 -#define ERROR_INTR_FLAG 30 -#define DMA_INTR_FLAG 31 - -#define XILINX_GLOBAL_INTER_STATUS 0xD0000000 - -#define TIMESLOT_BIT_SHIFT 16 -#define TIMESLOT_BIT_MASK 0x001F0000 -#define HDLC_LOGIC_CH_BIT_MASK 0x0000001F - -#define HDLC_LCH_TIMESLOT_MASK 0x001F001F - - -#define HDLC_RX_CHAN_ENABLE_BIT 0 -#define HDLC_RX_FRAME_DATA_BIT 1 -#define HDLC_RC_CHAN_ACTIVE_BIT 2 -#define HDLC_RX_FRAME_ERROR_BIT 3 -#define HDLC_RX_FRAME_ABORT_BIT 4 -#define HDLC_RX_PROT_DISABLE_BIT 16 -#define HDLC_RX_ADDR_RECOGN_DIS_BIT 17 -#define HDLC_RX_ADDR_FIELD_DISC_BIT 18 -#define HDLC_RX_ADDR_SIZE_BIT 19 -#define HDLC_RX_BRD_ADDR_MATCH_BIT 20 -#define HDLC_RX_FCS_SIZE_BIT 21 -#define HDLC_CORE_RX_IDLE_LINE_BIT 22 -#define HDLC_CODE_RX_ABORT_LINE_BIT 23 -#define HDLC_TX_CHAN_ENABLE_BIT 24 -#define HDLC_TX_PROT_DISABLE_BIT 25 -#define HDLC_TX_ADDR_INSERTION_BIT 26 -#define HDLC_TX_ADDR_SIZE_BIT 27 -#define HDLC_TX_FCS_SIZE_BIT 28 -#define HDLC_TX_FRAME_ABORT_BIT 29 -#define HDLC_TX_STOP_TX_ON_ABORT_BIT 30 -#define HDLC_TX_CHANNEL_ACTIVE_BIT 31 - - -#define CONTROL_RAM_DATA_MASK 0x0000001F - - -#define HDLC_FIFO_BASE_ADDR_SHIFT 16 -#define HDLC_FIFO_BASE_ADDR_MASK 0x1F - -#define HDLC_FIFO_SIZE_SHIFT 8 -#define HDLC_FIFO_SIZE_MASK 0x1F - -#define HDLC_FREE_LOGIC_CH 31 -#define TRANSPARENT_MODE_BIT 31 - - -#define DMA_SIZE_BIT_SHIFT 0 -#define DMA_FIFO_HI_MARK_BIT_SHIFT 4 -#define DMA_FIFO_LO_MARK_BIT_SHIFT 8 -#define DMA_FIFO_T3_MARK_BIT_SHIFT 8 - -#define DMA_ACTIVE_CHANNEL_BIT_SHIFT 16 -#define DMA_ACTIVE_CHANNEL_BIT_MASK 0xFFE0FFFF - -#define DMA_ENGINE_ENABLE_BIT 31 - -#define DMA_CHAIN_TE3_MASK 0x0000000F - -#define TxDMA_LO_PC_ADDR_PTR_BIT_MASK 0xFFFFFFFC -#define TxDMA_LO_ALIGNMENT_BIT_MASK 0x00000003 -#define TxDMA_HI_DMA_DATA_LENGTH_MASK 0x000007FF - -#define TxDMA_HI_DMA_PCI_ERROR_MASK 0x00007800 -#define TxDMA_HI_DMA_PCI_ERROR_M_ABRT 0x00000800 -#define TxDMA_HI_DMA_PCI_ERROR_T_ABRT 0x00001000 -#define TxDMA_HI_DMA_PCI_ERROR_DS_TOUT 0x00002000 -#define TxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT 0x00004000 - - -#define INIT_DMA_FIFO_CMD_BIT 28 -#define TxDMA_HI_DMA_FRAME_START_BIT 30 -#define TxDMA_HI_DMA_FRAME_END_BIT 29 -#define TxDMA_HI_DMA_GO_READY_BIT 31 -#define DMA_FIFO_BASE_ADDR_SHIFT 20 -#define DMA_FIFO_BASE_ADDR_MASK 0x1F -#define DMA_FIFO_SIZE_SHIFT 15 -#define DMA_FIFO_SIZE_MASK 0x1F - -#define DMA_FIFO_PARAM_CLEAR_MASK 0xFE007FFF - -#define FIFO_32B 0x00 -#define FIFO_64B 0x01 -#define FIFO_128B 0x03 -#define FIFO_256B 0x07 -#define FIFO_512B 0x0F -#define FIFO_1024B 0x1F - - -#define RxDMA_LO_PC_ADDR_PTR_BIT_MASK 0xFFFFFFFC -#define RxDMA_LO_ALIGNMENT_BIT_MASK 0x00000003 -#define RxDMA_HI_DMA_DATA_LENGTH_MASK 0x000007FF - -#define RxDMA_HI_DMA_PCI_ERROR_MASK 0x00007800 -#define RxDMA_HI_DMA_PCI_ERROR_M_ABRT 0x00000800 -#define RxDMA_HI_DMA_PCI_ERROR_T_ABRT 0x00001000 -#define RxDMA_HI_DMA_PCI_ERROR_DS_TOUT 0x00002000 -#define RxDMA_HI_DMA_PCI_ERROR_RETRY_TOUT 0x00004000 - - -#define RxDMA_HI_DMA_COMMAND_BIT_SHIFT 28 -#define RxDMA_HI_DMA_FRAME_START_BIT 30 -#define RxDMA_HI_DMA_CRC_ERROR_BIT 25 -#define RxDMA_HI_DMA_FRAME_ABORT_BIT 26 -#define RxDMA_HI_DMA_FRAME_END_BIT 29 -#define RxDMA_HI_DMA_GO_READY_BIT 31 - -#define DMA_HI_TE3_INTR_DISABLE_BIT 27 -#define DMA_HI_TE3_NOT_LAST_FRAME_BIT 24 - -#define AFT_TE3_CRNT_TX_DMA_MASK 0x0000000F -#define AFT_TE3_CRNT_RX_DMA_MASK 0x000000F0 -#define AFT_TE3_CRNT_RX_DMA_SHIFT 4 - -typedef struct xilinx_config -{ - unsigned long xilinx_chip_cfg_reg; - unsigned long xilinx_dma_control_reg; -} xilinx_config_t; - - -#define XILINX_DMA_SIZE 10 -#define XILINX_DMA_FIFO_UP 8 -#define XILINX_DMA_FIFO_LO 8 -#define AFT_T3_DMA_FIFO_MARK 8 -#define XILINX_DEFLT_ACTIVE_CH 0 - -#define MAX_XILINX_TX_DMA_SIZE 0xFFFF - -#define MIN_WP_PRI_MTU 128 -#define DEFAULT_WP_PRI_MTU 1500 -#define MAX_WP_PRI_MTU 8188 - - -#define MAX_DATA_SIZE 2000 -struct sdla_hdlc_api { - unsigned int cmd; - unsigned short len; - unsigned char bar; - unsigned short offset; - unsigned char data[MAX_DATA_SIZE]; -}; - -#pragma pack(1) -typedef struct { - unsigned char error_flag; - unsigned short time_stamp; - unsigned char reserved[13]; -} api_rx_hdr_t; - -typedef struct { - api_rx_hdr_t api_rx_hdr; - unsigned char data[1]; -} api_rx_element_t; - -typedef struct { - unsigned char attr; - unsigned char misc_Tx_bits; - unsigned char reserved[14]; -} api_tx_hdr_t; - -typedef struct { - api_tx_hdr_t api_tx_hdr; - unsigned char data[1]; -} api_tx_element_t; -#pragma pack() - -#undef wan_udphdr_data -#define wan_udphdr_data wan_udphdr_u.aft.data - - - -#define PMC_CONTROL_REG 0x00 - - -#define PMC_RESET_BIT 0 -#define PMC_CLOCK_SELECT 1 - -#define LED_CONTROL_REG 0x01 - -#define JP8_VALUE 0x02 -#define JP7_VALUE 0x01 -#define SW0_VALUE 0x04 -#define SW1_VALUE 0x08 - - -#define SECURITY_CPLD_REG 0x09 - -#define SECURITY_CPLD_MASK 0x03 -#define SECURITY_CPLD_SHIFT 0x02 - -#define SECURITY_1LINE_UNCH 0x00 -#define SECURITY_1LINE_CH 0x01 -#define SECURITY_2LINE_UNCH 0x02 -#define SECURITY_2LINE_CH 0x03 - - - -#define WRITE_DEF_SECTOR_DSBL 0x01 -#define FRONT_END_TYPE_MASK 0x38 - -#define BIT_DEV_ADDR_CLEAR 0x600 -#define BIT_DEV_ADDR_CPLD 0x200 - -#define MEMORY_TYPE_SRAM 0x00 -#define MEMORY_TYPE_FLASH 0x01 -#define MASK_MEMORY_TYPE_SRAM 0x10 -#define MASK_MEMORY_TYPE_FLASH 0x20 - -#define BIT_A18_SECTOR_SA4_SA7 0x20 -#define USER_SECTOR_START_ADDR 0x40000 - -#define MAX_TRACE_QUEUE 100 - -#define TX_DMA_BUF_INIT 0 - -#define MAX_TRACE_BUFFER (MAX_LGTH_UDP_MGNT_PKT - \ - sizeof(iphdr_t) - \ - sizeof(udphdr_t) - \ - sizeof(wan_mgmt_t) - \ - sizeof(wan_trace_info_t) - \ - sizeof(wan_cmd_t)) - -enum { - ROUTER_UP_TIME = 0x50, - ENABLE_TRACING, - DISABLE_TRACING, - GET_TRACE_INFO, - READ_CODE_VERSION, - FLUSH_OPERATIONAL_STATS, - OPERATIONAL_STATS, - READ_OPERATIONAL_STATS, - READ_CONFIGURATION, - COMMS_ERROR_STATS_STRUCT, - AFT_LINK_STATUS -}; - -#define UDPMGMT_SIGNATURE "AFTPIPEA" - - -typedef struct { - unsigned char flag; - unsigned short length; - unsigned char rsrv0[2]; - unsigned char attr; - unsigned short tmstamp; - unsigned char rsrv1[4]; - unsigned long offset; -} aft_trc_el_t; - - -typedef struct wp_rx_element -{ - unsigned long dma_addr; - unsigned int reg; - unsigned int align; - unsigned char pkt_error; -}wp_rx_element_t; - - -#if defined(_KERNEL) - -static __inline unsigned short xilinx_valid_mtu(unsigned short mtu) -{ - if (mtu <= 128) { - return 128; - } else if (mtu <= 256) { - return 256; - } else if (mtu <= 512) { - return 512; - } else if (mtu <= 1024) { - return 1024; - } else if (mtu <= 2048) { - return 2048; - } else if (mtu <= 4096) { - return 4096; - } else if (mtu <= 8188) { - return 8188; - } else { - return 0; - } -} - -static __inline unsigned short xilinx_dma_buf_bits(unsigned short dma_bufs) -{ - if (dma_bufs < 2) { - return 0; - } else if (dma_bufs < 3) { - return 1; - } else if (dma_bufs < 5) { - return 2; - } else if (dma_bufs < 9) { - return 3; - } else if (dma_bufs < 17) { - return 4; - } else { - return 0; - } -} - -#define AFT_TX_TIMEOUT 25 -#define AFT_RX_TIMEOUT 10 -#define AFT_MAX_WTD_TIMEOUT 250 - -static __inline void aft_reset_rx_watchdog(sdla_t *card) -{ - sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,0); -} - -static __inline void aft_enable_rx_watchdog(sdla_t *card, unsigned char timeout) -{ - aft_reset_rx_watchdog(card); - sdla_bus_write_4(card->hw,AFT_TE3_RX_WDT_CTRL_REG,timeout); -} - -static __inline void aft_reset_tx_watchdog(sdla_t *card) -{ - sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,0); -} - -static __inline void aft_enable_tx_watchdog(sdla_t *card, unsigned char timeout) -{ - aft_reset_tx_watchdog(card); - sdla_bus_write_4(card->hw,AFT_TE3_TX_WDT_CTRL_REG,timeout); -} - -#endif - -#endif diff --git a/sys/dev/pci/if_sandrv.c b/sys/dev/pci/if_sandrv.c deleted file mode 100644 index 520b54ee5bc..00000000000 --- a/sys/dev/pci/if_sandrv.c +++ /dev/null @@ -1,1491 +0,0 @@ -/* $OpenBSD: if_sandrv.c,v 1.16 2014/07/12 18:48:52 tedu Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define __SDLA_HW_LEVEL -#define __SDLADRV__ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define EXEC_DELAY 20 /* shared memory access delay, mks */ -#define EXEC_TIMEOUT (hz*2) -#define MAX_NLOOPS (EXEC_DELAY*2000) - /* timeout used if jiffies are stopped - ** EXEC_DELAY=20 - ** EXEC_TIMEOUT=EXEC_DELAY*2000 = 40000 - ** 40000 ~= 80 jiffies = EXEC_TIMEOUT */ - -#define EXEC_HZ_DIVISOR 8/10 - /* We don't want to wait a full second on sdla_exec - ** timeout, thus use HZ * EXEC_HZ_DIVISOR to get - ** the number of jiffies we would like to wait */ - -#define IS_SUPPORTED_ADAPTER(hw) ((hw)->type == SDLA_AFT) - -#define SDLA_CTYPE_NAME(type) \ - ((type) == SDLA_AFT) ? "AFT" : "Unknown" - -#define IS_AFT(hw) (hw->type == SDLA_AFT) - -/* Definitions for identifying and finding S514 PCI adapters */ -#define V3_VENDOR_ID 0x11B0 /* V3 vendor ID number */ -#define V3_DEVICE_ID 0x0002 /* V3 device ID number */ -#define SANGOMA_SUBSYS_VENDOR 0x4753 /* ID for Sangoma */ - -/* Definition for identifying and finding XILINX PCI adapters */ -#define SANGOMA_PCI_VENDOR 0x1923 /* Old value -> 0x11B0 */ -#define SANGOMA_PCI_VENDOR_OLD 0x10EE /* Old value -> 0x11B0 */ -#define SANGOMA_PCI_DEVICE 0x0300 /* Old value -> 0x0200 */ - -#define A101_1TE1_SUBSYS_VENDOR 0xA010 /* A101 with T1/E1 1 line */ -#define A101_2TE1_SUBSYS_VENDOR 0xA011 /* A101 with T1/E1 2 lines */ -#define A105_T3_SUBSYS_VENDOR 0xA020 /* A102 with T3 */ - -/* Read PCI SUBVENDOR ID */ -#define PCI_SUBVENDOR_MASK 0xFFFF -#define PCI_SUBVENDOR(pa) (pci_conf_read(pa->pa_pc, pa->pa_tag, \ - PCI_SUBSYS_ID_REG) & PCI_SUBVENDOR_MASK) -#define PCI_DEVICE_MASK 0xFFFF0000 -#define PCI_DEVICE(id) ((id & PCI_DEVICE_MASK ) >> 16) - -/* Status values */ -#define SDLA_MEM_RESERVED 0x0001 -#define SDLA_MEM_MAPPED 0x0002 -#define SDLA_IO_MAPPED 0x0004 -#define SDLA_PCI_ENABLE 0x0008 - -struct san_softc { - struct device dev; - struct pci_attach_args pa; -}; - -typedef struct sdla_hw_probe { - int used; - unsigned char hw_info[100]; - LIST_ENTRY(sdla_hw_probe) next; -} sdla_hw_probe_t; - -/* - * This structure keeps common parameters per physical card. - */ -typedef struct sdlahw_card { - int used; - unsigned int type; /* S50x/S514/ADSL/XILINX */ - unsigned int atype; /* SubVendor ID */ - unsigned char core_id; /* SubSystem ID [0..7] */ - unsigned char core_rev; /* SubSystem ID [8..15] */ - unsigned char pci_extra_ver; - unsigned int slot_no; - unsigned int bus_no; - bus_space_tag_t memt; - struct pci_attach_args pa; /* PCI config header info */ - pci_intr_handle_t ih; - LIST_ENTRY(sdlahw_card) next; -} sdlahw_card_t; - -/* - * Adapter hardware configuration. Pointer to this structure is passed to all - * APIs. - */ -typedef struct sdlahw { - int used; - unsigned magic; - char devname[20]; - u_int16_t status; - int irq; /* interrupt request level */ - unsigned int cpu_no; /* PCI CPU Number */ - char auto_pci_cfg; /* Auto PCI configuration */ - bus_addr_t mem_base_addr; - bus_space_handle_t dpmbase; /* dual-port memory base */ - unsigned dpmsize; /* dual-port memory size */ - unsigned long memory; /* memory size */ - - unsigned reserved[5]; - unsigned char hw_info[100]; - - u_int16_t configured; - void *arg; /* card structure */ - sdla_hw_probe_t *hwprobe; - sdlahw_card_t *hwcard; - LIST_ENTRY(sdlahw) next; -} sdlahw_t; - -/* Entry Point for Low-Level function */ -int sdladrv_init(void); -int sdladrv_exit(void); - -static int sdla_pci_probe(int, struct pci_attach_args *); - -/* PCI bus interface function */ -static int sdla_pci_write_config_word(void *, int, u_int16_t); -static int sdla_pci_write_config_dword(void *, int, u_int32_t); -static int sdla_pci_read_config_byte(void *, int, u_int8_t *); -static int sdla_pci_read_config_word(void *, int, u_int16_t *); -static int sdla_pci_read_config_dword(void *, int, u_int32_t *); - -static int sdla_detect (sdlahw_t *); -static int sdla_detect_aft(sdlahw_t *); -static int sdla_exec(sdlahw_t *, unsigned long); -static void sdla_peek_by_4(sdlahw_t *, unsigned long, u_int8_t *, unsigned int); -static void sdla_poke_by_4(sdlahw_t *, unsigned long, u_int8_t *, unsigned int); - -static sdlahw_card_t* sdla_card_register(u_int16_t, int, int); -#if 0 -static int sdla_card_unregister (unsigned char, int, int, int); -#endif -static sdlahw_card_t* sdla_card_search(u_int16_t, int, int); - -static sdlahw_t* sdla_hw_register(sdlahw_card_t *, int, int, void *); -#if 0 -static int sdla_hw_unregister(sdlahw_card_t*, int); -#endif -static sdlahw_t* sdla_hw_search(u_int16_t, int, int, int); - -static sdlahw_t* sdla_aft_hw_select (sdlahw_card_t *, int, int, - struct pci_attach_args *); -static void sdla_save_hw_probe (sdlahw_t*, int); - -/* SDLA PCI device relative entry point */ -int san_match(struct device *, void *, void *); -void san_attach(struct device *, struct device *, void *); - - -struct cfdriver san_cd = { - NULL, "san", DV_IFNET -}; - -struct cfattach san_ca = { - sizeof(struct san_softc), san_match, san_attach -}; - -extern int ticks; - -/* SDLA ISA/PCI varibles */ -static int Sangoma_cards_no = 0; -static int Sangoma_devices_no = 0; -static int Sangoma_PCI_cards_no = 0; - -/* private data */ -char *san_drvname = "san"; - -/* Array of already initialized PCI slots */ -static int pci_slot_ar[MAX_S514_CARDS]; - -LIST_HEAD(, sdlahw_card) sdlahw_card_head = - LIST_HEAD_INITIALIZER(sdlahw_card_head); -LIST_HEAD(, sdlahw) sdlahw_head = - LIST_HEAD_INITIALIZER(sdlahw_head); -LIST_HEAD(, sdla_hw_probe) sdlahw_probe_head = - LIST_HEAD_INITIALIZER(sdlahw_probe_head); -static sdla_hw_type_cnt_t sdla_adapter_cnt; - - - -/* - * PCI Device Driver Entry Points - */ -int -san_match(struct device *parent, void *match, void *aux) -{ - struct pci_attach_args* pa = aux; - u_int16_t vendor_id = PCI_VENDOR(pa->pa_id); - u_int16_t device_id = PCI_DEVICE(pa->pa_id); - - if ((vendor_id == SANGOMA_PCI_VENDOR || - vendor_id == SANGOMA_PCI_VENDOR_OLD) && - device_id == SANGOMA_PCI_DEVICE) { - return (1); - } - return (0); -} - -#define PCI_CBIO 0x10 -void -san_attach(struct device *parent, struct device *self, void *aux) -{ - struct pci_attach_args* pa = aux; - u_int16_t vendor_id = PCI_VENDOR(pa->pa_id); - u_int16_t subvendor_id = PCI_SUBVENDOR(pa); - int atype = 0x00; - - atype = PCI_PRODUCT(pci_conf_read(pa->pa_pc, pa->pa_tag, - PCI_SUBSYS_ID_REG)); - switch (vendor_id) { - case SANGOMA_PCI_VENDOR_OLD: - case SANGOMA_PCI_VENDOR: - switch (subvendor_id) { - case A101_1TE1_SUBSYS_VENDOR: - atype = A101_ADPTR_1TE1; - break; - case A101_2TE1_SUBSYS_VENDOR: - atype = A101_ADPTR_2TE1; - break; - default: - return; - } - break; - default: - return; - } - - if (sdla_pci_probe(atype, pa)) { - printf(": PCI probe FAILED!\n"); - return; - } - -#ifdef DEBUG - switch (PCI_VENDOR(pa->pa_id)) { - case V3_VENDOR_ID: - switch (atype) { - case S5141_ADPTR_1_CPU_SERIAL: - log(LOG_INFO, "%s: Sangoma S5141/FT1 (Single CPU) " - "adapter\n", self->dv_xname); - break; - case S5142_ADPTR_2_CPU_SERIAL: - log(LOG_INFO, "%s: Sangoma S5142 (Dual CPU) adapter\n", - self->dv_xname); - break; - case S5143_ADPTR_1_CPU_FT1: - log(LOG_INFO, "%s: Sangoma S5143 (Single CPU) " - "FT1 adapter\n", self->dv_xname); - break; - case S5144_ADPTR_1_CPU_T1E1: - case S5148_ADPTR_1_CPU_T1E1: - log(LOG_INFO, "%s: Sangoma S5144 (Single CPU) " - "T1/E1 adapter\n", self->dv_xname); - break; - case S5145_ADPTR_1_CPU_56K: - log(LOG_INFO, "%s: Sangoma S5145 (Single CPU) " - "56K adapter\n", self->dv_xname); - break; - case S5147_ADPTR_2_CPU_T1E1: - log(LOG_INFO, "%s: Sangoma S5147 (Dual CPU) " - "T1/E1 adapter\n", self->dv_xname); - break; - } - break; - - case SANGOMA_PCI_VENDOR_OLD: - switch (atype) { - case A101_ADPTR_1TE1: - log(LOG_INFO, "%s: Sangoma AFT (1 channel) " - "T1/E1 adapter\n", self->dv_xname); - break; - case A101_ADPTR_2TE1: - log(LOG_INFO, "%s: Sangoma AFT (2 channels) " - "T1/E1 adapter\n", self->dv_xname); - break; - } - break; - } -#endif - return; -} - -/* - * Module init point. - */ -int -sdladrv_init(void) -{ - int volatile i = 0; - - /* Initialize the PCI Card array, which - * will store flags, used to mark - * card initialization state */ - for (i=0; ihwcard, tmp->cpu_no) == EBUSY) - return EBUSY; - } - LIST_INIT(&sdlahw_head); - - elm_hw_card = LIST_FIRST(&sdlahw_card_head); - while (elm_hw_card) { - sdlahw_card_t *tmp = elm_hw_card; - elm_hw_card = LIST_NEXT(elm_hw_card, next); - if (sdla_card_unregister(tmp->hw_type, - tmp->slot_no, - tmp->bus_no, - tmp->ioport) == EBUSY) - return EBUSY; - } - LIST_INIT(&sdlahw_card_head); - - elm_hw_probe = LIST_FIRST(&sdlahw_probe_head); - while (elm_hw_probe) { - sdla_hw_probe_t *tmp = elm_hw_probe; - elm_hw_probe = LIST_NEXT(elm_hw_probe, next); - if (tmp->used){ - log(LOG_INFO, "HW probe info is in used (%s)\n", - elm_hw_probe->hw_info); - return EBUSY; - } - LIST_REMOVE(tmp, next); - free(tmp, M_DEVBUF, 0); - } -#endif - return (0); -} - -static void -sdla_save_hw_probe(sdlahw_t *hw, int port) -{ - sdla_hw_probe_t *tmp_hw_probe; - - tmp_hw_probe = malloc(sizeof(*tmp_hw_probe), M_DEVBUF, M_NOWAIT|M_ZERO); - if (tmp_hw_probe == NULL) - return; - - snprintf(tmp_hw_probe->hw_info, sizeof(tmp_hw_probe->hw_info), - "%s : SLOT=%d : BUS=%d : IRQ=%d : CPU=%c : PORT=%s", - SDLA_ADPTR_DECODE(hw->hwcard->atype), hw->hwcard->slot_no, - hw->hwcard->bus_no, hw->irq, SDLA_GET_CPU(hw->cpu_no), "PRI"); - - hw->hwprobe = tmp_hw_probe; - tmp_hw_probe->used++; - LIST_INSERT_HEAD(&sdlahw_probe_head, tmp_hw_probe, next); -} - -static sdlahw_t* -sdla_aft_hw_select(sdlahw_card_t *hwcard, int cpu_no, - int irq, struct pci_attach_args *pa) -{ - sdlahw_t* hw = NULL; - int number_of_cards = 0; - - hwcard->type = SDLA_AFT; - switch (hwcard->atype) { - case A101_ADPTR_1TE1: - hw = sdla_hw_register(hwcard, cpu_no, irq, pa); - sdla_save_hw_probe(hw, 0); - number_of_cards += 1; -#ifdef DEBUG - log(LOG_INFO, "%s: %s T1/E1 card found (%s rev.%d), " - "cpu(s) 1, bus #%d, slot #%d, irq #%d\n", san_drvname, - SDLA_ADPTR_DECODE(hwcard->atype), - AFT_CORE_ID_DECODE(hwcard->core_id), hwcard->core_rev, - hwcard->bus_no, hwcard->slot_no, irq); -#endif /* DEBUG */ - break; - case A101_ADPTR_2TE1: - hw = sdla_hw_register(hwcard, cpu_no, irq, pa); - sdla_save_hw_probe(hw, 0); - number_of_cards += 1; -#ifdef DEBUG - log(LOG_INFO, "%s: %s T1/E1 card found (%s rev.%d), " - "cpu(s) 2, bus #%d, slot #%d, irq #%d\n", san_drvname, - SDLA_ADPTR_DECODE(hwcard->atype), - AFT_CORE_ID_DECODE(hwcard->core_id), hwcard->core_rev, - hwcard->bus_no, hwcard->slot_no, irq); -#endif /* DEBUG */ - break; - case A105_ADPTR_1_CHN_T3E3: - - hw = sdla_hw_register(hwcard, cpu_no, irq, pa); - sdla_save_hw_probe(hw, 0); - number_of_cards += 1; -#ifdef DEBUG - log(LOG_INFO, "%s: %s T3/E3 card found, cpu(s) 1," - "bus #%d, slot #%d, irq #%d\n", san_drvname, - SDLA_ADPTR_DECODE(hwcard->atype), - hwcard->bus_no, hwcard->slot_no, irq); -#endif /* DEBUG */ - break; - default: - log(LOG_INFO, "%s: Unknown adapter %04X " - "(bus #%d, slot #%d, irq #%d)!\n", san_drvname, - hwcard->atype, hwcard->bus_no, hwcard->slot_no, irq); - break; - } - - return (hw); -} - - -static int -sdla_pci_probe(int atype, struct pci_attach_args *pa) -{ - sdlahw_card_t* hwcard; - sdlahw_t* hw; - /*sdladev_t* dev = NULL;*/ - int dual_cpu = 0; - int bus, slot, cpu = SDLA_CPU_A; - u_int16_t vendor_id, subvendor_id, device_id; - u_int8_t irq; - pci_intr_handle_t ih; - const char* intrstr = NULL; - - bus = pa->pa_bus; - slot = pa->pa_device; - vendor_id = PCI_VENDOR(pa->pa_id); - subvendor_id = PCI_SUBVENDOR(pa); - device_id = PCI_DEVICE(pa->pa_id); - irq = (u_int8_t)pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_INTLINE); - - /* Map and establish the interrupt */ - if (pci_intr_map(pa, &ih)) { - printf(": can't map interrupt\n"); - return (EINVAL); - } - intrstr = pci_intr_string(pa->pa_pc, ih); - if (intrstr != NULL) - printf(" %s\n", intrstr); - - Sangoma_cards_no ++; -reg_new_card: - Sangoma_PCI_cards_no ++; - hwcard = sdla_card_register(atype, slot, bus); - if (hwcard == NULL) - return (EINVAL); - - hwcard->memt = pa->pa_memt; - hwcard->ih = ih; - hwcard->pa = *pa; - /* Increment number of available Sangoma devices */ - Sangoma_devices_no ++; - switch (atype) { - case A101_ADPTR_1TE1: - case A101_ADPTR_2TE1: - hw = sdla_aft_hw_select(hwcard, cpu, irq, pa); - sdla_adapter_cnt.AFT_adapters++; - if (atype == A101_ADPTR_2TE1) - dual_cpu = 1; - break; - - } - - if (hw == NULL) - return (EINVAL); - if (san_dev_attach(hw, hw->devname, sizeof(hw->devname))) - return (EINVAL); - - hw->used++; - - if (dual_cpu && cpu == SDLA_CPU_A) { - cpu = SDLA_CPU_B; - goto reg_new_card; - } - - return (0); -} - -int -sdla_intr_establish(void *phw, int (*intr_func)(void*), void* intr_arg) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *hwcard; - - WAN_ASSERT(hw == NULL); - hwcard = hw->hwcard; - if (pci_intr_establish(hwcard->pa.pa_pc, hwcard->ih, IPL_NET, - intr_func, intr_arg, "san") == NULL) - return (EINVAL); - - return 0; -} - -int -sdla_intr_disestablish(void *phw) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - log(LOG_INFO, "%s: Disestablish interrupt is not defined!\n", - hw->devname); - return (EINVAL); -} - -int -sdla_get_hw_devices(void) -{ - return (Sangoma_devices_no); -} - -void* -sdla_get_hw_adptr_cnt(void) -{ - return (&sdla_adapter_cnt); -} - -static sdlahw_card_t* -sdla_card_register(u_int16_t atype, int slot_no, int bus_no) -{ - sdlahw_card_t *new_hwcard, *last_hwcard; - - new_hwcard = sdla_card_search(atype, slot_no, bus_no); - if (new_hwcard) - return (new_hwcard); - - new_hwcard = malloc(sizeof(*new_hwcard), M_DEVBUF, M_NOWAIT | M_ZERO); - if (!new_hwcard) - return (NULL); - - new_hwcard->atype = atype; - new_hwcard->slot_no = slot_no; - new_hwcard->bus_no = bus_no; - - if (LIST_EMPTY(&sdlahw_card_head)) { - /* Initialize SAN HW parameters */ - sdladrv_init(); - } - LIST_FOREACH(last_hwcard, &sdlahw_card_head, next) { - if (!LIST_NEXT(last_hwcard, next)) - break; - } - - if (last_hwcard) - LIST_INSERT_AFTER(last_hwcard, new_hwcard, next); - else - LIST_INSERT_HEAD(&sdlahw_card_head, new_hwcard, next); - - return (new_hwcard); -} - -#if 0 -static int -sdla_card_unregister(u_int16_t atype, int slot_no, int bus_no, int ioport) -{ - sdlahw_card_t* tmp_card; - - LIST_FOREACH(tmp_card, &sdlahw_card_head, next){ - if (tmp_card->atype != atype){ - continue; - } - if (tmp_card->slot_no == slot_no && - tmp_card->bus_no == bus_no){ - break; - } - } - if (tmp_card == NULL){ - log(LOG_INFO, - "Error: Card didn't find %04X card (slot=%d, bus=%d)\n" - atype, slot_no, bus_no); - return (EFAULT) - } - if (tmp_card->used){ - log(LOG_INFO, - "Error: Card is still in used (slot=%d,bus=%d,used=%d)\n", - slot_no, bus_no, tmp_card->used); - return (EBUSY); - } - LIST_REMOVE(tmp_card, next); - free(tmp_card, M_DEVBUF, 0); - return 0; -} -#endif - -static sdlahw_card_t* -sdla_card_search(u_int16_t atype, int slot_no, int bus_no) -{ - sdlahw_card_t* tmp_card; - - LIST_FOREACH(tmp_card, &sdlahw_card_head, next) { - if (tmp_card->atype != atype) - continue; - - if (tmp_card->slot_no == slot_no && - tmp_card->bus_no == bus_no) - return (tmp_card); - } - return (NULL); -} - -static sdlahw_t* -sdla_hw_register(sdlahw_card_t *card, int cpu_no, int irq, void *dev) -{ - sdlahw_t *new_hw, *last_hw; - - new_hw = sdla_hw_search(card->atype, card->slot_no, - card->bus_no, cpu_no); - if (new_hw) - return (new_hw); - - new_hw = malloc(sizeof(*new_hw), M_DEVBUF, M_NOWAIT | M_ZERO); - if (!new_hw) - return (NULL); - - new_hw->cpu_no = cpu_no; - new_hw->irq = irq; - new_hw->hwcard = card; -#if 0 - new_hw->dev = dev; -#endif - new_hw->magic = SDLAHW_MAGIC; - card->used++; - - LIST_FOREACH(last_hw, &sdlahw_head, next) { - if (!LIST_NEXT(last_hw, next)) - break; - } - if (last_hw) - LIST_INSERT_AFTER(last_hw, new_hw, next); - else - LIST_INSERT_HEAD(&sdlahw_head, new_hw, next); - - return (new_hw); -} - -#if 0 -static int -sdla_hw_unregister(sdlahw_card_t* hwcard, int cpu_no) -{ - sdlahw_t* tmp_hw; - int i; - - LIST_FOREACH(tmp_hw, &sdlahw_head, next) { - if (tmp_hw->hwcard != hwcard) - continue; - - if (tmp_hw->cpu_no == cpu_no) - break; - } - - if (tmp_hw == NULL) { - log(LOG_INFO, - "Error: Failed to find device (slot=%d,bus=%d,cpu=%c)\n", - hwcard->slot_no, hwcard->bus_no, SDLA_GET_CPU(cpu_no)); - return (EFAULT); - } - if (tmp_hw->used) { - log(LOG_INFO, - "Error: Device is still in used (slot=%d,bus=%d,cpu=%c,%d)\n", - hwcard->slot_no, - hwcard->bus_no, - SDLA_GET_CPU(cpu_no), - hwcard->used); - return (EBUSY); - } - - tmp_hw->hwprobe = NULL; - tmp_hw->hwcard = NULL; - hwcard->used--; /* Decrement card usage */ - LIST_REMOVE(tmp_hw, next); - free(tmp_hw, M_DEVBUF, 0); - - return (0); -} -#endif - -static sdlahw_t* -sdla_hw_search(u_int16_t atype, int slot_no, int bus_no, int cpu_no) -{ - sdlahw_t* tmp_hw; - - - LIST_FOREACH(tmp_hw, &sdlahw_head, next) { - if (tmp_hw->hwcard == NULL) { - log(LOG_INFO, - "Critical Error: sdla_cpu_search: line %d\n", - __LINE__); - // XXX REMOVE in LIST_FOREACH - LIST_REMOVE(tmp_hw, next); - continue; - } - if (tmp_hw->hwcard->atype != atype) { - // XXX why ??? - LIST_REMOVE(tmp_hw, next); - continue; - } - if (tmp_hw->hwcard->slot_no == slot_no && - tmp_hw->hwcard->bus_no == bus_no && - tmp_hw->cpu_no == cpu_no) - return (tmp_hw); - } - - return (NULL); -} - - -/* - * Set up adapter. - * o detect adapter type - * o set up adapter shared memory - * Return: 0 ok. - * < 0 error - */ - -int -sdla_setup(void *phw) -{ - sdlahw_card_t* hwcard = NULL; - sdlahw_t* hw = (sdlahw_t*)phw; - int err=0; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - switch (hwcard->type) { - case SDLA_AFT: - break; - - default: - log(LOG_INFO, "%s: Invalid card type %x\n", - hw->devname, hw->hwcard->type); - return (EINVAL); - } - - hw->dpmsize = SDLA_WINDOWSIZE; - - err = sdla_detect(hw); - return (err); -} - - -/* - * Shut down SDLA: disable shared memory access and interrupts, stop CPU, etc. - */ -int -sdla_down(void *phw) -{ - sdlahw_card_t* card = NULL; - sdlahw_t* hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - switch (card->type) { - case SDLA_AFT: - /* free up the allocated virtual memory */ - if (hw->status & SDLA_MEM_MAPPED) { - bus_space_unmap(hw->hwcard->memt, - hw->dpmbase, - XILINX_PCI_MEM_SIZE); - hw->status &= ~SDLA_MEM_MAPPED; - } - break; - - default: - return (EINVAL); - } - return (0); -} - -/* - * Read the hardware interrupt status. - */ -int -sdla_read_int_stat(void *phw, u_int32_t *int_status) -{ - sdlahw_card_t* card = NULL; - sdlahw_t* hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - switch (card->type) { - case SDLA_AFT: - sdla_pci_read_config_dword(hw, PCI_INT_STATUS, int_status); - } - return (0); -} - - -/* - * Generate an interrupt to adapter's CPU. - */ -int -sdla_cmd(void *phw, unsigned long offset, wan_mbox_t *mbox) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - int len = sizeof(wan_cmd_t); - int err = 0; - u_int8_t value; - - SDLA_MAGIC(hw); - len += mbox->wan_data_len; - - sdla_peek(hw, offset, (void*)&value, 1); - if (value != 0x00) { - log(LOG_INFO, "%s: opp flag set on entry to sdla_exec!\n", - hw->devname); - return (0); - } - mbox->wan_opp_flag = 0x00; - sdla_poke(hw, offset, (void*)mbox, len); - - err = sdla_exec(hw, offset); - if (!err) { - log(LOG_INFO, "%s: Command 0x%02X failed!\n", - hw->devname, mbox->wan_command); - return (WAN_CMD_TIMEOUT); - } - sdla_peek(hw, offset, (void*)mbox, sizeof(wan_cmd_t)); - if (mbox->wan_data_len) { - sdla_peek(hw, offset+offsetof(wan_mbox_t, wan_data), - mbox->wan_data, mbox->wan_data_len); - } - - return (mbox->wan_return_code); -} - -/* - * Execute Adapter Command. - * o Set exec flag. - * o Busy-wait until flag is reset. - * o Return number of loops made, or 0 if command timed out. - */ -static int -sdla_exec(sdlahw_t *hw, unsigned long offset) -{ - volatile unsigned long tstop; - volatile unsigned long nloops; - u_int8_t value; - - value = 0x01; - sdla_poke(hw, offset, (void*)&value, 1); - tstop = ticks + EXEC_TIMEOUT; - - sdla_peek(hw, offset, (void*)&value, 1); - for (nloops = 1; value == 0x01; ++ nloops) { - DELAY(EXEC_DELAY); - if (ticks - tstop > 0 || nloops > MAX_NLOOPS) { - log(LOG_INFO, "%s: Timeout %lu ticks (max=%lu) " - "loops %lu (max=%u)\n", hw->devname, - (ticks-tstop+EXEC_TIMEOUT), - (unsigned long)EXEC_TIMEOUT, nloops, MAX_NLOOPS); - return (0); /* time is up! */ - } - sdla_peek(hw, offset, (void*)&value, 1); - } - - return (nloops); -} - - -/* - * Read absolute adapter memory. - * Transfer data from adapter's memory to data buffer. - * - * Note: - * Care should be taken when crossing dual-port memory window boundary. - * This function is not atomic, so caller must disable interrupt if - * interrupt routines are accessing adapter shared memory. - */ -int -sdla_peek(void *phw, unsigned long addr, void *buf, unsigned len) -{ - sdlahw_card_t* card = NULL; - sdlahw_t* hw = (sdlahw_t*)phw; - int err = 0; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - if (addr + len > hw->memory) /* verify arguments */ - return (EINVAL); - - switch (card->type) { - case SDLA_AFT: - sdla_peek_by_4(hw, addr, buf, len); - break; - - default: - log(LOG_INFO, "%s: Invalid card type 0x%X\n", - __FUNCTION__,card->type); - err = (EINVAL); - break; - } - return (err); -} - - -/* - * Read data from adapter's memory to a data buffer in 4-byte chunks. - * Note that we ensure that the SDLA memory address is on a 4-byte boundary - * before we begin moving the data in 4-byte chunks. -*/ -static void -sdla_peek_by_4(sdlahw_t *hw, unsigned long offset, u_int8_t *buf, - unsigned int len) -{ - /* byte copy data until we get to a 4-byte boundary */ - while (len && (offset & 0x03)) { - sdla_bus_read_1(hw, offset++, buf); - buf++; - len--; - } - - /* copy data in 4-byte chunks */ - while (len >= 4) { - sdla_bus_read_4(hw, offset, (u_int32_t*)buf); - buf += 4; - offset += 4; - len -= 4; - } - - /* byte copy any remaining data */ - while (len) { - sdla_bus_read_1(hw, offset++, buf); - buf++; - len--; - } -} - -/* - * Write Absolute Adapter Memory. - * Transfer data from data buffer to adapter's memory. - * - * Note: - * Care should be taken when crossing dual-port memory window boundary. - * This function is not atomic, so caller must disable interrupt if - * interrupt routines are accessing adapter shared memory. - */ -int -sdla_poke(void *phw, unsigned long addr, void *buf, unsigned len) -{ - sdlahw_card_t* card = NULL; - sdlahw_t* hw = (sdlahw_t*)phw; - int err = 0; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - if (addr + len > hw->memory) { /* verify arguments */ - return (EINVAL); - } - - switch (card->type) { - case SDLA_AFT: - sdla_poke_by_4(hw, addr, buf, len); - break; - - default: - log(LOG_INFO, "%s: Invalid card type 0x%X\n", - __FUNCTION__,card->type); - err = (EINVAL); - break; - } - return (err); -} - - -/* - * Write from a data buffer to adapter's memory in 4-byte chunks. - * Note that we ensure that the SDLA memory address is on a 4-byte boundary - * before we begin moving the data in 4-byte chunks. -*/ -static void -sdla_poke_by_4(sdlahw_t *hw, unsigned long offset, u_int8_t *buf, - unsigned int len) -{ - /* byte copy data until we get to a 4-byte boundary */ - while (len && (offset & 0x03)) { - sdla_bus_write_1(hw, offset++, *buf); - buf++; - len --; - } - - /* copy data in 4-byte chunks */ - while (len >= 4) { - sdla_bus_write_4(hw, offset, *(unsigned long *)buf); - offset += 4; - buf += 4; - len -= 4; - } - - /* byte copy any remaining data */ - while (len) { - sdla_bus_write_1(hw, offset++, *buf); - buf++; - len --; - } -} - -int -sdla_poke_byte(void *phw, unsigned long offset, u_int8_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - SDLA_MAGIC(hw); - /* Sangoma ISA card sdla_bus_write_1(hw, offset, value); */ - sdla_poke(hw, offset, (void*)&value, 1); - return (0); -} - -int -sdla_set_bit(void *phw, unsigned long offset, u_int8_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - u_int8_t tmp; - - SDLA_MAGIC(hw); - /* Sangoma ISA card -> sdla_bus_read_1(hw, offset, &tmp); */ - sdla_peek(hw, offset, (void*)&tmp, 1); - tmp |= value; - /* Sangoma ISA card -> sdla_bus_write_1(hw, offset, tmp); */ - sdla_poke(hw, offset, (void*)&tmp, 1); - return (0); -} - -int -sdla_clear_bit(void *phw, unsigned long offset, u_int8_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - u_int8_t tmp; - - SDLA_MAGIC(hw); - /* Sangoma ISA card -> sdla_bus_read_1(hw, offset, &tmp); */ - sdla_peek(hw, offset, (void*)&tmp, 1); - tmp &= ~value; - /* Sangoma ISA card -> sdla_bus_write_1(hw, offset, tmp); */ - sdla_poke(hw, offset, (void*)&tmp, 1); - return (0); -} - -/* - * Find the AFT HDLC PCI adapter in the PCI bus. - * Return the number of AFT adapters found (0 if no adapter found). - */ -static int -sdla_detect_aft(sdlahw_t *hw) -{ - sdlahw_card_t *card; - u_int16_t ut_u16; - - WAN_ASSERT(hw == NULL); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - sdla_pci_read_config_dword(hw, - (hw->cpu_no == SDLA_CPU_A) ? PCI_IO_BASE_DWORD : - PCI_MEM_BASE0_DWORD, (u_int32_t*)&hw->mem_base_addr); - if (!hw->mem_base_addr) { - if (hw->cpu_no == SDLA_CPU_B) { - printf("%s: No PCI memory allocated for CPU #B\n", - hw->devname); - } else { - printf("%s: No PCI memory allocated to card\n", - hw->devname); - } - return (EINVAL); - } -#ifdef DEBUG - log(LOG_INFO, "%s: AFT PCI memory at 0x%lX\n", - hw->devname, (unsigned long)hw->mem_base_addr); -#endif /* DEBUG */ - sdla_pci_read_config_byte(hw, PCI_INTLINE, (u_int8_t*)&hw->irq); - if (hw->irq == PCI_IRQ_NOT_ALLOCATED) { - printf("%s: IRQ not allocated to AFT adapter\n", hw->devname); - return (EINVAL); - } - -#ifdef DEBUG - log(LOG_INFO, "%s: IRQ %d allocated to the AFT PCI card\n", - hw->devname, hw->irq); -#endif /* DEBUG */ - - hw->memory=XILINX_PCI_MEM_SIZE; - - /* Map the physical PCI memory to virtual memory */ - bus_space_map(hw->hwcard->memt, hw->mem_base_addr, XILINX_PCI_MEM_SIZE, - 0, &hw->dpmbase); - if (!hw->dpmbase) { - printf("%s: can't map mem space\n", hw->devname); - return (EINVAL); - } - hw->status |= SDLA_MEM_MAPPED; - - - /* Enable master operation on PCI and enable bar0 memory */ - sdla_pci_read_config_word(hw, XILINX_PCI_CMD_REG, &ut_u16); - ut_u16 |=0x06; - sdla_pci_write_config_word(hw, XILINX_PCI_CMD_REG, ut_u16); - - /* Set PCI Latency of 0xFF*/ - sdla_pci_write_config_dword(hw, XILINX_PCI_LATENCY_REG, - XILINX_PCI_LATENCY); - - return (0); -} - - -/* - * Detect adapter type. - */ -static int -sdla_detect(sdlahw_t *hw) -{ - sdlahw_card_t *card = NULL; - int err = 0; - - WAN_ASSERT(hw == NULL); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - switch (card->type) { - case SDLA_AFT: - err = sdla_detect_aft(hw); - break; - } - if (err) - sdla_down(hw); - - return (err); -} - -int -sdla_is_te1(void *phw) -{ - sdlahw_card_t *hwcard = NULL; - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - switch (hwcard->atype) { - case S5144_ADPTR_1_CPU_T1E1: - case S5147_ADPTR_2_CPU_T1E1: - case S5148_ADPTR_1_CPU_T1E1: - case A101_ADPTR_1TE1: - case A101_ADPTR_2TE1: - return (1); - } - return (0); -} - -int -sdla_check_mismatch(void *phw, unsigned char media) -{ - sdlahw_card_t *hwcard = NULL; - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - if (media == WAN_MEDIA_T1 || - media == WAN_MEDIA_E1) { - if (hwcard->atype != S5144_ADPTR_1_CPU_T1E1 && - hwcard->atype != S5147_ADPTR_2_CPU_T1E1 && - hwcard->atype != S5148_ADPTR_1_CPU_T1E1) { - log(LOG_INFO, "%s: Error: Card type mismatch: " - "User=T1/E1 Actual=%s\n", hw->devname, - SDLA_ADPTR_DECODE(hwcard->atype)); - return (EIO); - } - hwcard->atype = S5144_ADPTR_1_CPU_T1E1; - - } else if (media == WAN_MEDIA_56K) { - if (hwcard->atype != S5145_ADPTR_1_CPU_56K) { - log(LOG_INFO, "%s: Error: Card type mismatch: " - "User=56K Actual=%s\n", hw->devname, - SDLA_ADPTR_DECODE(hwcard->atype)); - return (EIO); - } - } else { - if (hwcard->atype == S5145_ADPTR_1_CPU_56K || - hwcard->atype == S5144_ADPTR_1_CPU_T1E1 || - hwcard->atype == S5147_ADPTR_2_CPU_T1E1 || - hwcard->atype == S5148_ADPTR_1_CPU_T1E1) { - log(LOG_INFO, "%s: Error: Card type mismatch: " - "User=S514(1/2/3) Actual=%s\n", hw->devname, - SDLA_ADPTR_DECODE(hwcard->atype)); - return (EIO); - } - } - - return (0); -} - -int -sdla_getcfg(void *phw, int type, void *value) -{ - sdlahw_t* hw = (sdlahw_t*)phw; - sdlahw_card_t *hwcard; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - switch (type) { - case SDLA_CARDTYPE: - *(u_int16_t*)value = hwcard->type; - break; - case SDLA_MEMBASE: - *(bus_space_handle_t*)value = hw->dpmbase; - break; - case SDLA_MEMEND: - *(u_int32_t*)value = ((unsigned long)hw->dpmbase + - hw->dpmsize - 1); - break; - case SDLA_MEMSIZE: - *(u_int16_t*)value = hw->dpmsize; - break; - case SDLA_MEMORY: - *(u_int32_t*)value = hw->memory; - break; - case SDLA_IRQ: - *(u_int16_t*)value = hw->irq; - break; - case SDLA_ADAPTERTYPE: - *(u_int16_t*)value = hwcard->atype; - break; - case SDLA_CPU: - *(u_int16_t*)value = hw->cpu_no; - break; - case SDLA_SLOT: - *(u_int16_t*)value = hwcard->slot_no; - break; - case SDLA_BUS: - *(u_int16_t*)value = hwcard->bus_no; - break; - case SDLA_DMATAG: - *(bus_dma_tag_t*)value = hwcard->pa.pa_dmat; - break; - case SDLA_PCIEXTRAVER: - *(u_int8_t*)value = hwcard->pci_extra_ver; - break; - case SDLA_BASEADDR: - *(u_int32_t*)value = hw->mem_base_addr; - break; - } - return (0); -} - - -int -sdla_get_hwcard(void *phw, void **phwcard) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - - *phwcard = hw->hwcard; - return (0); -} - - -int -sdla_get_hwprobe(void *phw, void **str) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - - if (hw->hwprobe) - *str = hw->hwprobe->hw_info; - - return (0); -} - -int -sdla_bus_write_1(void *phw, unsigned int offset, u_int8_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - bus_space_write_1(hw->hwcard->memt, hw->dpmbase, offset, value); - return (0); -} - -int -sdla_bus_write_2(void *phw, unsigned int offset, u_int16_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - bus_space_write_2(hw->hwcard->memt, hw->dpmbase, offset, value); - return (0); -} - -int -sdla_bus_write_4(void *phw, unsigned int offset, u_int32_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - bus_space_write_4(hw->hwcard->memt, hw->dpmbase, offset, value); - return (0); -} - -int -sdla_bus_read_1(void *phw, unsigned int offset, u_int8_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT2(hw == NULL, 0); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - *value = bus_space_read_1(hw->hwcard->memt, hw->dpmbase, offset); - return (0); -} - -int -sdla_bus_read_2(void *phw, unsigned int offset, u_int16_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT2(hw == NULL, 0); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - *value = bus_space_read_2(hw->hwcard->memt, hw->dpmbase, offset); - return (0); -} - -int -sdla_bus_read_4(void *phw, unsigned int offset, u_int32_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - - WAN_ASSERT2(hw == NULL, 0); - WAN_ASSERT2(hw->dpmbase == 0, 0); - SDLA_MAGIC(hw); - if (!(hw->status & SDLA_MEM_MAPPED)) - return (0); - *value = bus_space_read_4(hw->hwcard->memt, hw->dpmbase, offset); - return (0); -} - -static int -sdla_pci_read_config_dword(void *phw, int reg, u_int32_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *hwcard; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - *value = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg); - return (0); -} - -static int -sdla_pci_read_config_word(void *phw, int reg, u_int16_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *hwcard; - u_int32_t tmp = 0x00; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - tmp = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg); - *value = (u_int16_t)((tmp >> 16) & 0xFFFF); - return (0); -} - -static int -sdla_pci_read_config_byte(void *phw, int reg, u_int8_t *value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *hwcard; - u_int32_t tmp = 0x00; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - hwcard = hw->hwcard; - tmp = pci_conf_read(hwcard->pa.pa_pc, hwcard->pa.pa_tag, reg); - *value = (u_int8_t)(tmp & 0xFF); - return (0); -} - -static int -sdla_pci_write_config_dword(void *phw, int reg, u_int32_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *card; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - pci_conf_write(card->pa.pa_pc, card->pa.pa_tag, reg, value); - return (0); -} - -static int -sdla_pci_write_config_word(void *phw, int reg, u_int16_t value) -{ - sdlahw_t *hw = (sdlahw_t*)phw; - sdlahw_card_t *card; - - WAN_ASSERT(hw == NULL); - SDLA_MAGIC(hw); - WAN_ASSERT(hw->hwcard == NULL); - card = hw->hwcard; - pci_conf_write(card->pa.pa_pc, card->pa.pa_tag, reg, value); - return (0); -} diff --git a/sys/dev/pci/if_sandrv.h b/sys/dev/pci/if_sandrv.h deleted file mode 100644 index 1dfb096c249..00000000000 --- a/sys/dev/pci/if_sandrv.h +++ /dev/null @@ -1,333 +0,0 @@ -/* $OpenBSD: if_sandrv.h,v 1.4 2005/04/01 21:42:36 canacar Exp $ */ - -/*- - * Copyright (c) 2001-2004 Sangoma Technologies (SAN) - * All rights reserved. www.sangoma.com - * - * This code is written by Alex Feldman for SAN. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name of Sangoma Technologies nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IF_SANDRV_H -# define __IF_SANDRV_H - -#ifdef __SDLADRV__ -# define EXTERN -#else -# define EXTERN extern -#endif - - - -#define WAN_MAILBOX_SIZE 16 -#define WAN_MAX_DATA_SIZE 2032 -#pragma pack(1) -typedef struct { - union { - struct { - unsigned char opp_flag; - unsigned char command; - unsigned short data_len; - unsigned char return_code; - } wan_p_cmd; - unsigned char mbox[WAN_MAILBOX_SIZE]; - } wan_cmd_u; -#define wan_cmd_opp_flag wan_cmd_u.wan_p_cmd.opp_flag -#define wan_cmd_command wan_cmd_u.wan_p_cmd.command -#define wan_cmd_data_len wan_cmd_u.wan_p_cmd.data_len -#define wan_cmd_return_code wan_cmd_u.wan_p_cmd.return_code -} wan_cmd_t; -#pragma pack() - -/************************************************ - * GLOBAL DEFINITION FOR SANGOMA MAILBOX * - ************************************************/ -#pragma pack(1) -typedef struct { - wan_cmd_t wan_cmd; - unsigned char wan_data[WAN_MAX_DATA_SIZE]; -#define wan_opp_flag wan_cmd.wan_cmd_opp_flag -#define wan_command wan_cmd.wan_cmd_command -#define wan_data_len wan_cmd.wan_cmd_data_len -#define wan_return_code wan_cmd.wan_cmd_return_code -} wan_mbox_t; -#pragma pack() -#define WAN_MBOX_INIT(mbox) memset(mbox, 0, sizeof(wan_cmd_t)); - - -#if defined(_KERNEL) - -/* -****************************************************************** -** D E F I N E S ** -****************************************************************** -*/ -#define SDLADRV_MAJOR_VER 2 -#define SDLADRV_MINOR_VER 1 -#define SDLA_WINDOWSIZE 0x2000 /* default dual-port memory window size */ - -/* Adapter types */ -#define SDLA_S508 5080 -#define SDLA_S514 5140 -#define SDLA_ADSL 6000 -#define SDLA_AFT 7000 - -#define SDLA_PRI_PORT 1 -#define SDLA_SEC_PORT 2 - -/* Firmware supported version */ -#define SFM_VERSION 2 -#define SFM_SIGNATURE "SFM - Sangoma SDLA Firmware Module" - -/* min/max */ -#define SFM_IMAGE_SIZE 0x8000 /* max size of SDLA code image file */ -#define SFM_DESCR_LEN 256 /* max length of description string */ -#define SFM_MAX_SDLA 16 /* max number of compatible adapters */ - -/* Firmware identification numbers: - * 0 .. 999 Test & Diagnostics - * 1000 .. 1999 Streaming HDLC - * 2000 .. 2999 Bisync - * 3000 .. 3999 SDLC - * 4000 .. 4999 HDLC - * 5000 .. 5999 X.25 - * 6000 .. 6999 Frame Relay - * 7000 .. 7999 PPP - * 8000 .. 8999 Cisco HDLC - */ -#define SFID_HDLC502 4200 -#define SFID_HDLC508 4800 -#define SFID_CHDLC508 8800 -#define SFID_CHDLC514 8140 -#define SFID_AFT 30000 - -/* */ -#define SDLA_MEMBASE 0x01 -#define SDLA_MEMEND 0x02 -#define SDLA_MEMSIZE 0x03 -#define SDLA_MEMORY 0x05 -#define SDLA_BASEADDR 0x06 -#define SDLA_DMATAG 0x04 -#define SDLA_IRQ 0x07 -#define SDLA_BUS 0x08 -#define SDLA_CPU 0x0A -#define SDLA_SLOT 0x0B -#define SDLA_ADAPTERTYPE 0x0C -#define SDLA_CARDTYPE 0x0D -#define SDLA_PCIEXTRAVER 0x0E - -/* S514 PCI adapter CPU numbers */ -#define SDLA_MAX_CPUS 2 -#define S514_CPU_A 'A' -#define S514_CPU_B 'B' -#define SDLA_CPU_A 1 -#define SDLA_CPU_B 2 -#define SDLA_GET_CPU(cpu_no) (cpu_no==SDLA_CPU_A)?S514_CPU_A:S514_CPU_B - -#define AFT_CORE_ID_MASK 0x00FF -#define AFT_CORE_REV_MASK 0xFF00 -#define AFT_HDLC_CORE_ID 0x00 /* HDLC core */ -#define AFT_ATM_CORE_ID 0x01 /* ATM core */ -#define AFT_SS7_CORE_ID 0x02 /* SS7 core */ - -#define XILINX_PCI_MEM_SIZE 0x2FF -#define XILINX_PCI_LATENCY 0x0000FF00 - -#define XILINX_PCI_CMD_REG 0x04 -#define XILINX_PCI_LATENCY_REG 0x0C - -/* Local PCI register offsets */ -#if 0 -#define PCI_VENDOR_ID_WORD 0x00 /* vendor ID */ -#define PCI_DEVICE_ID_WORD 0x02 /* device ID */ -#define PCI_SUBCLASS_ID_BYTE 0x0a /* subclass ID byte */ -#endif -#define PCI_IO_BASE_DWORD 0x10 /* IO base */ -#define PCI_MEM_BASE0_DWORD 0x14 /* memory base - apperture 0 */ -#define PCI_MEM_BASE1_DWORD 0x18 /* memory base - apperture 1 */ -#if 0 -#define PCI_SUBSYS_VENDOR_WORD 0x2C /* subsystem vendor ID */ -#define PCI_SUBSYS_ID_WORD 0x2E /* subsystem ID */ -#define PCI_INT_LINE_BYTE 0x3C /* interrupt line */ -#define PCI_INT_PIN_BYTE 0x3D /* interrupt pin */ -#endif -#define PCI_MAP0_DWORD 0x40 /* PCI to local bus address 0 */ -#define PCI_MAP1_DWORD 0x44 /* PCI to local bus address 1 */ -#define PCI_INT_STATUS 0x48 /* interrupt status */ -#define PCI_INT_CONFIG 0x4C /* interrupt configuration */ - -#define PCI_DEV_SLOT_MASK 0x1F /* mask for slot numbering */ -#define PCI_IRQ_NOT_ALLOCATED 0xFF /* interrupt line for no IRQ */ -/* Local PCI register usage */ -#define PCI_MEMORY_ENABLE 0x00000003 /* enable PCI memory */ -#define PCI_CPU_A_MEM_DISABLE 0x00000002 /* disable CPU A memory */ -#define PCI_CPU_B_MEM_DISABLE 0x00100002 /* disable CPU B memory */ -#define PCI_ENABLE_IRQ_CPU_A 0x005A0004 /* enable IRQ for CPU A */ -#define PCI_ENABLE_IRQ_CPU_B 0x005A0008 /* enable IRQ for CPU B */ -#define PCI_ENABLE_IRQ_DMA0 0x01000000 /* enable IRQ for DMA 0 */ -#define PCI_ENABLE_IRQ_DMA1 0x02000000 /* enable IRQ for DMA 1 */ -#define PCI_DISABLE_IRQ_CPU_A 0x00000004 /* disable IRQ for CPU A */ -#define PCI_DISABLE_IRQ_CPU_B 0x00000008 /* disable IRQ for CPU B */ -#define PCI_DISABLE_IRQ_DMA0 0x01000000 /* disable IRQ for DMA 0 */ -#define PCI_DISABLE_IRQ_DMA1 0x02000000 /* disable IRQ for DMA 1 */ - -/* Setting for the Interrupt Status register */ -#define IRQ_DMA0 0x01000000 /* IRQ for DMA0 */ -#define IRQ_DMA1 0x02000000 /* IRQ for DMA1 */ -#define IRQ_LOCAL_CPU_A 0x00000004 /* IRQ for CPU A */ -#define IRQ_LOCAL_CPU_B 0x00000008 /* IRQ for CPU B */ -#define IRQ_CPU_A 0x04 /* IRQ for CPU A */ -#define IRQ_CPU_B 0x08 /* IRQ for CPU B */ - -/* The maximum size of the S514 memory */ -#define MAX_SIZEOF_S514_MEMORY (256 * 1024) - -/* S514 control register offsets within the memory address space */ -#define S514_CTRL_REG_BYTE 0x80000 - -/* S514 adapter control bytes */ -#define S514_CPU_HALT 0x00 -#define S514_CPU_START 0x01 - -/* The maximum number of S514 adapters supported */ -#define MAX_S514_CARDS 20 - -#define WAN_CMD_OK 0 /* normal firmware return code */ -#define WAN_CMD_TIMEOUT 0xFF /* firmware command timed out */ - -/* signature: 'SDLA' reversed */ -#define SDLAHW_MAGIC 0x414C4453L - -/* -****************************************************************** -** M A C R O S ** -****************************************************************** -*/ -#define AFT_CORE_ID_DECODE(core_id) \ - (core_id == AFT_HDLC_CORE_ID) ? "HDLC" : \ - (core_id == AFT_ATM_CORE_ID) ? "ATM" : \ - (core_id == AFT_SS7_CORE_ID) ? "SS7" : \ - "Unknown" -#define WAN_ASSERT(val) \ - if (val){ \ - log(LOG_INFO, "********** ASSERT FAILED **********\n"); \ - log(LOG_INFO, "%s:%d - Critical error\n", \ - __FILE__,__LINE__); \ - return -EINVAL; \ - } - -#define WAN_ASSERT1(val) \ - if (val){ \ - log(LOG_INFO, "********** ASSERT FAILED **********\n"); \ - log(LOG_INFO, "%s:%d - Critical error\n", \ - __FILE__,__LINE__); \ - return; \ - } - -#define WAN_ASSERT2(val, ret) \ - if (val){ \ - log(LOG_INFO, "********** ASSERT FAILED **********\n"); \ - log(LOG_INFO, "%s:%d - Critical error\n", \ - __FILE__,__LINE__); \ - return ret; \ - } - -#define SDLA_MAGIC(hw) WAN_ASSERT((hw)->magic != SDLAHW_MAGIC) -/* -****************************************************************** -** S T R U C T U R E S ** -****************************************************************** -*/ - -typedef struct sfm_info /* firmware module information */ -{ - unsigned short codeid; /* firmware ID */ - unsigned short version; /* firmaware version number */ - unsigned short adapter[SFM_MAX_SDLA]; /* compatible adapter types */ - unsigned long memsize; /* minimum memory size */ - unsigned short reserved[2]; /* reserved */ - unsigned short startoffs; /* entry point offset */ - unsigned short winoffs; /* dual-port memory window offset */ - unsigned short codeoffs; /* code load offset */ - unsigned short codesize; /* code size */ - unsigned short dataoffs; /* configuration data load offset */ - unsigned short datasize; /* configuration data size */ -} sfm_info_t; - -typedef struct sfm /* SDLA firmware file structire */ -{ - char signature[80]; /* SFM file signature */ - unsigned short version; /* file format version */ - unsigned short checksum; /* info + image */ - unsigned short reserved[6]; /* reserved */ - char descr[SFM_DESCR_LEN]; /* description string */ - sfm_info_t info; /* firmware module info */ - unsigned char image[1]; /* code image (variable size) */ -} sfm_t; - - -typedef struct sdla_hw_type_cnt -{ - unsigned char AFT_adapters; -}sdla_hw_type_cnt_t; - -/****** Function Prototypes *************************************************/ -extern int san_dev_attach(void*, u_int8_t*, int); - -/* Hardware interface function */ -extern int sdladrv_init(void); -extern int sdladrv_exit(void); -extern int sdla_get_hw_devices(void); -extern void *sdla_get_hw_adptr_cnt(void); - -extern int sdla_setup (void*); -extern int sdla_down (void*); -extern int sdla_read_int_stat (void*, u_int32_t*); -extern int sdla_check_mismatch(void*, unsigned char); -extern int sdla_cmd (void*, unsigned long, wan_mbox_t*); -extern int sdla_getcfg(void*, int, void*); -extern int sdla_bus_write_1(void*, unsigned int, u_int8_t); -extern int sdla_bus_write_2(void*, unsigned int, u_int16_t); -extern int sdla_bus_write_4(void*, unsigned int, u_int32_t); -extern int sdla_bus_read_1(void*, unsigned int, u_int8_t*); -extern int sdla_bus_read_2(void*, unsigned int, u_int16_t*); -extern int sdla_bus_read_4(void*, unsigned int, u_int32_t*); -extern int sdla_peek (void*, unsigned long, void*, unsigned); -extern int sdla_poke (void*, unsigned long, void*, unsigned); -extern int sdla_poke_byte (void*, unsigned long, u_int8_t); -extern int sdla_set_bit (void*, unsigned long, u_int8_t); -extern int sdla_clear_bit (void*, unsigned long, u_int8_t); -extern int sdla_intr_establish(void*, int(*intr_func)(void*), void*); -extern int sdla_intr_disestablish(void*); -extern int sdla_get_hwprobe(void*, void**); -extern int sdla_get_hwcard(void*, void**); -extern int sdla_is_te1(void*); - -#endif - -#undef EXTERN -#endif /* __IF_SANDRV_H */