From: jsg <jsg@openbsd.org>
Date: Fri, 4 Aug 2023 09:20:15 +0000 (+0000)
Subject: drm/amd/display: set per pipe dppclk to 0 when dpp is off
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=b671765c0dfad60c0fdc45750bd3282e2f41d20c;p=openbsd

drm/amd/display: set per pipe dppclk to 0 when dpp is off

From Dmytro Laktyushkin
f5e8f7a02c158afbfe7657e0358ee964978ee138 in linux-6.1.y/6.1.43
6609141c49df1b86fbad26a8643d4b4044f28b11 in mainline linux
---

diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 0c0feec88e4..19d034341e6 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -559,6 +559,9 @@ void dcn31_calculate_wm_and_dlg_fp(
 		context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
 		context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
 		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+		for (i = 0; i < dc->res_pool->pipe_count; i++)
+			if (context->res_ctx.pipe_ctx[i].stream)
+				context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
 	}
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 		if (!context->res_ctx.pipe_ctx[i].stream)
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index f88c80594bd..c89b761bcb9 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1305,7 +1305,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
 
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
-		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		if (context->res_ctx.pipe_ctx[i].plane_state)
+			context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		else
+			context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 		pipe_idx++;
 	}