From: jsg Date: Tue, 2 Jan 2024 00:03:06 +0000 (+0000) Subject: Revert "drm/amd/display: Do not set DRR on pipe commit" X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=af367b3e7443a92c061cdb8fd6c934952290e7d4;p=openbsd Revert "drm/amd/display: Do not set DRR on pipe commit" From Aric Cyr b09a67617621f41e12ad9ec771ff320fc8b88a94 in linux-6.1.y/6.1.70 36951fc9460fce96bafd131ceb0f343cae6d3cb9 in mainline linux --- diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 53262f6bc40..72bec33e371 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -994,5 +994,8 @@ void dcn30_prepare_bandwidth(struct dc *dc, dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); dcn20_prepare_bandwidth(dc, context); + + dc_dmub_srv_p_state_delegate(dc, + context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context); }