From: guenther Date: Fri, 21 Jul 2023 04:04:51 +0000 (+0000) Subject: Rename ARCH_CAPABILITIES_* #defined to ARCH_CAP_* X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=9ff0cc92041d55b615873825d0618233465f7dc4;p=openbsd Rename ARCH_CAPABILITIES_* #defined to ARCH_CAP_* Provide more ARCH_CAP_* defines per June 2023 SDM ok jsg@ deraadt@ --- diff --git a/sys/arch/amd64/amd64/cpu.c b/sys/arch/amd64/amd64/cpu.c index 7bd566d4e31..9cee5a06313 100644 --- a/sys/arch/amd64/amd64/cpu.c +++ b/sys/arch/amd64/amd64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.170 2023/07/10 03:32:10 guenther Exp $ */ +/* $OpenBSD: cpu.c,v 1.171 2023/07/21 04:04:51 guenther Exp $ */ /* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */ /*- @@ -273,7 +273,7 @@ replacemds(void) if (strcmp(cpu_vendor, "GenuineIntel") != 0 || ((ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP) && - (rdmsr(MSR_ARCH_CAPABILITIES) & ARCH_CAPABILITIES_MDS_NO))) { + (rdmsr(MSR_ARCH_CAPABILITIES) & ARCH_CAP_MDS_NO))) { /* Unaffected, nop out the handling code */ has_verw = 0; } else if (ci->ci_feature_sefflags_edx & SEFF0EDX_MD_CLEAR) { @@ -1242,7 +1242,7 @@ cpu_tsx_disable(struct cpu_info *ci) if (strcmp(cpu_vendor, "GenuineIntel") == 0 && (sefflags_edx & SEFF0EDX_ARCH_CAP)) { msr = rdmsr(MSR_ARCH_CAPABILITIES); - if (msr & ARCH_CAPABILITIES_TSX_CTRL) { + if (msr & ARCH_CAP_TSX_CTRL) { msr = rdmsr(MSR_TSX_CTRL); msr |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_TSX_CPUID_CLEAR; wrmsr(MSR_TSX_CTRL, msr); diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 98fdda98a6c..7904058a84f 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.133 2023/04/22 18:27:28 guenther Exp $ */ +/* $OpenBSD: identcpu.c,v 1.134 2023/07/21 04:04:51 guenther Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -1049,8 +1049,8 @@ cpu_check_vmm_cap(struct cpu_info *ci) */ if (ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP) { msr = rdmsr(MSR_ARCH_CAPABILITIES); - if ((msr & ARCH_CAPABILITIES_RDCL_NO) || - ((msr & ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY) && + if ((msr & ARCH_CAP_RDCL_NO) || + ((msr & ARCH_CAP_SKIP_L1DFL_VMENTRY) && ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr)) ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr = VMX_SKIP_L1D_FLUSH; diff --git a/sys/arch/amd64/amd64/locore0.S b/sys/arch/amd64/amd64/locore0.S index fa739e344c1..e989e37a89a 100644 --- a/sys/arch/amd64/amd64/locore0.S +++ b/sys/arch/amd64/amd64/locore0.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore0.S,v 1.21 2022/12/01 00:26:15 guenther Exp $ */ +/* $OpenBSD: locore0.S,v 1.22 2023/07/21 04:04:51 guenther Exp $ */ /* $NetBSD: locore.S,v 1.13 2004/03/25 18:33:17 drochner Exp $ */ /* @@ -235,7 +235,7 @@ bi_size_ok: /* IA32_ARCH_CAPABILITIES MSR available, use it to check CPU security */ movl $MSR_ARCH_CAPABILITIES, %ecx rdmsr - testl $ARCH_CAPABILITIES_RDCL_NO, %eax + testl $ARCH_CAP_RDCL_NO, %eax jz .Lcpu_check_finished .Lcpu_secure: diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index ca1eb336d9f..f639379a0b0 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.103 2023/07/10 03:32:10 guenther Exp $ */ +/* $OpenBSD: specialreg.h,v 1.104 2023/07/21 04:04:51 guenther Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -400,15 +400,29 @@ #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ #define MSR_ARCH_CAPABILITIES 0x10a -#define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */ -#define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */ -#define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */ -#define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3) -#define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */ -#define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */ -#define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ -#define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ -#define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */ +#define ARCH_CAP_RDCL_NO (1 << 0) /* Meltdown safe */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* enhanced IBRS */ +#define ARCH_CAP_RSBA (1 << 2) /* RSB Alternate */ +#define ARCH_CAP_SKIP_L1DFL_VMENTRY (1 << 3) +#define ARCH_CAP_SSB_NO (1 << 4) /* Spec St Byp safe */ +#define ARCH_CAP_MDS_NO (1 << 5) /* microarch data-sampling */ +#define ARCH_CAP_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ +#define ARCH_CAP_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ +#define ARCH_CAP_TAA_NO (1 << 8) /* TSX AA safe */ +#define ARCH_CAP_MCU_CONTROL (1 << 9) /* has MCU_CTRL MSR */ +#define ARCH_CAP_MISC_PACKAGE_CTLS (1 << 10) /* has MISC_PKG_CTLS MSR */ +#define ARCH_CAP_ENERGY_FILTERING_CTL (1 << 11) /* r/w energy fltring bit */ +#define ARCH_CAP_DOITM (1 << 12) /* Data oprnd indpdnt tmng */ +#define ARCH_CAP_SBDR_SSDP_NO (1 << 13) /* SBDR/SSDP safe */ +#define ARCH_CAP_FBSDP_NO (1 << 14) /* FBSDP safe */ +#define ARCH_CAP_PSDP_NO (1 << 15) /* PSDP safe */ +#define ARCH_CAP_FB_CLEAR (1 << 17) /* MD_CLEAR covers FB */ +#define ARCH_CAP_FB_CLEAR_CTRL (1 << 18) +#define ARCH_CAP_RRSBA (1 << 19) /* has RRSBA if not dis */ +#define ARCH_CAP_BHI_NO (1 << 20) /* BHI safe */ +#define ARCH_CAP_XAPIC_DISABLE_STATUS (1 << 21) /* can disable xAPIC */ +#define ARCH_CAP_OVERCLOCKING_STATUS (1 << 23) /* has OVRCLCKNG_STAT MSR */ +#define ARCH_CAP_PBRSB_NO (1 << 24) /* PBSR safe */ #define MSR_FLUSH_CMD 0x10b #define FLUSH_CMD_L1D_FLUSH 0x1 /* (1ULL << 0) */ #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ diff --git a/sys/arch/i386/i386/cpu.c b/sys/arch/i386/i386/cpu.c index c0b989e0df3..92a293a97a9 100644 --- a/sys/arch/i386/i386/cpu.c +++ b/sys/arch/i386/i386/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.112 2023/06/15 22:18:07 cheloha Exp $ */ +/* $OpenBSD: cpu.c,v 1.113 2023/07/21 04:04:52 guenther Exp $ */ /* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */ /*- @@ -478,7 +478,7 @@ cpu_tsx_disable(struct cpu_info *ci) if (strcmp(cpu_vendor, "GenuineIntel") == 0 && (sefflags_edx & SEFF0EDX_ARCH_CAP)) { msr = rdmsr(MSR_ARCH_CAPABILITIES); - if (msr & ARCH_CAPABILITIES_TSX_CTRL) { + if (msr & ARCH_CAP_TSX_CTRL) { msr = rdmsr(MSR_TSX_CTRL); msr |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_TSX_CPUID_CLEAR; wrmsr(MSR_TSX_CTRL, msr); diff --git a/sys/arch/i386/i386/locore0.S b/sys/arch/i386/i386/locore0.S index a19a64e185d..c2883e52e5b 100644 --- a/sys/arch/i386/i386/locore0.S +++ b/sys/arch/i386/i386/locore0.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore0.S,v 1.10 2022/12/08 01:25:44 guenther Exp $ */ +/* $OpenBSD: locore0.S,v 1.11 2023/07/21 04:04:52 guenther Exp $ */ /* $NetBSD: locore.s,v 1.145 1996/05/03 19:41:19 christos Exp $ */ /*- @@ -178,7 +178,7 @@ start: movw $0x1234,0x472 # warm boot /* IA32_ARCH_CAPABILITIES MSR available, use it to check CPU security */ movl $MSR_ARCH_CAPABILITIES,%ecx rdmsr - testl $ARCH_CAPABILITIES_RDCL_NO,%eax + testl $ARCH_CAP_RDCL_NO,%eax jz .Lcpu_check_finished .Lcpu_secure: diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index 22ee7abbae7..cbf5fab1758 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.81 2023/01/10 01:09:14 dv Exp $ */ +/* $OpenBSD: specialreg.h,v 1.82 2023/07/21 04:04:52 guenther Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -347,15 +347,29 @@ #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ #define MSR_ARCH_CAPABILITIES 0x10a -#define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */ -#define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */ -#define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */ -#define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3) -#define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */ -#define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */ -#define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ -#define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ -#define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */ +#define ARCH_CAP_RDCL_NO (1 << 0) /* Meltdown safe */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* enhanced IBRS */ +#define ARCH_CAP_RSBA (1 << 2) /* RSB Alternate */ +#define ARCH_CAP_SKIP_L1DFL_VMENTRY (1 << 3) +#define ARCH_CAP_SSB_NO (1 << 4) /* Spec St Byp safe */ +#define ARCH_CAP_MDS_NO (1 << 5) /* microarch data-sampling */ +#define ARCH_CAP_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ +#define ARCH_CAP_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ +#define ARCH_CAP_TAA_NO (1 << 8) /* TSX AA safe */ +#define ARCH_CAP_MCU_CONTROL (1 << 9) /* has MCU_CTRL MSR */ +#define ARCH_CAP_MISC_PACKAGE_CTLS (1 << 10) /* has MISC_PKG_CTLS MSR */ +#define ARCH_CAP_ENERGY_FILTERING_CTL (1 << 11) /* r/w energy fltring bit */ +#define ARCH_CAP_DOITM (1 << 12) /* Data oprnd indpdnt tmng */ +#define ARCH_CAP_SBDR_SSDP_NO (1 << 13) /* SBDR/SSDP safe */ +#define ARCH_CAP_FBSDP_NO (1 << 14) /* FBSDP safe */ +#define ARCH_CAP_PSDP_NO (1 << 15) /* PSDP safe */ +#define ARCH_CAP_FB_CLEAR (1 << 17) /* MD_CLEAR covers FB */ +#define ARCH_CAP_FB_CLEAR_CTRL (1 << 18) +#define ARCH_CAP_RRSBA (1 << 19) /* has RRSBA if not dis */ +#define ARCH_CAP_BHI_NO (1 << 20) /* BHI safe */ +#define ARCH_CAP_XAPIC_DISABLE_STATUS (1 << 21) /* can disable xAPIC */ +#define ARCH_CAP_OVERCLOCKING_STATUS (1 << 23) /* has OVRCLCKNG_STAT MSR */ +#define ARCH_CAP_PBRSB_NO (1 << 24) /* PBSR safe */ #define MSR_FLUSH_CMD 0x10b #define FLUSH_CMD_L1D_FLUSH (1ULL << 0) #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */