From: jsg <jsg@openbsd.org>
Date: Wed, 26 Jul 2023 06:16:19 +0000 (+0000)
Subject: drm/amd/pm: revise the ASPM settings for thunderbolt attached scenario
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=7eb2747d17f976ae12b99b1b972257fcaf4d0004;p=openbsd

drm/amd/pm: revise the ASPM settings for thunderbolt attached scenario

From Evan Quan
c8c703befd2fb2ebbcc9cedbdc98953b52453a35 in linux-6.1.y/6.1.40
fd21987274463a439c074b8f3c93d3b132e4c031 in mainline linux
---

diff --git a/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c b/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
index aa761ff3a5f..7ba47fc1917 100644
--- a/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
+++ b/sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
@@ -346,7 +346,7 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
 
 #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT		0x00000000 // off by default, no gains over L1
 #define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT		0x00000009 // 1=1us, 9=1ms
-#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT	0x0000000E // 4ms
+#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT	0x0000000E // 400ms
 
 static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
 				  bool enable)
@@ -479,9 +479,12 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
 
 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
-	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
-	data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
-	data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
+	data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+	if (pci_is_thunderbolt_attached(adev->pdev))
+		data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+	else
+		data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+	data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
 	if (def != data)
 		WREG32_PCIE(smnPCIE_LC_CNTL, data);