From: uwe <uwe@openbsd.org>
Date: Thu, 7 Dec 2023 09:46:58 +0000 (+0000)
Subject: avoid bad register access in eephy_reset for Marvell Alaska 88E1512
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=74580c44efc9169e2faf585074dbbc748d4317f2;p=openbsd

avoid bad register access in eephy_reset for Marvell Alaska 88E1512

The register write before this change had no visible run-time effect
on 88E1512 under normal conditions but it tried to update a reserved
bit and might prevent the standard behaviour of breaking the link on
insufficient Inter-Packet Gaps.

Cross-checked with datasheets for supported variants. Extended special
control register 20 exists only in E1111 but not in E151x, E1545x, or
E3016. It seems that the register was dropped in E15xx and subsequent
designs.

Originally from stsp@

ok claudio@ stsp@
---

diff --git a/sys/dev/mii/eephy.c b/sys/dev/mii/eephy.c
index efcea2b43ec..ca68e057014 100644
--- a/sys/dev/mii/eephy.c
+++ b/sys/dev/mii/eephy.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: eephy.c,v 1.61 2023/12/05 11:06:05 uwe Exp $	*/
+/*	$OpenBSD: eephy.c,v 1.62 2023/12/07 09:46:58 uwe Exp $	*/
 /*
  * Principal Author: Parag Patel
  * Copyright (c) 2001
@@ -276,10 +276,13 @@ eephy_reset(struct mii_softc *sc)
 
 	PHY_WRITE(sc, E1000_SCR, reg);
 
-	/* 25 MHz TX_CLK should always work. */
-	reg = PHY_READ(sc, E1000_ESCR);
-	reg |= E1000_ESCR_TX_CLK_25;
-	PHY_WRITE(sc, E1000_ESCR, reg);
+	if (sc->mii_model != MII_MODEL_MARVELL_E1512 &&
+	    sc->mii_model != MII_MODEL_MARVELL_E1545) {
+		/* 25 MHz TX_CLK should always work. */
+		reg = PHY_READ(sc, E1000_ESCR);
+		reg |= E1000_ESCR_TX_CLK_25;
+		PHY_WRITE(sc, E1000_ESCR, reg);
+	}
 
 	/* Configure LEDs if they were left unconfigured. */
 	if (sc->mii_model == MII_MODEL_MARVELL_E3016 &&
diff --git a/sys/dev/mii/eephyreg.h b/sys/dev/mii/eephyreg.h
index 59c6c567898..593127a7b4b 100644
--- a/sys/dev/mii/eephyreg.h
+++ b/sys/dev/mii/eephyreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: eephyreg.h,v 1.9 2022/01/09 05:42:44 jsg Exp $	*/
+/*	$OpenBSD: eephyreg.h,v 1.10 2023/12/07 09:46:58 uwe Exp $	*/
 /*
  * Principal Author: Parag Patel
  * Copyright (c) 2001
@@ -284,6 +284,7 @@
 #define E1000_ISR_SPEED_CHANGED		0x4000
 #define E1000_ISR_AUTO_NEG_ERR		0x8000
 
+/* page any */
 #define E1000_ESCR			0x14	/* extended special control reg */
 #define E1000_ESCR_FIBER_LOOPBACK	0x4000
 #define E1000_ESCR_DOWN_NO_IDLE		0x8000