From: deraadt <deraadt@openbsd.org>
Date: Tue, 11 May 2021 14:58:08 +0000 (+0000)
Subject: whitespace cleanup
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=4ea72c642af027c5f11b67603f574d15658b36fa;p=openbsd

whitespace cleanup
---

diff --git a/sys/arch/riscv64/conf/GENERIC b/sys/arch/riscv64/conf/GENERIC
index bacf03af089..41bb7100144 100644
--- a/sys/arch/riscv64/conf/GENERIC
+++ b/sys/arch/riscv64/conf/GENERIC
@@ -51,10 +51,13 @@ sfcc*		at fdt? early 1
 syscon*		at fdt? early 1
 gfrtc*		at fdt?
 
+dwge*		at fdt?
+ukphy*		at mii?
+
 dwmmc*		at fdt?
 sdmmc*		at dwmmc?
 
-scsibus*        at scsi?
+scsibus*	at scsi?
 sd*		at scsibus?
 cd*		at scsibus?
 ch*		at scsibus?
diff --git a/sys/arch/riscv64/conf/RAMDISK b/sys/arch/riscv64/conf/RAMDISK
index b8b94ff2900..65f5dda5860 100644
--- a/sys/arch/riscv64/conf/RAMDISK
+++ b/sys/arch/riscv64/conf/RAMDISK
@@ -1,4 +1,4 @@
-# $OpenBSD: RAMDISK,v 1.8 2021/05/06 04:09:41 jsg Exp $
+# $OpenBSD: RAMDISK,v 1.9 2021/05/11 14:58:08 deraadt Exp $
 #
 # GENERIC machine description file
 #
@@ -73,7 +73,7 @@ gfrtc*		at fdt?
 dwmmc*		at fdt?
 sdmmc*		at dwmmc?
 
-scsibus*        at scsi?
+scsibus*	at scsi?
 sd*		at scsibus?
 cd*		at scsibus?
 ch*		at scsibus?
diff --git a/sys/arch/riscv64/dev/plic.c b/sys/arch/riscv64/dev/plic.c
index dcb2dfc691c..a1ffd009561 100644
--- a/sys/arch/riscv64/dev/plic.c
+++ b/sys/arch/riscv64/dev/plic.c
@@ -82,8 +82,8 @@ struct plic_intrhand {
  */
 struct plic_irqsrc {
 	TAILQ_HEAD(, plic_intrhand) is_list; /* handler list */
-	int 	is_irq_max;	/* IRQ to mask while handling */
-	int 	is_irq_min;	/* lowest IRQ when shared */
+	int	is_irq_max;	/* IRQ to mask while handling */
+	int	is_irq_min;	/* lowest IRQ when shared */
 };
 
 struct plic_context {
@@ -99,7 +99,7 @@ struct plic_softc {
 	struct plic_irqsrc	*sc_isrcs;
 	struct plic_context	sc_contexts[MAXCPUS];
 	int			sc_ndev;
-	struct interrupt_controller 	sc_intc;
+	struct interrupt_controller	sc_intc;
 };
 struct plic_softc *plic = NULL;
 
@@ -408,7 +408,7 @@ plic_intr_establish(int irqno, int level, int (*func)(void *),
 
 	if (irqno < 0 || irqno >= PLIC_MAX_IRQS)
 		panic("plic_intr_establish: bogus irqnumber %d: %s",
-		     irqno, name);
+		    irqno, name);
 	sie = disable_interrupts();
 
 	ih = malloc(sizeof *ih, M_DEVBUF, M_WAITOK);
@@ -466,7 +466,7 @@ plic_intr_route(void *cookie, int enable, struct cpu_info *ci)
 
 	int		irq = ih->ih_irq;
 	int		cpu = ci->ci_cpuid;
-	uint32_t 	min_pri = sc->sc_isrcs[irq].is_irq_min;
+	uint32_t	min_pri = sc->sc_isrcs[irq].is_irq_min;
 
 	if (enable == IRQ_ENABLE) {
 		plic_intr_enable_with_pri(irq, min_pri, cpu);
@@ -542,7 +542,7 @@ plic_setipl(int new)
 
 	restore_interrupts(sie);
 }
- 
+
  /*
   * update the max/min priority for an interrupt src,
   * and enforce the updated priority to plic.
@@ -551,10 +551,10 @@ plic_setipl(int new)
 void
 plic_calc_mask(void)
 {
-	struct cpu_info 	*ci = curcpu();
-	struct plic_softc 	*sc = plic;
-	struct plic_intrhand 	*ih;
-	int 			irq;
+	struct cpu_info		*ci = curcpu();
+	struct plic_softc	*sc = plic;
+	struct plic_intrhand	*ih;
+	int			irq;
 
 	/* PLIC irq 0 is reserved, thus we start from 1 */
 	for (irq = 1; irq <= sc->sc_ndev; irq++) {
diff --git a/sys/arch/riscv64/dev/plic.h b/sys/arch/riscv64/dev/plic.h
index 1d806d987e1..a3677df1867 100644
--- a/sys/arch/riscv64/dev/plic.h
+++ b/sys/arch/riscv64/dev/plic.h
@@ -25,11 +25,11 @@ int	plic_spllower(int);
 int	plic_splraise(int);
 void	plic_setipl(int);
 
-void 	*plic_intr_establish(int, int, int (*)(void *),
+void	*plic_intr_establish(int, int, int (*)(void *),
 		void *, char *);
-void 	*plic_intr_establish_fdt(void *, int *, int,
+void	*plic_intr_establish_fdt(void *, int *, int,
 		int (*)(void *), void *, char *);
-void 	plic_intr_disestablish(void *);
+void	plic_intr_disestablish(void *);
 
 #endif /* ! _LOCORE */
 
diff --git a/sys/arch/riscv64/dev/riscv_cpu_intc.c b/sys/arch/riscv64/dev/riscv_cpu_intc.c
index 799dc0c5baa..e1cffbdf3e6 100644
--- a/sys/arch/riscv64/dev/riscv_cpu_intc.c
+++ b/sys/arch/riscv64/dev/riscv_cpu_intc.c
@@ -50,12 +50,12 @@ void	*riscv_intc_intr_establish(int, int, int (*)(void *),
 void	riscv_intc_intr_disestablish(void *);
 
 
-struct cfattach        intc_ca = {
-       sizeof (struct device), riscv_intc_match, riscv_intc_attach
+struct cfattach intc_ca = {
+	sizeof (struct device), riscv_intc_match, riscv_intc_attach
 };
 
 struct cfdriver intc_cd = {
-       NULL, "intc", DV_DULL
+	NULL, "intc", DV_DULL
 };
 
 int
@@ -64,7 +64,7 @@ riscv_intc_match(struct device *parent, void *match, void *aux)
 	struct fdt_attach_args *faa = aux;
 	int node = faa->fa_node;
 	return (OF_getproplen(node, "interrupt-controller") >= 0 &&
-		OF_is_compatible(node, "riscv,cpu-intc"));
+	    OF_is_compatible(node, "riscv,cpu-intc"));
 }
 
 void
@@ -105,8 +105,7 @@ riscv_intc_irq_handler(void *frame)
 {
 	int irq;
 	struct intrhand *ih;
-	struct trapframe *_frame;
-        _frame = (struct trapframe*) frame;
+	struct trapframe *_frame = (struct trapframe*) frame;
 
 	KASSERTMSG(_frame->tf_scause & EXCP_INTR,
 		"riscv_cpu_intr: wrong frame passed");
@@ -134,7 +133,7 @@ riscv_intc_intr_establish(int irqno, int dummy_level, int (*func)(void *),
 
 	if (irqno < 0 || irqno >= INTC_NIRQS)
 		panic("intc_intr_establish: bogus irqnumber %d: %s",
-		     irqno, name);
+		    irqno, name);
 	sie = disable_interrupts();
 
 	ih = malloc(sizeof(*ih), M_DEVBUF, M_WAITOK);
diff --git a/sys/arch/riscv64/dev/riscv_cpu_intc.h b/sys/arch/riscv64/dev/riscv_cpu_intc.h
index d8c7b660c12..16d1a2553a0 100644
--- a/sys/arch/riscv64/dev/riscv_cpu_intc.h
+++ b/sys/arch/riscv64/dev/riscv_cpu_intc.h
@@ -17,11 +17,11 @@
 #ifndef _RISCV_CPU_INTC_H_
 #define _RISCV_CPU_INTC_H_
 
-void 	*riscv_intc_intr_establish(int, int, int (*func)(void *),
+void	*riscv_intc_intr_establish(int, int, int (*func)(void *),
 		void *, char *);
-void 	*riscv_intc_intr_establish_fdt(void *, int *, int, int (*)(void *),
+void	*riscv_intc_intr_establish_fdt(void *, int *, int, int (*)(void *),
 		void *, char *);
-void 	riscv_intc_intr_disestablish(void *cookie);
+void	riscv_intc_intr_disestablish(void *cookie);
 
 #endif /* _RISCV_CPU_INTC_H_ */
 
diff --git a/sys/arch/riscv64/dev/simplebus.c b/sys/arch/riscv64/dev/simplebus.c
index 7fa9138b71d..d6fad127520 100644
--- a/sys/arch/riscv64/dev/simplebus.c
+++ b/sys/arch/riscv64/dev/simplebus.c
@@ -339,7 +339,7 @@ simplebus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
 
 		/* For each range. */
 		for (range = sc->sc_dmaranges; rlen >= rone;
-		     rlen -= rone, range += rone) {
+		    rlen -= rone, range += rone) {
 			/* Extract from and size, so we can see if we fit. */
 			rfrom = range[sc->sc_acells];
 			if (sc->sc_pacells == 2)
diff --git a/sys/arch/riscv64/include/bootconfig.h b/sys/arch/riscv64/include/bootconfig.h
index 49a5ca22cde..050cde28d40 100644
--- a/sys/arch/riscv64/include/bootconfig.h
+++ b/sys/arch/riscv64/include/bootconfig.h
@@ -44,7 +44,7 @@ struct riscv_bootparams {
 	vaddr_t		kern_l1pt;	/* L1 page table for the kernel */
 	uint64_t	kern_delta;	/* PA - VA */
 	vaddr_t		kern_stack;
-#if 0 
+#if 0
 	void		*arg0; // passed to kernel in R0
 	void		*arg1; // passed to kernel in R1
 	void		*arg2; // passed to kernel in R2
diff --git a/sys/arch/riscv64/include/cpu.h b/sys/arch/riscv64/include/cpu.h
index 0a7f7bff3ed..e036dc47191 100644
--- a/sys/arch/riscv64/include/cpu.h
+++ b/sys/arch/riscv64/include/cpu.h
@@ -142,8 +142,8 @@ struct cpu_info {
 #endif
 };
 
-#define CPUF_PRIMARY 		(1<<0)
-#define CPUF_AP	 		(1<<1)
+#define CPUF_PRIMARY		(1<<0)
+#define CPUF_AP			(1<<1)
 #define CPUF_IDENTIFY		(1<<2)
 #define CPUF_IDENTIFIED		(1<<3)
 #define CPUF_PRESENT		(1<<4)
@@ -154,7 +154,7 @@ static inline struct cpu_info *
 curcpu(void)
 {
 	struct cpu_info *__ci = NULL;
-        __asm __volatile("mv %0, tp" : "=&r"(__ci));
+	__asm __volatile("mv %0, tp" : "=&r"(__ci));
 	return (__ci);
 }
 
@@ -202,7 +202,7 @@ cpu_rnd_messybits(void)
 /*
  * Scheduling glue
  */
-#define aston(p)        ((p)->p_md.md_astpending = 1)
+#define aston(p)	((p)->p_md.md_astpending = 1)
 #define	setsoftast()	aston(curcpu()->ci_curproc)
 
 /*
@@ -212,12 +212,12 @@ cpu_rnd_messybits(void)
 
 #ifdef MULTIPROCESSOR
 void cpu_unidle(struct cpu_info *ci);
-#define signotify(p)            (aston(p), cpu_unidle((p)->p_cpu))
+#define signotify(p)	(aston(p), cpu_unidle((p)->p_cpu))
 void cpu_kick(struct cpu_info *);
 #else
 #define cpu_kick(ci)
 #define cpu_unidle(ci)
-#define signotify(p)            setsoftast()
+#define signotify(p)	setsoftast()
 #endif
 
 /*
@@ -225,7 +225,7 @@ void cpu_kick(struct cpu_info *);
  * or after the current trap/syscall if in system mode.
  */
 void need_resched(struct cpu_info *);
-#define clear_resched(ci) 	((ci)->ci_want_resched = 0)
+#define clear_resched(ci)	((ci)->ci_want_resched = 0)
 
 /*
  * Give a profiling tick to the current process when the user profiling
diff --git a/sys/arch/riscv64/include/db_machdep.h b/sys/arch/riscv64/include/db_machdep.h
index 73e0bbdd7d9..414fc34dbf6 100644
--- a/sys/arch/riscv64/include/db_machdep.h
+++ b/sys/arch/riscv64/include/db_machdep.h
@@ -47,7 +47,7 @@
 #define	T_BREAKPOINT	(EXCP_BREAKPOINT)
 #define	T_WATCHPOINT	(0)
 
-typedef vaddr_t 	db_addr_t;
+typedef vaddr_t		db_addr_t;
 typedef long		db_expr_t;
 
 typedef trapframe_t	db_regs_t;
diff --git a/sys/arch/riscv64/include/intr.h b/sys/arch/riscv64/include/intr.h
index 100e7f2145a..a38ee8b1463 100644
--- a/sys/arch/riscv64/include/intr.h
+++ b/sys/arch/riscv64/include/intr.h
@@ -184,7 +184,7 @@ extern uint32_t riscv_smask[NIPL];
 
 #include <machine/softintr.h>
 
-void 	riscv_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
+void	riscv_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
     void (*)(void));
 
 /*
diff --git a/sys/arch/riscv64/include/pmap.h b/sys/arch/riscv64/include/pmap.h
index 6208f387203..3f2995d2175 100644
--- a/sys/arch/riscv64/include/pmap.h
+++ b/sys/arch/riscv64/include/pmap.h
@@ -42,10 +42,10 @@
 /* cache flags */
 // XXX These are duplicated from arm64 and may need some reworking
 #define PMAP_CACHE_CI		(PMAP_MD0)		/* cache inhibit */
-#define PMAP_CACHE_WT		(PMAP_MD1)	 	/* writethru */
+#define PMAP_CACHE_WT		(PMAP_MD1)		/* writethru */
 #define PMAP_CACHE_WB		(PMAP_MD1|PMAP_MD0)	/* writeback */
 #define PMAP_CACHE_DEV		(PMAP_MD2)		/* device mapping */
-#define PMAP_CACHE_BITS		(PMAP_MD0|PMAP_MD1|PMAP_MD2)	
+#define PMAP_CACHE_BITS		(PMAP_MD0|PMAP_MD1|PMAP_MD2)
 
 #define PTED_VA_MANAGED_M	(PMAP_MD3)
 #define PTED_VA_WIRED_M		(PMAP_MD3 << 1)
@@ -87,7 +87,7 @@ extern paddr_t copy_dst_page;
 void pagezero(vaddr_t);
 
 extern struct pmap kernel_pmap_;
-#define pmap_kernel()   		(&kernel_pmap_)
+#define pmap_kernel()			(&kernel_pmap_)
 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
 
diff --git a/sys/arch/riscv64/include/profile.h b/sys/arch/riscv64/include/profile.h
index 7c7effc98ed..5034f85912c 100644
--- a/sys/arch/riscv64/include/profile.h
+++ b/sys/arch/riscv64/include/profile.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: profile.h,v 1.1 2021/04/23 02:42:16 drahn Exp $ */
+/* $OpenBSD: profile.h,v 1.2 2021/05/11 14:58:08 deraadt Exp $ */
 /*
  * Copyright (c) 2015 Dale Rahn <drahn@dalerahn.com>
  *
@@ -87,5 +87,5 @@ __asm__ (".text						\n;"	\
 __asm__ ("mrs %x0,daif; msr daifset, #0x2": "=r"(s));
 #define	MCOUNT_EXIT						\
 __asm__ ("msr daif, %x0":: "r"(s));
-	
+
 #endif // _KERNEL
diff --git a/sys/arch/riscv64/include/riscvreg.h b/sys/arch/riscv64/include/riscvreg.h
index a2a9453c033..5f8eb4a28b6 100644
--- a/sys/arch/riscv64/include/riscvreg.h
+++ b/sys/arch/riscv64/include/riscvreg.h
@@ -194,24 +194,24 @@
 	(__builtin_constant_p(val) && ((u_long)(val) < 32))
 
 #define csr_swap(csr, val)						\
-({	if (CSR_ZIMM(val))  						\
+({	if (CSR_ZIMM(val))						\
 		__asm __volatile("csrrwi %0, " #csr ", %1"		\
 				: "=r" (val) : "i" (val));		\
-	else 								\
+	else								\
 		__asm __volatile("csrrw %0, " #csr ", %1"		\
 				: "=r" (val) : "r" (val));		\
 	val;								\
 })
 
 #define csr_write(csr, val)						\
-({	if (CSR_ZIMM(val)) 						\
+({	if (CSR_ZIMM(val))						\
 		__asm __volatile("csrwi " #csr ", %0" :: "i" (val));	\
-	else 								\
+	else								\
 		__asm __volatile("csrw " #csr ", %0" ::  "r" (val));	\
 })
 
 #define csr_set(csr, val)						\
-({	if (CSR_ZIMM(val)) 						\
+({	if (CSR_ZIMM(val))						\
 		__asm __volatile("csrsi " #csr ", %0" :: "i" (val));	\
 	else								\
 		__asm __volatile("csrs " #csr ", %0" :: "r" (val));	\
diff --git a/sys/arch/riscv64/include/softintr.h b/sys/arch/riscv64/include/softintr.h
index f65ec1c61ea..5da7d00258e 100644
--- a/sys/arch/riscv64/include/softintr.h
+++ b/sys/arch/riscv64/include/softintr.h
@@ -55,26 +55,26 @@ struct soft_intrhand {
 	TAILQ_ENTRY(soft_intrhand)
 		sih_q;
 	struct soft_intr *sih_intrhead;
-	void    (*sih_fn)(void *);
-	void    (*sih_fnwrap)(void *);
-	void    *sih_arg;
-	void    *sih_argwrap;
-	int     sih_pending;
+	void	(*sih_fn)(void *);
+	void	(*sih_fnwrap)(void *);
+	void	*sih_arg;
+	void	*sih_argwrap;
+	int	sih_pending;
 };
 
 struct soft_intr {
 	TAILQ_HEAD(, soft_intrhand)
 			softintr_q;
-	int             softintr_ssir;
-	struct mutex    softintr_lock;
+	int		softintr_ssir;
+	struct mutex	softintr_lock;
 };
 
-#define SOFTINTR_ESTABLISH_MPSAFE       0x01
+#define SOFTINTR_ESTABLISH_MPSAFE	0x01
 void    *softintr_establish_flags(int, void (*)(void *), void *, int);
-#define softintr_establish(i, f, a)                                     \
-        softintr_establish_flags(i, f, a, 0)
-#define softintr_establish_mpsafe(i, f, a)                              \
-        softintr_establish_flags(i, f, a, SOFTINTR_ESTABLISH_MPSAFE)
+#define softintr_establish(i, f, a)					\
+	softintr_establish_flags(i, f, a, 0)
+#define softintr_establish_mpsafe(i, f, a)				\
+	softintr_establish_flags(i, f, a, SOFTINTR_ESTABLISH_MPSAFE)
 void    softintr_disestablish(void *);
 void    softintr_init(void);
 void    softintr_dispatch(int);
diff --git a/sys/arch/riscv64/include/vmparam.h b/sys/arch/riscv64/include/vmparam.h
index 250d4d9461b..883b57d0a34 100644
--- a/sys/arch/riscv64/include/vmparam.h
+++ b/sys/arch/riscv64/include/vmparam.h
@@ -45,7 +45,7 @@
  * Virtual memory related constants, all in bytes
  */
 #ifndef MAXTSIZ
-#define	MAXTSIZ	        ((paddr_t)1*1024*1024*1024)	/* max text size */
+#define	MAXTSIZ		((paddr_t)1*1024*1024*1024)	/* max text size */
 #endif
 #ifndef DFLDSIZ
 #define	DFLDSIZ		((paddr_t)128*1024*1024)	/* initial data size limit */
@@ -75,7 +75,7 @@
 /*
  * Size of User Raw I/O map
  */
-#define	USRIOSIZE 	300
+#define	USRIOSIZE	300
 
 /**
  * Address space layout.
diff --git a/sys/arch/riscv64/riscv64/conf.c b/sys/arch/riscv64/riscv64/conf.c
index 07e279a4f34..32e7098e72b 100644
--- a/sys/arch/riscv64/riscv64/conf.c
+++ b/sys/arch/riscv64/riscv64/conf.c
@@ -179,7 +179,7 @@ struct cdevsw	cdevsw[] =
 	cdev_openprom_init(NOPENPROM,openprom),	/* 70: /dev/openprom */
 	cdev_notdef(),			/* 71: was: Cyclades-Z serial port */
 #ifdef USER_PCICONF
-	cdev_pci_init(NPCI,pci),        /* 72: PCI user */
+	cdev_pci_init(NPCI,pci),	/* 72: PCI user */
 #else
 	cdev_notdef(),
 #endif
@@ -201,7 +201,7 @@ struct cdevsw	cdevsw[] =
 	cdev_notdef(),			/* 88: GPIO interface */
 	cdev_vscsi_init(NVSCSI,vscsi),	/* 89: vscsi */
 	cdev_disk_init(1,diskmap),	/* 90: disk mapper */
-	cdev_pppx_init(NPPPX,pppx),     /* 91: pppx */
+	cdev_pppx_init(NPPPX,pppx),	/* 91: pppx */
 	cdev_fuse_init(NFUSE,fuse),	/* 92: fuse */
 	cdev_tun_init(NTUN,tap),	/* 93: Ethernet network tunnel */
 	cdev_notdef(),			/* 94 */
diff --git a/sys/arch/riscv64/riscv64/db_disasm.c b/sys/arch/riscv64/riscv64/db_disasm.c
index 31f6f0f94be..95aabf892af 100644
--- a/sys/arch/riscv64/riscv64/db_disasm.c
+++ b/sys/arch/riscv64/riscv64/db_disasm.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_disasm.c,v 1.3 2021/05/08 18:10:03 deraadt Exp $	*/
+/*	$OpenBSD: db_disasm.c,v 1.4 2021/05/11 14:58:08 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2016-2018 Ruslan Bukin <br@bsdpad.com>
@@ -99,206 +99,206 @@ static struct riscv_op riscv_opcodes[] = {
 	{"ret","", MATCH_JALR | (X_RA << RS1_SHIFT),
 	    MASK_JALR | RD_MASK | RS1_MASK | IMM_MASK, m_op },
 
-	{ "beq",	"s,t,p", 	MATCH_BEQ, MASK_BEQ,		m_op },
-	{ "bne",	"s,t,p", 	MATCH_BNE, MASK_BNE,		m_op },
-	{ "blt",	"s,t,p", 	MATCH_BLT, MASK_BLT,		m_op },
-	{ "bge",	"s,t,p", 	MATCH_BGE, MASK_BGE,		m_op },
-	{ "bltu",	"s,t,p", 	MATCH_BLTU, MASK_BLTU,		m_op },
-	{ "bgeu",	"s,t,p", 	MATCH_BGEU, MASK_BGEU,		m_op },
-	{ "jalr",	"d,o(s)", 	MATCH_JALR, MASK_JALR,		m_op },
-	{ "jal",	"d,a", 		MATCH_JAL, MASK_JAL,		m_op },
-	{ "lui",	"d,u", 		MATCH_LUI, MASK_LUI,		m_op },
-	{ "auipc",	"d,u", 		MATCH_AUIPC, MASK_AUIPC,	m_op },
-	{ "addi",	"d,s,j", 	MATCH_ADDI, MASK_ADDI,		m_op },
-	{ "slli",	"d,s,>", 	MATCH_SLLI, MASK_SLLI,		m_op },
-	{ "slti",	"d,s,j", 	MATCH_SLTI, MASK_SLTI,		m_op },
-	{ "sltiu",	"d,s,j", 	MATCH_SLTIU, MASK_SLTIU,	m_op },
-	{ "xori",	"d,s,j", 	MATCH_XORI, MASK_XORI,		m_op },
-	{ "srli",	"d,s,>", 	MATCH_SRLI, MASK_SRLI,		m_op },
-	{ "srai",	"d,s,>", 	MATCH_SRAI, MASK_SRAI,		m_op },
-	{ "ori",	"d,s,j", 	MATCH_ORI, MASK_ORI,		m_op },
-	{ "andi",	"d,s,j", 	MATCH_ANDI, MASK_ANDI,		m_op },
-	{ "add",	"d,s,t", 	MATCH_ADD, MASK_ADD,		m_op },
-	{ "sub",	"d,s,t", 	MATCH_SUB, MASK_SUB,		m_op },
-	{ "sll",	"d,s,t", 	MATCH_SLL, MASK_SLL,		m_op },
-	{ "slt",	"d,s,t", 	MATCH_SLT, MASK_SLT,		m_op },
-	{ "sltu",	"d,s,t", 	MATCH_SLTU, MASK_SLTU,		m_op },
-	{ "xor",	"d,s,t", 	MATCH_XOR, MASK_XOR,		m_op },
-	{ "srl",	"d,s,t", 	MATCH_SRL, MASK_SRL,		m_op },
-	{ "sra",	"d,s,t", 	MATCH_SRA, MASK_SRA,		m_op },
-	{ "or",		"d,s,t", 	MATCH_OR, MASK_OR,		m_op },
-	{ "and",	"d,s,t", 	MATCH_AND, MASK_AND,		m_op },
-	{ "addiw",	"d,s,j", 	MATCH_ADDIW, MASK_ADDIW,	m_op },
-	{ "slliw",	"d,s,<", 	MATCH_SLLIW, MASK_SLLIW,	m_op },
-	{ "srliw",	"d,s,<", 	MATCH_SRLIW, MASK_SRLIW,	m_op },
-	{ "sraiw",	"d,s,<", 	MATCH_SRAIW, MASK_SRAIW,	m_op },
-	{ "addw",	"d,s,t", 	MATCH_ADDW, MASK_ADDW,		m_op },
-	{ "subw",	"d,s,t", 	MATCH_SUBW, MASK_SUBW,		m_op },
-	{ "sllw",	"d,s,t", 	MATCH_SLLW, MASK_SLLW,		m_op },
-	{ "srlw",	"d,s,t", 	MATCH_SRLW, MASK_SRLW,		m_op },
-	{ "sraw",	"d,s,t", 	MATCH_SRAW, MASK_SRAW,		m_op },
-	{ "lb",		"d,o(s)", 	MATCH_LB, MASK_LB,		m_op },
-	{ "lh",		"d,o(s)", 	MATCH_LH, MASK_LH,		m_op },
-	{ "lw",		"d,o(s)", 	MATCH_LW, MASK_LW,		m_op },
-	{ "ld",		"d,o(s)", 	MATCH_LD, MASK_LD,		m_op },
-	{ "lbu",	"d,o(s)", 	MATCH_LBU, MASK_LBU,		m_op },
-	{ "lhu",	"d,o(s)", 	MATCH_LHU, MASK_LHU,		m_op },
-	{ "lwu",	"d,o(s)", 	MATCH_LWU, MASK_LWU,		m_op },
-	{ "sb",		"t,q(s)", 	MATCH_SB, MASK_SB,		m_op },
-	{ "sh",		"t,q(s)", 	MATCH_SH, MASK_SH,		m_op },
-	{ "sw",		"t,q(s)", 	MATCH_SW, MASK_SW,		m_op },
-	{ "sd",		"t,q(s)", 	MATCH_SD, MASK_SD,		m_op },
+	{ "beq",	"s,t,p",	MATCH_BEQ, MASK_BEQ,		m_op },
+	{ "bne",	"s,t,p",	MATCH_BNE, MASK_BNE,		m_op },
+	{ "blt",	"s,t,p",	MATCH_BLT, MASK_BLT,		m_op },
+	{ "bge",	"s,t,p",	MATCH_BGE, MASK_BGE,		m_op },
+	{ "bltu",	"s,t,p",	MATCH_BLTU, MASK_BLTU,		m_op },
+	{ "bgeu",	"s,t,p",	MATCH_BGEU, MASK_BGEU,		m_op },
+	{ "jalr",	"d,o(s)",	MATCH_JALR, MASK_JALR,		m_op },
+	{ "jal",	"d,a",		MATCH_JAL, MASK_JAL,		m_op },
+	{ "lui",	"d,u",		MATCH_LUI, MASK_LUI,		m_op },
+	{ "auipc",	"d,u",		MATCH_AUIPC, MASK_AUIPC,	m_op },
+	{ "addi",	"d,s,j",	MATCH_ADDI, MASK_ADDI,		m_op },
+	{ "slli",	"d,s,>",	MATCH_SLLI, MASK_SLLI,		m_op },
+	{ "slti",	"d,s,j",	MATCH_SLTI, MASK_SLTI,		m_op },
+	{ "sltiu",	"d,s,j",	MATCH_SLTIU, MASK_SLTIU,	m_op },
+	{ "xori",	"d,s,j",	MATCH_XORI, MASK_XORI,		m_op },
+	{ "srli",	"d,s,>",	MATCH_SRLI, MASK_SRLI,		m_op },
+	{ "srai",	"d,s,>",	MATCH_SRAI, MASK_SRAI,		m_op },
+	{ "ori",	"d,s,j",	MATCH_ORI, MASK_ORI,		m_op },
+	{ "andi",	"d,s,j",	MATCH_ANDI, MASK_ANDI,		m_op },
+	{ "add",	"d,s,t",	MATCH_ADD, MASK_ADD,		m_op },
+	{ "sub",	"d,s,t",	MATCH_SUB, MASK_SUB,		m_op },
+	{ "sll",	"d,s,t",	MATCH_SLL, MASK_SLL,		m_op },
+	{ "slt",	"d,s,t",	MATCH_SLT, MASK_SLT,		m_op },
+	{ "sltu",	"d,s,t",	MATCH_SLTU, MASK_SLTU,		m_op },
+	{ "xor",	"d,s,t",	MATCH_XOR, MASK_XOR,		m_op },
+	{ "srl",	"d,s,t",	MATCH_SRL, MASK_SRL,		m_op },
+	{ "sra",	"d,s,t",	MATCH_SRA, MASK_SRA,		m_op },
+	{ "or",		"d,s,t",	MATCH_OR, MASK_OR,		m_op },
+	{ "and",	"d,s,t",	MATCH_AND, MASK_AND,		m_op },
+	{ "addiw",	"d,s,j",	MATCH_ADDIW, MASK_ADDIW,	m_op },
+	{ "slliw",	"d,s,<",	MATCH_SLLIW, MASK_SLLIW,	m_op },
+	{ "srliw",	"d,s,<",	MATCH_SRLIW, MASK_SRLIW,	m_op },
+	{ "sraiw",	"d,s,<",	MATCH_SRAIW, MASK_SRAIW,	m_op },
+	{ "addw",	"d,s,t",	MATCH_ADDW, MASK_ADDW,		m_op },
+	{ "subw",	"d,s,t",	MATCH_SUBW, MASK_SUBW,		m_op },
+	{ "sllw",	"d,s,t",	MATCH_SLLW, MASK_SLLW,		m_op },
+	{ "srlw",	"d,s,t",	MATCH_SRLW, MASK_SRLW,		m_op },
+	{ "sraw",	"d,s,t",	MATCH_SRAW, MASK_SRAW,		m_op },
+	{ "lb",		"d,o(s)",	MATCH_LB, MASK_LB,		m_op },
+	{ "lh",		"d,o(s)",	MATCH_LH, MASK_LH,		m_op },
+	{ "lw",		"d,o(s)",	MATCH_LW, MASK_LW,		m_op },
+	{ "ld",		"d,o(s)",	MATCH_LD, MASK_LD,		m_op },
+	{ "lbu",	"d,o(s)",	MATCH_LBU, MASK_LBU,		m_op },
+	{ "lhu",	"d,o(s)",	MATCH_LHU, MASK_LHU,		m_op },
+	{ "lwu",	"d,o(s)",	MATCH_LWU, MASK_LWU,		m_op },
+	{ "sb",		"t,q(s)",	MATCH_SB, MASK_SB,		m_op },
+	{ "sh",		"t,q(s)",	MATCH_SH, MASK_SH,		m_op },
+	{ "sw",		"t,q(s)",	MATCH_SW, MASK_SW,		m_op },
+	{ "sd",		"t,q(s)",	MATCH_SD, MASK_SD,		m_op },
 	{ "fence",	"P,Q",		MATCH_FENCE, MASK_FENCE,	m_op },
 	{ "fence.i",	"",		MATCH_FENCE_I, MASK_FENCE_I,	m_op },
-	{ "mul",	"d,s,t", 	MATCH_MUL, MASK_MUL,		m_op },
-	{ "mulh",	"d,s,t", 	MATCH_MULH, MASK_MULH,		m_op },
-	{ "mulhsu",	"d,s,t", 	MATCH_MULHSU, MASK_MULHSU,	m_op },
-	{ "mulhu",	"d,s,t", 	MATCH_MULHU, MASK_MULHU,	m_op },
-	{ "div",	"d,s,t", 	MATCH_DIV, MASK_DIV,		m_op },
-	{ "divu",	"d,s,t", 	MATCH_DIVU, MASK_DIVU,		m_op },
-	{ "rem",	"d,s,t", 	MATCH_REM, MASK_REM,		m_op },
-	{ "remu",	"d,s,t", 	MATCH_REMU, MASK_REMU,		m_op },
-	{ "mulw",	"d,s,t", 	MATCH_MULW, MASK_MULW,		m_op },
-	{ "divw",	"d,s,t", 	MATCH_DIVW, MASK_DIVW,		m_op },
-	{ "divuw",	"d,s,t", 	MATCH_DIVUW, MASK_DIVUW,	m_op },
-	{ "remw",	"d,s,t", 	MATCH_REMW, MASK_REMW,		m_op },
-	{ "remuw",	"d,s,t", 	MATCH_REMUW, MASK_REMUW,	m_op },
-	{ "amoadd.w",	"d,t,0(s)", 	MATCH_AMOADD_W, MASK_AMOADD_W,	m_op },
-	{ "amoxor.w",	"d,t,0(s)", 	MATCH_AMOXOR_W, MASK_AMOXOR_W,	m_op },
-	{ "amoor.w",	"d,t,0(s)", 	MATCH_AMOOR_W, MASK_AMOOR_W,	m_op },
-	{ "amoand.w",	"d,t,0(s)", 	MATCH_AMOAND_W, MASK_AMOAND_W,	m_op },
-	{ "amomin.w",	"d,t,0(s)", 	MATCH_AMOMIN_W, MASK_AMOMIN_W,	m_op },
-	{ "amomax.w",	"d,t,0(s)", 	MATCH_AMOMAX_W, MASK_AMOMAX_W,	m_op },
-	{ "amominu.w",	"d,t,0(s)", 	MATCH_AMOMINU_W, MASK_AMOMINU_W,m_op },
-	{ "amomaxu.w",	"d,t,0(s)", 	MATCH_AMOMAXU_W, MASK_AMOMAXU_W,m_op },
-	{ "amoswap.w",	"d,t,0(s)", 	MATCH_AMOSWAP_W, MASK_AMOSWAP_W,m_op },
-	{ "lr.w",	"d,0(s)", 	MATCH_LR_W, MASK_LR_W,		m_op },
-	{ "sc.w",	"d,t,0(s)", 	MATCH_SC_W, MASK_SC_W,		m_op },
-	{ "amoadd.d",	"d,t,0(s)", 	MATCH_AMOADD_D, MASK_AMOADD_D,	m_op },
-	{ "amoxor.d",	"d,t,0(s)", 	MATCH_AMOXOR_D, MASK_AMOXOR_D,	m_op },
-	{ "amoor.d",	"d,t,0(s)", 	MATCH_AMOOR_D, MASK_AMOOR_D,	m_op },
-	{ "amoand.d",	"d,t,0(s)", 	MATCH_AMOAND_D, MASK_AMOAND_D,	m_op },
-	{ "amomin.d",	"d,t,0(s)", 	MATCH_AMOMIN_D, MASK_AMOMIN_D,	m_op },
-	{ "amomax.d",	"d,t,0(s)", 	MATCH_AMOMAX_D, MASK_AMOMAX_D,	m_op },
-	{ "amominu.d",	"d,t,0(s)", 	MATCH_AMOMINU_D, MASK_AMOMINU_D,m_op },
-	{ "amomaxu.d",	"d,t,0(s)", 	MATCH_AMOMAXU_D, MASK_AMOMAXU_D,m_op },
-	{ "amoswap.d",	"d,t,0(s)", 	MATCH_AMOSWAP_D, MASK_AMOSWAP_D,m_op },
-	{ "lr.d",	"d,0(s)", 	MATCH_LR_D, MASK_LR_D,		m_op },
-	{ "sc.d",	"d,t,0(s)", 	MATCH_SC_D, MASK_SC_D,		m_op },
-	{ "ecall",	"", 		MATCH_ECALL, MASK_ECALL,	m_op },
-	{ "ebreak",	"", 		MATCH_EBREAK, MASK_EBREAK,	m_op },
-	{ "uret",	"", 		MATCH_URET, MASK_URET,		m_op },
-	{ "sret",	"", 		MATCH_SRET, MASK_SRET,		m_op },
-	{ "mret",	"", 		MATCH_MRET, MASK_MRET,		m_op },
-	{ "dret",	"", 		MATCH_DRET, MASK_DRET,		m_op },
-	{ "sfence.vma",	"", 	MATCH_SFENCE_VMA, MASK_SFENCE_VMA,	m_op },
-	{ "wfi",	"", 		MATCH_WFI, MASK_WFI,		m_op },
-	{ "csrrw",	"d,E,s", 	MATCH_CSRRW, MASK_CSRRW,	m_op },
-	{ "csrrs",	"d,E,s", 	MATCH_CSRRS, MASK_CSRRS,	m_op },
-	{ "csrrc",	"d,E,s", 	MATCH_CSRRC, MASK_CSRRC,	m_op },
-	{ "csrrwi",	"d,E,Z", 	MATCH_CSRRWI, MASK_CSRRWI,	m_op },
-	{ "csrrsi",	"d,E,Z", 	MATCH_CSRRSI, MASK_CSRRSI,	m_op },
-	{ "csrrci",	"d,E,Z", 	MATCH_CSRRCI, MASK_CSRRCI,	m_op },
-	{ "fadd.s",	"D,S,T", 	MATCH_FADD_S, MASK_FADD_S,	m_op },
-	{ "fsub.s",	"D,S,T", 	MATCH_FSUB_S, MASK_FSUB_S,	m_op },
-	{ "fmul.s",	"D,S,T", 	MATCH_FMUL_S, MASK_FMUL_S,	m_op },
-	{ "fdiv.s",	"D,S,T", 	MATCH_FDIV_S, MASK_FDIV_S,	m_op },
-	{ "fsgnj.s",	"D,S,T", 	MATCH_FSGNJ_S, MASK_FSGNJ_S,	m_op },
-	{ "fsgnjn.s",	"D,S,T", 	MATCH_FSGNJN_S, MASK_FSGNJN_S,	m_op },
-	{ "fsgnjx.s",	"D,S,T", 	MATCH_FSGNJX_S, MASK_FSGNJX_S,	m_op },
-	{ "fmin.s",	"D,S,T", 	MATCH_FMIN_S, MASK_FMIN_S,	m_op },
-	{ "fmax.s",	"D,S,T", 	MATCH_FMAX_S, MASK_FMAX_S,	m_op },
-	{ "fsqrt.s",	"D,S", 		MATCH_FSQRT_S, MASK_FSQRT_S,	m_op },
-	{ "fadd.d",	"D,S,T", 	MATCH_FADD_D, MASK_FADD_D,	m_op },
-	{ "fsub.d",	"D,S,T", 	MATCH_FSUB_D, MASK_FSUB_D,	m_op },
-	{ "fmul.d",	"D,S,T", 	MATCH_FMUL_D, MASK_FMUL_D,	m_op },
-	{ "fdiv.d",	"D,S,T", 	MATCH_FDIV_D, MASK_FDIV_D,	m_op },
-	{ "fsgnj.d",	"D,S,T", 	MATCH_FSGNJ_D, MASK_FSGNJ_D,	m_op },
-	{ "fsgnjn.d",	"D,S,T", 	MATCH_FSGNJN_D, MASK_FSGNJN_D,	m_op },
-	{ "fsgnjx.d",	"D,S,T", 	MATCH_FSGNJX_D, MASK_FSGNJX_D,	m_op },
-	{ "fmin.d",	"D,S,T", 	MATCH_FMIN_D, MASK_FMIN_D,	m_op },
-	{ "fmax.d",	"D,S,T", 	MATCH_FMAX_D, MASK_FMAX_D,	m_op },
-	{ "fcvt.s.d",	"D,S", 		MATCH_FCVT_S_D, MASK_FCVT_S_D,	m_op },
-	{ "fcvt.d.s",	"D,S", 		MATCH_FCVT_D_S, MASK_FCVT_D_S,	m_op },
-	{ "fsqrt.d",	"D,S", 		MATCH_FSQRT_D, MASK_FSQRT_D,	m_op },
-	{ "fadd.q",	"D,S,T", 	MATCH_FADD_Q, MASK_FADD_Q,	m_op },
-	{ "fsub.q",	"D,S,T", 	MATCH_FSUB_Q, MASK_FSUB_Q,	m_op },
-	{ "fmul.q",	"D,S,T", 	MATCH_FMUL_Q, MASK_FMUL_Q,	m_op },
-	{ "fdiv.q",	"D,S,T", 	MATCH_FDIV_Q, MASK_FDIV_Q,	m_op },
-	{ "fsgnj.q",	"D,S,T", 	MATCH_FSGNJ_Q, MASK_FSGNJ_Q,	m_op },
-	{ "fsgnjn.q",	"D,S,T", 	MATCH_FSGNJN_Q, MASK_FSGNJN_Q,	m_op },
-	{ "fsgnjx.q",	"D,S,T", 	MATCH_FSGNJX_Q, MASK_FSGNJX_Q,	m_op },
-	{ "fmin.q",	"D,S,T", 	MATCH_FMIN_Q, MASK_FMIN_Q,	m_op },
-	{ "fmax.q",	"D,S,T", 	MATCH_FMAX_Q, MASK_FMAX_Q,	m_op },
-	{ "fcvt.s.q",	"D,S", 		MATCH_FCVT_S_Q, MASK_FCVT_S_Q,	m_op },
-	{ "fcvt.q.s",	"D,S", 		MATCH_FCVT_Q_S, MASK_FCVT_Q_S,	m_op },
-	{ "fcvt.d.q",	"D,S", 		MATCH_FCVT_D_Q, MASK_FCVT_D_Q,	m_op },
-	{ "fcvt.q.d",	"D,S", 		MATCH_FCVT_Q_D, MASK_FCVT_Q_D,	m_op },
-	{ "fsqrt.q",	"D,S", 		MATCH_FSQRT_Q, MASK_FSQRT_Q,	m_op },
-	{ "fle.s",	"d,S,T", 	MATCH_FLE_S, MASK_FLE_S,	m_op },
-	{ "flt.s",	"d,S,T", 	MATCH_FLT_S, MASK_FLT_S,	m_op },
-	{ "feq.s",	"d,S,T", 	MATCH_FEQ_S, MASK_FEQ_S,	m_op },
-	{ "fle.d",	"d,S,T", 	MATCH_FLE_D, MASK_FLE_D,	m_op },
-	{ "flt.d",	"d,S,T", 	MATCH_FLT_D, MASK_FLT_D,	m_op },
-	{ "feq.d",	"d,S,T", 	MATCH_FEQ_D, MASK_FEQ_D,	m_op },
-	{ "fle.q",	"d,S,T", 	MATCH_FLE_Q, MASK_FLE_Q,	m_op },
-	{ "flt.q",	"d,S,T", 	MATCH_FLT_Q, MASK_FLT_Q,	m_op },
-	{ "feq.q",	"d,S,T", 	MATCH_FEQ_Q, MASK_FEQ_Q,	m_op },
-	{ "fcvt.w.s",	"d,S", 		MATCH_FCVT_W_S, MASK_FCVT_W_S,	m_op },
-	{ "fcvt.wu.s",	"d,S", 		MATCH_FCVT_WU_S, MASK_FCVT_WU_S,m_op },
-	{ "fcvt.l.s",	"d,S", 		MATCH_FCVT_L_S, MASK_FCVT_L_S,	m_op },
-	{ "fcvt.lu.s",	"d,S", 		MATCH_FCVT_LU_S, MASK_FCVT_LU_S,m_op },
-	{ "fmv.x.w",	"d,S", 		MATCH_FMV_X_W, MASK_FMV_X_W,	m_op },
-	{ "fclass.s",	"d,S", 		MATCH_FCLASS_S, MASK_FCLASS_S,	m_op },
-	{ "fcvt.w.d",	"d,S", 		MATCH_FCVT_W_D, MASK_FCVT_W_D,	m_op },
-	{ "fcvt.wu.d",	"d,S", 		MATCH_FCVT_WU_D, MASK_FCVT_WU_D,m_op },
-	{ "fcvt.l.d",	"d,S", 		MATCH_FCVT_L_D, MASK_FCVT_L_D,	m_op },
-	{ "fcvt.lu.d",	"d,S", 		MATCH_FCVT_LU_D, MASK_FCVT_LU_D,m_op },
-	{ "fmv.x.d",	"d,S", 		MATCH_FMV_X_D, MASK_FMV_X_D,	m_op },
-	{ "fclass.d",	"d,S", 		MATCH_FCLASS_D, MASK_FCLASS_D,	m_op },
-	{ "fcvt.w.q",	"d,S", 		MATCH_FCVT_W_Q, MASK_FCVT_W_Q,	m_op },
-	{ "fcvt.wu.q",	"d,S", 		MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q,m_op },
-	{ "fcvt.l.q",	"d,S", 		MATCH_FCVT_L_Q, MASK_FCVT_L_Q,	m_op },
-	{ "fcvt.lu.q",	"d,S", 		MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q,m_op },
+	{ "mul",	"d,s,t",	MATCH_MUL, MASK_MUL,		m_op },
+	{ "mulh",	"d,s,t",	MATCH_MULH, MASK_MULH,		m_op },
+	{ "mulhsu",	"d,s,t",	MATCH_MULHSU, MASK_MULHSU,	m_op },
+	{ "mulhu",	"d,s,t",	MATCH_MULHU, MASK_MULHU,	m_op },
+	{ "div",	"d,s,t",	MATCH_DIV, MASK_DIV,		m_op },
+	{ "divu",	"d,s,t",	MATCH_DIVU, MASK_DIVU,		m_op },
+	{ "rem",	"d,s,t",	MATCH_REM, MASK_REM,		m_op },
+	{ "remu",	"d,s,t",	MATCH_REMU, MASK_REMU,		m_op },
+	{ "mulw",	"d,s,t",	MATCH_MULW, MASK_MULW,		m_op },
+	{ "divw",	"d,s,t",	MATCH_DIVW, MASK_DIVW,		m_op },
+	{ "divuw",	"d,s,t",	MATCH_DIVUW, MASK_DIVUW,	m_op },
+	{ "remw",	"d,s,t",	MATCH_REMW, MASK_REMW,		m_op },
+	{ "remuw",	"d,s,t",	MATCH_REMUW, MASK_REMUW,	m_op },
+	{ "amoadd.w",	"d,t,0(s)",	MATCH_AMOADD_W, MASK_AMOADD_W,	m_op },
+	{ "amoxor.w",	"d,t,0(s)",	MATCH_AMOXOR_W, MASK_AMOXOR_W,	m_op },
+	{ "amoor.w",	"d,t,0(s)",	MATCH_AMOOR_W, MASK_AMOOR_W,	m_op },
+	{ "amoand.w",	"d,t,0(s)",	MATCH_AMOAND_W, MASK_AMOAND_W,	m_op },
+	{ "amomin.w",	"d,t,0(s)",	MATCH_AMOMIN_W, MASK_AMOMIN_W,	m_op },
+	{ "amomax.w",	"d,t,0(s)",	MATCH_AMOMAX_W, MASK_AMOMAX_W,	m_op },
+	{ "amominu.w",	"d,t,0(s)",	MATCH_AMOMINU_W, MASK_AMOMINU_W,m_op },
+	{ "amomaxu.w",	"d,t,0(s)",	MATCH_AMOMAXU_W, MASK_AMOMAXU_W,m_op },
+	{ "amoswap.w",	"d,t,0(s)",	MATCH_AMOSWAP_W, MASK_AMOSWAP_W,m_op },
+	{ "lr.w",	"d,0(s)",	MATCH_LR_W, MASK_LR_W,		m_op },
+	{ "sc.w",	"d,t,0(s)",	MATCH_SC_W, MASK_SC_W,		m_op },
+	{ "amoadd.d",	"d,t,0(s)",	MATCH_AMOADD_D, MASK_AMOADD_D,	m_op },
+	{ "amoxor.d",	"d,t,0(s)",	MATCH_AMOXOR_D, MASK_AMOXOR_D,	m_op },
+	{ "amoor.d",	"d,t,0(s)",	MATCH_AMOOR_D, MASK_AMOOR_D,	m_op },
+	{ "amoand.d",	"d,t,0(s)",	MATCH_AMOAND_D, MASK_AMOAND_D,	m_op },
+	{ "amomin.d",	"d,t,0(s)",	MATCH_AMOMIN_D, MASK_AMOMIN_D,	m_op },
+	{ "amomax.d",	"d,t,0(s)",	MATCH_AMOMAX_D, MASK_AMOMAX_D,	m_op },
+	{ "amominu.d",	"d,t,0(s)",	MATCH_AMOMINU_D, MASK_AMOMINU_D,m_op },
+	{ "amomaxu.d",	"d,t,0(s)",	MATCH_AMOMAXU_D, MASK_AMOMAXU_D,m_op },
+	{ "amoswap.d",	"d,t,0(s)",	MATCH_AMOSWAP_D, MASK_AMOSWAP_D,m_op },
+	{ "lr.d",	"d,0(s)",	MATCH_LR_D, MASK_LR_D,		m_op },
+	{ "sc.d",	"d,t,0(s)",	MATCH_SC_D, MASK_SC_D,		m_op },
+	{ "ecall",	"",		MATCH_ECALL, MASK_ECALL,	m_op },
+	{ "ebreak",	"",		MATCH_EBREAK, MASK_EBREAK,	m_op },
+	{ "uret",	"",		MATCH_URET, MASK_URET,		m_op },
+	{ "sret",	"",		MATCH_SRET, MASK_SRET,		m_op },
+	{ "mret",	"",		MATCH_MRET, MASK_MRET,		m_op },
+	{ "dret",	"",		MATCH_DRET, MASK_DRET,		m_op },
+	{ "sfence.vma",	"",		MATCH_SFENCE_VMA, MASK_SFENCE_VMA, m_op },
+	{ "wfi",	"",		MATCH_WFI, MASK_WFI,		m_op },
+	{ "csrrw",	"d,E,s",	MATCH_CSRRW, MASK_CSRRW,	m_op },
+	{ "csrrs",	"d,E,s",	MATCH_CSRRS, MASK_CSRRS,	m_op },
+	{ "csrrc",	"d,E,s",	MATCH_CSRRC, MASK_CSRRC,	m_op },
+	{ "csrrwi",	"d,E,Z",	MATCH_CSRRWI, MASK_CSRRWI,	m_op },
+	{ "csrrsi",	"d,E,Z",	MATCH_CSRRSI, MASK_CSRRSI,	m_op },
+	{ "csrrci",	"d,E,Z",	MATCH_CSRRCI, MASK_CSRRCI,	m_op },
+	{ "fadd.s",	"D,S,T",	MATCH_FADD_S, MASK_FADD_S,	m_op },
+	{ "fsub.s",	"D,S,T",	MATCH_FSUB_S, MASK_FSUB_S,	m_op },
+	{ "fmul.s",	"D,S,T",	MATCH_FMUL_S, MASK_FMUL_S,	m_op },
+	{ "fdiv.s",	"D,S,T",	MATCH_FDIV_S, MASK_FDIV_S,	m_op },
+	{ "fsgnj.s",	"D,S,T",	MATCH_FSGNJ_S, MASK_FSGNJ_S,	m_op },
+	{ "fsgnjn.s",	"D,S,T",	MATCH_FSGNJN_S, MASK_FSGNJN_S,	m_op },
+	{ "fsgnjx.s",	"D,S,T",	MATCH_FSGNJX_S, MASK_FSGNJX_S,	m_op },
+	{ "fmin.s",	"D,S,T",	MATCH_FMIN_S, MASK_FMIN_S,	m_op },
+	{ "fmax.s",	"D,S,T",	MATCH_FMAX_S, MASK_FMAX_S,	m_op },
+	{ "fsqrt.s",	"D,S",		MATCH_FSQRT_S, MASK_FSQRT_S,	m_op },
+	{ "fadd.d",	"D,S,T",	MATCH_FADD_D, MASK_FADD_D,	m_op },
+	{ "fsub.d",	"D,S,T",	MATCH_FSUB_D, MASK_FSUB_D,	m_op },
+	{ "fmul.d",	"D,S,T",	MATCH_FMUL_D, MASK_FMUL_D,	m_op },
+	{ "fdiv.d",	"D,S,T",	MATCH_FDIV_D, MASK_FDIV_D,	m_op },
+	{ "fsgnj.d",	"D,S,T",	MATCH_FSGNJ_D, MASK_FSGNJ_D,	m_op },
+	{ "fsgnjn.d",	"D,S,T",	MATCH_FSGNJN_D, MASK_FSGNJN_D,	m_op },
+	{ "fsgnjx.d",	"D,S,T",	MATCH_FSGNJX_D, MASK_FSGNJX_D,	m_op },
+	{ "fmin.d",	"D,S,T",	MATCH_FMIN_D, MASK_FMIN_D,	m_op },
+	{ "fmax.d",	"D,S,T",	MATCH_FMAX_D, MASK_FMAX_D,	m_op },
+	{ "fcvt.s.d",	"D,S",		MATCH_FCVT_S_D, MASK_FCVT_S_D,	m_op },
+	{ "fcvt.d.s",	"D,S",		MATCH_FCVT_D_S, MASK_FCVT_D_S,	m_op },
+	{ "fsqrt.d",	"D,S",		MATCH_FSQRT_D, MASK_FSQRT_D,	m_op },
+	{ "fadd.q",	"D,S,T",	MATCH_FADD_Q, MASK_FADD_Q,	m_op },
+	{ "fsub.q",	"D,S,T",	MATCH_FSUB_Q, MASK_FSUB_Q,	m_op },
+	{ "fmul.q",	"D,S,T",	MATCH_FMUL_Q, MASK_FMUL_Q,	m_op },
+	{ "fdiv.q",	"D,S,T",	MATCH_FDIV_Q, MASK_FDIV_Q,	m_op },
+	{ "fsgnj.q",	"D,S,T",	MATCH_FSGNJ_Q, MASK_FSGNJ_Q,	m_op },
+	{ "fsgnjn.q",	"D,S,T",	MATCH_FSGNJN_Q, MASK_FSGNJN_Q,	m_op },
+	{ "fsgnjx.q",	"D,S,T",	MATCH_FSGNJX_Q, MASK_FSGNJX_Q,	m_op },
+	{ "fmin.q",	"D,S,T",	MATCH_FMIN_Q, MASK_FMIN_Q,	m_op },
+	{ "fmax.q",	"D,S,T",	MATCH_FMAX_Q, MASK_FMAX_Q,	m_op },
+	{ "fcvt.s.q",	"D,S",		MATCH_FCVT_S_Q, MASK_FCVT_S_Q,	m_op },
+	{ "fcvt.q.s",	"D,S",		MATCH_FCVT_Q_S, MASK_FCVT_Q_S,	m_op },
+	{ "fcvt.d.q",	"D,S",		MATCH_FCVT_D_Q, MASK_FCVT_D_Q,	m_op },
+	{ "fcvt.q.d",	"D,S",		MATCH_FCVT_Q_D, MASK_FCVT_Q_D,	m_op },
+	{ "fsqrt.q",	"D,S",		MATCH_FSQRT_Q, MASK_FSQRT_Q,	m_op },
+	{ "fle.s",	"d,S,T",	MATCH_FLE_S, MASK_FLE_S,	m_op },
+	{ "flt.s",	"d,S,T",	MATCH_FLT_S, MASK_FLT_S,	m_op },
+	{ "feq.s",	"d,S,T",	MATCH_FEQ_S, MASK_FEQ_S,	m_op },
+	{ "fle.d",	"d,S,T",	MATCH_FLE_D, MASK_FLE_D,	m_op },
+	{ "flt.d",	"d,S,T",	MATCH_FLT_D, MASK_FLT_D,	m_op },
+	{ "feq.d",	"d,S,T",	MATCH_FEQ_D, MASK_FEQ_D,	m_op },
+	{ "fle.q",	"d,S,T",	MATCH_FLE_Q, MASK_FLE_Q,	m_op },
+	{ "flt.q",	"d,S,T",	MATCH_FLT_Q, MASK_FLT_Q,	m_op },
+	{ "feq.q",	"d,S,T",	MATCH_FEQ_Q, MASK_FEQ_Q,	m_op },
+	{ "fcvt.w.s",	"d,S",		MATCH_FCVT_W_S, MASK_FCVT_W_S,	m_op },
+	{ "fcvt.wu.s",	"d,S",		MATCH_FCVT_WU_S, MASK_FCVT_WU_S,m_op },
+	{ "fcvt.l.s",	"d,S",		MATCH_FCVT_L_S, MASK_FCVT_L_S,	m_op },
+	{ "fcvt.lu.s",	"d,S",		MATCH_FCVT_LU_S, MASK_FCVT_LU_S,m_op },
+	{ "fmv.x.w",	"d,S",		MATCH_FMV_X_W, MASK_FMV_X_W,	m_op },
+	{ "fclass.s",	"d,S",		MATCH_FCLASS_S, MASK_FCLASS_S,	m_op },
+	{ "fcvt.w.d",	"d,S",		MATCH_FCVT_W_D, MASK_FCVT_W_D,	m_op },
+	{ "fcvt.wu.d",	"d,S",		MATCH_FCVT_WU_D, MASK_FCVT_WU_D,m_op },
+	{ "fcvt.l.d",	"d,S",		MATCH_FCVT_L_D, MASK_FCVT_L_D,	m_op },
+	{ "fcvt.lu.d",	"d,S",		MATCH_FCVT_LU_D, MASK_FCVT_LU_D,m_op },
+	{ "fmv.x.d",	"d,S",		MATCH_FMV_X_D, MASK_FMV_X_D,	m_op },
+	{ "fclass.d",	"d,S",		MATCH_FCLASS_D, MASK_FCLASS_D,	m_op },
+	{ "fcvt.w.q",	"d,S",		MATCH_FCVT_W_Q, MASK_FCVT_W_Q,	m_op },
+	{ "fcvt.wu.q",	"d,S",		MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q,m_op },
+	{ "fcvt.l.q",	"d,S",		MATCH_FCVT_L_Q, MASK_FCVT_L_Q,	m_op },
+	{ "fcvt.lu.q",	"d,S",		MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q,m_op },
 #ifdef RV128Q
-	{ "fmv.x.q",	"d,S", 		MATCH_FMV_X_Q, MASK_FMV_X_Q,	m_op },
+	{ "fmv.x.q",	"d,S",		MATCH_FMV_X_Q, MASK_FMV_X_Q,	m_op },
 #endif
-	{ "fclass.q",	"d,S", 		MATCH_FCLASS_Q, MASK_FCLASS_Q,	m_op },
-	{ "fcvt.s.w",	"D,s", 		MATCH_FCVT_S_W, MASK_FCVT_S_W,	m_op },
-	{ "fcvt.s.wu",	"D,s", 		MATCH_FCVT_S_WU, MASK_FCVT_S_WU,m_op },
-	{ "fcvt.s.l",	"D,s", 		MATCH_FCVT_S_L, MASK_FCVT_S_L,	m_op },
-	{ "fcvt.s.lu",	"D,s", 		MATCH_FCVT_S_LU, MASK_FCVT_S_LU,m_op },
-	{ "fmv.w.x",	"D,s", 		MATCH_FMV_W_X, MASK_FMV_W_X,	m_op },
-	{ "fcvt.d.w",	"D,s", 		MATCH_FCVT_D_W, MASK_FCVT_D_W,	m_op },
-	{ "fcvt.d.wu",	"D,s", 		MATCH_FCVT_D_WU, MASK_FCVT_D_WU,m_op },
-	{ "fcvt.d.l",	"D,s", 		MATCH_FCVT_D_L, MASK_FCVT_D_L,	m_op },
-	{ "fcvt.d.lu",	"D,s", 		MATCH_FCVT_D_LU, MASK_FCVT_D_LU,m_op },
-	{ "fmv.d.x",	"D,s", 		MATCH_FMV_D_X, MASK_FMV_D_X,	m_op },
-	{ "fcvt.q.w",	"D,s", 		MATCH_FCVT_Q_W, MASK_FCVT_Q_W,	m_op },
-	{ "fcvt.q.wu",	"D,s", 		MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU,m_op },
-	{ "fcvt.q.l",	"D,s", 		MATCH_FCVT_Q_L, MASK_FCVT_Q_L,	m_op },
-	{ "fcvt.q.lu",	"D,s", 		MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU,m_op },
+	{ "fclass.q",	"d,S",		MATCH_FCLASS_Q, MASK_FCLASS_Q,	m_op },
+	{ "fcvt.s.w",	"D,s",		MATCH_FCVT_S_W, MASK_FCVT_S_W,	m_op },
+	{ "fcvt.s.wu",	"D,s",		MATCH_FCVT_S_WU, MASK_FCVT_S_WU,m_op },
+	{ "fcvt.s.l",	"D,s",		MATCH_FCVT_S_L, MASK_FCVT_S_L,	m_op },
+	{ "fcvt.s.lu",	"D,s",		MATCH_FCVT_S_LU, MASK_FCVT_S_LU,m_op },
+	{ "fmv.w.x",	"D,s",		MATCH_FMV_W_X, MASK_FMV_W_X,	m_op },
+	{ "fcvt.d.w",	"D,s",		MATCH_FCVT_D_W, MASK_FCVT_D_W,	m_op },
+	{ "fcvt.d.wu",	"D,s",		MATCH_FCVT_D_WU, MASK_FCVT_D_WU,m_op },
+	{ "fcvt.d.l",	"D,s",		MATCH_FCVT_D_L, MASK_FCVT_D_L,	m_op },
+	{ "fcvt.d.lu",	"D,s",		MATCH_FCVT_D_LU, MASK_FCVT_D_LU,m_op },
+	{ "fmv.d.x",	"D,s",		MATCH_FMV_D_X, MASK_FMV_D_X,	m_op },
+	{ "fcvt.q.w",	"D,s",		MATCH_FCVT_Q_W, MASK_FCVT_Q_W,	m_op },
+	{ "fcvt.q.wu",	"D,s",		MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU,m_op },
+	{ "fcvt.q.l",	"D,s",		MATCH_FCVT_Q_L, MASK_FCVT_Q_L,	m_op },
+	{ "fcvt.q.lu",	"D,s",		MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU,m_op },
 #ifdef RV128Q
-	{ "fmv.q.x",	"D,s", 		MATCH_FMV_Q_X, MASK_FMV_Q_X,	m_op },
+	{ "fmv.q.x",	"D,s",		MATCH_FMV_Q_X, MASK_FMV_Q_X,	m_op },
 #endif
-	{ "flw",	"D,o(s)", 	MATCH_FLW, MASK_FLW,		m_op },
-	{ "fld",	"D,o(s)", 	MATCH_FLD, MASK_FLD,		m_op },
-	{ "flq",	"D,o(s)", 	MATCH_FLQ, MASK_FLQ,		m_op },
-	{ "fsw",	"T,q(s)", 	MATCH_FSW, MASK_FSW,		m_op },
-	{ "fsd",	"T,q(s)", 	MATCH_FSD, MASK_FSD,		m_op },
-	{ "fsq",	"T,q(s)", 	MATCH_FSQ, MASK_FSQ,		m_op },
-	{ "fmadd.s",	"D,S,T,R", 	MATCH_FMADD_S, MASK_FMADD_S,	m_op },
-	{ "fmsub.s",	"D,S,T,R", 	MATCH_FMSUB_S, MASK_FMSUB_S,	m_op },
-	{ "fnmsub.s",	"D,S,T,R", 	MATCH_FNMSUB_S, MASK_FNMSUB_S,	m_op },
-	{ "fnmadd.s",	"D,S,T,R", 	MATCH_FNMADD_S, MASK_FNMADD_S,	m_op },
-	{ "fmadd.d",	"D,S,T,R", 	MATCH_FMADD_D, MASK_FMADD_D,	m_op },
-	{ "fmsub.d",	"D,S,T,R", 	MATCH_FMSUB_D, MASK_FMSUB_D,	m_op },
-	{ "fnmsub.d",	"D,S,T,R", 	MATCH_FNMSUB_D, MASK_FNMSUB_D,	m_op },
-	{ "fnmadd.d",	"D,S,T,R", 	MATCH_FNMADD_D, MASK_FNMADD_D,	m_op },
-	{ "fmadd.q",	"D,S,T,R", 	MATCH_FMADD_Q, MASK_FMADD_Q,	m_op },
-	{ "fmsub.q",	"D,S,T,R", 	MATCH_FMSUB_Q, MASK_FMSUB_Q,	m_op },
-	{ "fnmsub.q",	"D,S,T,R", 	MATCH_FNMSUB_Q, MASK_FNMSUB_Q,	m_op },
-	{ "fnmadd.q",	"D,S,T,R", 	MATCH_FNMADD_Q, MASK_FNMADD_Q,	m_op },
+	{ "flw",	"D,o(s)",	MATCH_FLW, MASK_FLW,		m_op },
+	{ "fld",	"D,o(s)",	MATCH_FLD, MASK_FLD,		m_op },
+	{ "flq",	"D,o(s)",	MATCH_FLQ, MASK_FLQ,		m_op },
+	{ "fsw",	"T,q(s)",	MATCH_FSW, MASK_FSW,		m_op },
+	{ "fsd",	"T,q(s)",	MATCH_FSD, MASK_FSD,		m_op },
+	{ "fsq",	"T,q(s)",	MATCH_FSQ, MASK_FSQ,		m_op },
+	{ "fmadd.s",	"D,S,T,R",	MATCH_FMADD_S, MASK_FMADD_S,	m_op },
+	{ "fmsub.s",	"D,S,T,R",	MATCH_FMSUB_S, MASK_FMSUB_S,	m_op },
+	{ "fnmsub.s",	"D,S,T,R",	MATCH_FNMSUB_S, MASK_FNMSUB_S,	m_op },
+	{ "fnmadd.s",	"D,S,T,R",	MATCH_FNMADD_S, MASK_FNMADD_S,	m_op },
+	{ "fmadd.d",	"D,S,T,R",	MATCH_FMADD_D, MASK_FMADD_D,	m_op },
+	{ "fmsub.d",	"D,S,T,R",	MATCH_FMSUB_D, MASK_FMSUB_D,	m_op },
+	{ "fnmsub.d",	"D,S,T,R",	MATCH_FNMSUB_D, MASK_FNMSUB_D,	m_op },
+	{ "fnmadd.d",	"D,S,T,R",	MATCH_FNMADD_D, MASK_FNMADD_D,	m_op },
+	{ "fmadd.q",	"D,S,T,R",	MATCH_FMADD_Q, MASK_FMADD_Q,	m_op },
+	{ "fmsub.q",	"D,S,T,R",	MATCH_FMSUB_Q, MASK_FMSUB_Q,	m_op },
+	{ "fnmsub.q",	"D,S,T,R",	MATCH_FNMSUB_Q, MASK_FNMSUB_Q,	m_op },
+	{ "fnmadd.q",	"D,S,T,R",	MATCH_FNMADD_Q, MASK_FNMADD_Q,	m_op },
 	{ NULL, NULL, 0, 0, NULL },
 };
 
@@ -307,48 +307,48 @@ static struct riscv_op riscv_c_opcodes[] = {
 	{ "ret","",MATCH_C_JR | (X_RA << RD_SHIFT), MASK_C_JR | RD_MASK, m_op},
 
 	/* C-Compressed ISA Extension Instructions */
-	{ "c.nop",	"", 		MATCH_C_NOP, MASK_C_NOP,	m_op },
-	{ "c.ebreak",	"", 		MATCH_C_EBREAK, MASK_C_EBREAK,	m_op },
-	{ "c.jr",	"d", 		MATCH_C_JR, MASK_C_JR,		m_op },
-	{ "c.jalr",	"d", 		MATCH_C_JALR, MASK_C_JALR,	m_op },
-	{ "c.jal",	"Ca", 		MATCH_C_JAL, MASK_C_JAL,	m_op },
-	{ "c.ld",	"Ct,Cl(Cs)", 	MATCH_C_LD, MASK_C_LD,		m_op },
-	{ "c.sd",	"Ct,Cl(Cs)", 	MATCH_C_SD, MASK_C_SD,		m_op },
-	{ "c.addiw",	"d,Co", 	MATCH_C_ADDIW, MASK_C_ADDIW,	m_op },
-	{ "c.ldsp",	"d,Cn(Cc)", 	MATCH_C_LDSP, MASK_C_LDSP,	m_op },
-	{ "c.sdsp",	"CV,CN(Cc)", 	MATCH_C_SDSP, MASK_C_SDSP,	m_op },
-	{ "c.addi4spn",	"", 	MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN,	m_op },
-	{ "c.addi16sp",	"", 	MATCH_C_ADDI16SP, MASK_C_ADDI16SP,	m_op },
-	{ "c.fld",	"CD,Cl(Cs)", 	MATCH_C_FLD, MASK_C_FLD,	m_op },
-	{ "c.lw",	"Ct,Ck(Cs)", 	MATCH_C_LW, MASK_C_LW,		m_op },
-	{ "c.flw",	"CD,Ck(Cs)", 	MATCH_C_FLW, MASK_C_FLW,	m_op },
-	{ "c.fsd",	"CD,Cl(Cs)", 	MATCH_C_FSD, MASK_C_FSD,	m_op },
-	{ "c.sw",	"Ct,Ck(Cs)", 	MATCH_C_SW, MASK_C_SW,		m_op },
-	{ "c.fsw",	"CD,Ck(Cs)", 	MATCH_C_FSW, MASK_C_FSW,	m_op },
-	{ "c.addi",	"d,Co", 	MATCH_C_ADDI, MASK_C_ADDI,	m_op },
-	{ "c.li",	"d,Co", 	MATCH_C_LI, MASK_C_LI,		m_op },
-	{ "c.lui",	"d,Cu", 	MATCH_C_LUI, MASK_C_LUI,	m_op },
-	{ "c.srli",	"Cs,C>", 	MATCH_C_SRLI, MASK_C_SRLI,	m_op },
-	{ "c.srai",	"Cs,C>", 	MATCH_C_SRAI, MASK_C_SRAI,	m_op },
-	{ "c.andi",	"Cs,Co", 	MATCH_C_ANDI, MASK_C_ANDI,	m_op },
-	{ "c.sub",	"Cs,Ct", 	MATCH_C_SUB, MASK_C_SUB,	m_op },
-	{ "c.xor",	"Cs,Ct", 	MATCH_C_XOR, MASK_C_XOR,	m_op },
-	{ "c.or",	"Cs,Ct", 	MATCH_C_OR, MASK_C_OR,		m_op },
-	{ "c.and",	"Cs,Ct", 	MATCH_C_AND, MASK_C_AND,	m_op },
-	{ "c.subw",	"Cs,Ct", 	MATCH_C_SUBW, MASK_C_SUBW,	m_op },
-	{ "c.addw",	"Cs,Ct", 	MATCH_C_ADDW, MASK_C_ADDW,	m_op },
-	{ "c.j",	"Ca", 		MATCH_C_J, MASK_C_J,		m_op },
-	{ "c.beqz",	"Cs,Cp", 	MATCH_C_BEQZ, MASK_C_BEQZ,	m_op },
-	{ "c.bnez",	"Cs,Cp", 	MATCH_C_BNEZ, MASK_C_BNEZ,	m_op },
-	{ "c.slli",	"d,C>", 	MATCH_C_SLLI, MASK_C_SLLI,	m_op },
-	{ "c.fldsp",	"D,Cn(Cc)", 	MATCH_C_FLDSP, MASK_C_FLDSP,	m_op },
-	{ "c.lwsp",	"d,Cm(Cc)", 	MATCH_C_LWSP, MASK_C_LWSP,	m_op },
-	{ "c.flwsp",	"D,Cm(Cc)", 	MATCH_C_FLWSP, MASK_C_FLWSP,	m_op },
-	{ "c.mv",	"d,CV", 	MATCH_C_MV, MASK_C_MV,		m_op },
-	{ "c.add",	"d,CV", 	MATCH_C_ADD, MASK_C_ADD,	m_op },
-	{ "c.fsdsp",	"CT,CN(Cc)", 	MATCH_C_FSDSP, MASK_C_FSDSP,	m_op },
-	{ "c.swsp",	"CV,CM(Cc)", 	MATCH_C_SWSP, MASK_C_SWSP,	m_op },
-	{ "c.fswsp",	"CT,CM(Cc)", 	MATCH_C_FSWSP, MASK_C_FSWSP,	m_op },
+	{ "c.nop",	"",		MATCH_C_NOP, MASK_C_NOP,	m_op },
+	{ "c.ebreak",	"",		MATCH_C_EBREAK, MASK_C_EBREAK,	m_op },
+	{ "c.jr",	"d",		MATCH_C_JR, MASK_C_JR,		m_op },
+	{ "c.jalr",	"d",		MATCH_C_JALR, MASK_C_JALR,	m_op },
+	{ "c.jal",	"Ca",		MATCH_C_JAL, MASK_C_JAL,	m_op },
+	{ "c.ld",	"Ct,Cl(Cs)",	MATCH_C_LD, MASK_C_LD,		m_op },
+	{ "c.sd",	"Ct,Cl(Cs)",	MATCH_C_SD, MASK_C_SD,		m_op },
+	{ "c.addiw",	"d,Co",		MATCH_C_ADDIW, MASK_C_ADDIW,	m_op },
+	{ "c.ldsp",	"d,Cn(Cc)",	MATCH_C_LDSP, MASK_C_LDSP,	m_op },
+	{ "c.sdsp",	"CV,CN(Cc)",	MATCH_C_SDSP, MASK_C_SDSP,	m_op },
+	{ "c.addi4spn",	"",		MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, m_op },
+	{ "c.addi16sp",	"",		MATCH_C_ADDI16SP, MASK_C_ADDI16SP, m_op },
+	{ "c.fld",	"CD,Cl(Cs)",	MATCH_C_FLD, MASK_C_FLD,	m_op },
+	{ "c.lw",	"Ct,Ck(Cs)",	MATCH_C_LW, MASK_C_LW,		m_op },
+	{ "c.flw",	"CD,Ck(Cs)",	MATCH_C_FLW, MASK_C_FLW,	m_op },
+	{ "c.fsd",	"CD,Cl(Cs)",	MATCH_C_FSD, MASK_C_FSD,	m_op },
+	{ "c.sw",	"Ct,Ck(Cs)",	MATCH_C_SW, MASK_C_SW,		m_op },
+	{ "c.fsw",	"CD,Ck(Cs)",	MATCH_C_FSW, MASK_C_FSW,	m_op },
+	{ "c.addi",	"d,Co",		MATCH_C_ADDI, MASK_C_ADDI,	m_op },
+	{ "c.li",	"d,Co",		MATCH_C_LI, MASK_C_LI,		m_op },
+	{ "c.lui",	"d,Cu",		MATCH_C_LUI, MASK_C_LUI,	m_op },
+	{ "c.srli",	"Cs,C>",	MATCH_C_SRLI, MASK_C_SRLI,	m_op },
+	{ "c.srai",	"Cs,C>",	MATCH_C_SRAI, MASK_C_SRAI,	m_op },
+	{ "c.andi",	"Cs,Co",	MATCH_C_ANDI, MASK_C_ANDI,	m_op },
+	{ "c.sub",	"Cs,Ct",	MATCH_C_SUB, MASK_C_SUB,	m_op },
+	{ "c.xor",	"Cs,Ct",	MATCH_C_XOR, MASK_C_XOR,	m_op },
+	{ "c.or",	"Cs,Ct",	MATCH_C_OR, MASK_C_OR,		m_op },
+	{ "c.and",	"Cs,Ct",	MATCH_C_AND, MASK_C_AND,	m_op },
+	{ "c.subw",	"Cs,Ct",	MATCH_C_SUBW, MASK_C_SUBW,	m_op },
+	{ "c.addw",	"Cs,Ct",	MATCH_C_ADDW, MASK_C_ADDW,	m_op },
+	{ "c.j",	"Ca",		MATCH_C_J, MASK_C_J,		m_op },
+	{ "c.beqz",	"Cs,Cp",	MATCH_C_BEQZ, MASK_C_BEQZ,	m_op },
+	{ "c.bnez",	"Cs,Cp",	MATCH_C_BNEZ, MASK_C_BNEZ,	m_op },
+	{ "c.slli",	"d,C>",		MATCH_C_SLLI, MASK_C_SLLI,	m_op },
+	{ "c.fldsp",	"D,Cn(Cc)",	MATCH_C_FLDSP, MASK_C_FLDSP,	m_op },
+	{ "c.lwsp",	"d,Cm(Cc)",	MATCH_C_LWSP, MASK_C_LWSP,	m_op },
+	{ "c.flwsp",	"D,Cm(Cc)",	MATCH_C_FLWSP, MASK_C_FLWSP,	m_op },
+	{ "c.mv",	"d,CV",		MATCH_C_MV, MASK_C_MV,		m_op },
+	{ "c.add",	"d,CV",		MATCH_C_ADD, MASK_C_ADD,	m_op },
+	{ "c.fsdsp",	"CT,CN(Cc)",	MATCH_C_FSDSP, MASK_C_FSDSP,	m_op },
+	{ "c.swsp",	"CV,CM(Cc)",	MATCH_C_SWSP, MASK_C_SWSP,	m_op },
+	{ "c.fswsp",	"CT,CM(Cc)",	MATCH_C_FSWSP, MASK_C_FSWSP,	m_op },
 	{ NULL, NULL, 0, 0, NULL },
 };
 
@@ -500,7 +500,6 @@ oprint(struct riscv_op *op, vaddr_t loc, int insn)
 			if (!p[1])
 				db_printf("%c", *p);
 			break;
-			
 		case 'o':
 			imm = (insn >> 20) & 0xfff;
 			if (imm & (1 << 11))
diff --git a/sys/arch/riscv64/riscv64/db_interface.c b/sys/arch/riscv64/riscv64/db_interface.c
index f0906b86bd6..640aa188f8d 100644
--- a/sys/arch/riscv64/riscv64/db_interface.c
+++ b/sys/arch/riscv64/riscv64/db_interface.c
@@ -85,9 +85,9 @@ struct db_variable db_regs[] = {
 	{ "t6", (long *)&DDB_REGS->tf_t[6], FCN_NULL, }		/* x31 */
 };
 
-extern label_t       *db_recover;
+extern label_t	*db_recover;
 
-struct db_variable * db_eregs = db_regs + nitems(db_regs);
+struct db_variable *db_eregs = db_regs + nitems(db_regs);
 
 #ifdef DDB
 /*
@@ -96,7 +96,7 @@ struct db_variable * db_eregs = db_regs + nitems(db_regs);
 int
 kdb_trap(int type, db_regs_t *regs)
 {
-	int s;	
+	int s;
 
 	switch (type) {
 	case T_BREAKPOINT:	/* breakpoint */
@@ -118,7 +118,7 @@ kdb_trap(int type, db_regs_t *regs)
 	cnpollc(0);
 	db_active--;
 	splx(s);
-	
+
 	*regs = ddb_regs;
 
 	return (1);
@@ -205,13 +205,13 @@ int
 db_trapper(vaddr_t addr, u_int inst, trapframe_t *frame, int fault_code)
 {
 
-        if (fault_code == EXCP_BREAKPOINT) {
-                kdb_trap(T_BREAKPOINT, frame);
-                frame->tf_sepc += 4;
-        } else
-                kdb_trap(-1, frame);
+	if (fault_code == EXCP_BREAKPOINT) {
+		kdb_trap(T_BREAKPOINT, frame);
+		frame->tf_sepc += 4;
+	} else
+		kdb_trap(-1, frame);
 
-        return (0);
+	return (0);
 }
 
 
diff --git a/sys/arch/riscv64/riscv64/fpu.c b/sys/arch/riscv64/riscv64/fpu.c
index c82758ea809..9f7cfead3d9 100644
--- a/sys/arch/riscv64/riscv64/fpu.c
+++ b/sys/arch/riscv64/riscv64/fpu.c
@@ -122,7 +122,7 @@ fpu_save(struct proc *p, struct trapframe *frame)
 
 	/*
 	 * pcb->pcb_fpcpu and ci->ci_fpuproc are still valid
-	 * until some other fpu context steals either the cpu 
+	 * until some other fpu context steals either the cpu
 	 * context or another cpu steals the fpu context.
 	 */
 
diff --git a/sys/arch/riscv64/riscv64/locore.S b/sys/arch/riscv64/riscv64/locore.S
index d18e7b6df76..207dc357540 100644
--- a/sys/arch/riscv64/riscv64/locore.S
+++ b/sys/arch/riscv64/riscv64/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.4 2021/05/11 13:56:28 deraadt Exp $ */
+/* $OpenBSD: locore.S,v 1.5 2021/05/11 14:58:08 deraadt Exp $ */
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
  * All rights reserved.
@@ -54,7 +54,7 @@ _start_kern_bootstrap:
 	lla	gp, __global_pointer$
 .option pop
 
-	/* Get the physical address kernel loaded to */ 
+	/* Get the physical address kernel loaded to */
 	lla	t0, virt_map	//virt_map is a phy addr where its own va is stored.
 	ld	t1, 0(t0)
 	sub	t1, t1, t0	//t1 = t1 - t0 = va - pa, va<-->pa offset
@@ -62,7 +62,7 @@ _start_kern_bootstrap:
 	sub	s9, t2, t1	//s9 = physmem base of kernel
 
 	//registers passed by bbl.
-	/* 
+	/*
 	 * a0 = hart id
 	 * a1 = dtbp
 	 */
@@ -79,11 +79,11 @@ _start_kern_bootstrap:
 	/* Pick a hart to run the boot process. */
 	lla	t0, hart_lottery
 	li	t1, 1
-	//atomic memory operation, read-modify-write: 
-		//only the first hart can read 0 and modify it to 1, 
-		//all other harts will read 1.
+	//atomic memory operation, read-modify-write:
+	//only the first hart can read 0 and modify it to 1,
+	//all other harts will read 1.
 	amoadd.w t2, t1, (t0)
-	
+
 	/*
 	 * We must jump to mpentry in the non-BSP case because the offset is
 	 * too large to fit in a 12-bit branch immediate.
@@ -100,16 +100,16 @@ _start_kern_bootstrap:
 	/* Build PTE for 1 GiB identity-mapped gigapage */
 	lla	s1, pagetable_l1	//phy addr
 	mv	s2, s9			//phy addr
-	li      t0, 0xffffffffc0000000
-	and     s2, s2, t0
+	li	t0, 0xffffffffc0000000
+	and	s2, s2, t0
 	srli	s2, s2, PAGE_SHIFT	//12, 4K page
-	slli	t5, s2, PTE_PPN0_S	//10bit Phys Mem Attribute 
+	slli	t5, s2, PTE_PPN0_S	//10bit Phys Mem Attribute
 	li	t4, (PTE_KERN | PTE_X)	//flag bit
 	or	t6, t4, t5		//t6 now is PTE for a 1 GiB gigapage
 
 	/* Calculate VPN[2] for 1 GiB identity-mapped gigapage */
 	mv	a5, s9			//va -- identity mapped
-	srli	a5, a5, L1_SHIFT	//30,  remaining va[63:30]
+	srli	a5, a5, L1_SHIFT	//30, remaining va[63:30]
 	andi	a5, a5, 0x1ff		//only use va[38:30] as VPN[2], =0x002
 
 	/* Store L1 PTE entry */
@@ -118,14 +118,14 @@ _start_kern_bootstrap:
 	add	t0, s1, a5
 	mv	s8, t0		// Store address in L1 Page Table to unmap later
 	sd	t6, (t0)
-	
+
 	/* step1) Add L1 entry for kernel */
-	
+
 	//calc PTE based on pa
 	lla	s1, pagetable_l1	//phy addr
-	lla	s2, pagetable_l2	
+	lla	s2, pagetable_l2
 	srli	s2, s2, PAGE_SHIFT	//12, 4K page
-	slli	t5, s2, PTE_PPN0_S	//10bit Phys Mem Attribute 
+	slli	t5, s2, PTE_PPN0_S	//10bit Phys Mem Attribute
 	li	t4, PTE_V		//PTE valid
 	or	t6, t4, t5		//t6 now is the PTE for a level 2 page table
 
@@ -134,14 +134,14 @@ _start_kern_bootstrap:
 	srli	a5, a5, L1_SHIFT	//30
 	andi	a5, a5, 0x1ff		//va[38:30] as VPN[2],==0x100
 
-	/* Store L1 PTE entry */ 
+	/* Store L1 PTE entry */
 	li	a6, PTE_SIZE		//8 Bytes
 	mulw	a5, a5, a6		//distance in unit of bytes
 	add	t0, s1, a5		//s1 is L1 table base pa
-	sd	t6, (t0)		//PTE of a l2 page table is populated to l1 page table 
+	sd	t6, (t0)		//PTE of a l2 page table is populated to l1 page table
 
 
-	/* step2)  Level 2 superpages (512 x 2MiB) */ 	//mega pages: two-level page table
+	/* step2) Level 2 superpages (512 x 2MiB) */ //mega pages: two-level page table
 	lla	s1, pagetable_l2
 	//calc PTE
 	srli	t4, s9, L2_SHIFT	/* Div physmem base by 2 MiB */
@@ -153,28 +153,28 @@ _start_kern_bootstrap:
 	slli	t2, t4, PTE_PPN1_S	//19
 	or	t5, t0, t2		//PTE contructed
 	sd	t5, (s1)		/* Store PTE entry to position */
-	
+
 	//iterating
 	addi	s1, s1, PTE_SIZE
 	addi	t4, t4, 1
-	bltu	t4, t3, 2b		//512 entries 
+	bltu	t4, t3, 2b		//512 entries
 
 
-	/* step3)  Create an L1 entry for early devmap */
+	/* step3) Create an L1 entry for early devmap */
 	lla	s1, pagetable_l1	//pa
-	
+
 	//calculate PTE based on pa: (PPN) + privilege/permission + ...
 	lla	s2, pagetable_l2_devmap	/* Link to next level PN */ //pa
 	srli	s2, s2, PAGE_SHIFT	//12, --> PPN
 	slli	t5, s2, PTE_PPN0_S	//10, PMA
 	li	t4, PTE_V
 	or	t6, t4, t5		//PTE contructed
-	
+
 	//calculate VPN[2] index based on va
 	li	a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE)//devmap is at kernel mem top, va
 	srli	a5, a5, L1_SHIFT	//30
 	andi	a5, a5, 0x1ff		//index using va[38:30]
-	
+
 	/* Store single level1 PTE entry to position */
 	li	a6, PTE_SIZE
 	mulw	a5, a5, a6		//offset in Bytes
@@ -184,19 +184,19 @@ _start_kern_bootstrap:
 
 	/* step4) Create ONE L2 superpage 2MB for DTB */
 	lla	s1, pagetable_l2_devmap
-	
+
 	//calc PTE based on pa
 	mv	s2, a1			//passed by bbl
-	li      t0, 0xffffffffffe00000
-	and     s2, s2, t0
+	li	t0, 0xffffffffffe00000
+	and	s2, s2, t0
 	srli	s2, s2, PAGE_SHIFT	//12
 	slli	t2, s2, PTE_PPN0_S	//10
 	li	t0, (PTE_KERN)
 	or	t0, t0, t2		//PTE contructed
 
 	/* Store PTE entry to position */
-	li	a6, PTE_SIZE	
-	li	a5, 510			
+	li	a6, PTE_SIZE
+	li	a5, 510
 	mulw	a5, a5, a6
 	add	t1, s1, a5
 	sd	t0, (t1)
@@ -212,8 +212,8 @@ _start_kern_bootstrap:
 
 	/* Set page tables base register */
 	lla	s2, pagetable_l1	//pa
-	srli	s2, s2, PAGE_SHIFT	//12, --> PPN 
-	li	t0, SATP_MODE_SV39	//satp[63:60] = 1000b, enable paging! 
+	srli	s2, s2, PAGE_SHIFT	//12, --> PPN
+	li	t0, SATP_MODE_SV39	//satp[63:60] = 1000b, enable paging!
 	or	s2, s2, t0
 	sfence.vma			//Supervisor Fence for Virtual Memory, to flush TLB
 	csrw	satp, s2
@@ -243,7 +243,7 @@ va:
 	/* Initialize stack pointer */
 	la	s3, initstack_end
 	mv	sp, s3
-	
+
 	/* Allocate space for thread0 PCB and riscv_bootparams */
 	addi	sp, sp, -(PCB_SIZEOF + RISCV_BOOTPARAMS_SIZEOF) & ~STACKALIGNBYTES
 
@@ -273,9 +273,9 @@ va:
 	sd	t0, KERN_STACK(sp)
 
 	li	t0, (VM_MAX_KERNEL_ADDRESS - 2 * L2_SIZE) // XXX Why 2?
-	li      t1, 0x1fffff
-	and     t1, a1, t1
-	add     t0, t0, t1
+	li	t1, 0x1fffff
+	and	t1, a1, t1
+	add	t0, t0, t1
 	sd	t0, DTBP_VIRT(sp)
 	sd	a1, DTBP_PHYS(sp)
 
@@ -284,9 +284,9 @@ va:
 	call	_C_LABEL(main)		//defined in openbsd/kern/init_main.c
 
 	.data
-	.align  4
+	.align	4
 initstack:
-	.space  (PAGE_SIZE * KSTACK_PAGES)
+	.space	(PAGE_SIZE * KSTACK_PAGES)
 initstack_end:
 
 	.globl	sigfill
@@ -300,18 +300,18 @@ sigfillsiz:
 
 	.text
 ENTRY(sigcode)
-	mv      a0, sp
-	addi    a0, a0, SF_SC //actual saved context
-	li      t0, SYS_sigreturn
-	ecall                //make a syscall from lower privilege to higher
+	mv	a0, sp
+	addi	a0, a0, SF_SC //actual saved context
+	li	t0, SYS_sigreturn
+	ecall
 	.globl _C_LABEL(sigcoderet)
 _C_LABEL(sigcoderet):
 	/* sigreturn failed, exit */
-	li      t0, SYS_exit
+	li	t0, SYS_exit
 	ecall
 END(sigcode)
 	/* This may be copied to the stack, keep it 16-byte aligned */
-	.align  3
+	.align	3
 	.globl _C_LABEL(esigcode)
 _C_LABEL(esigcode):
 
@@ -332,7 +332,7 @@ pagetable_l2_devmap:
 
 	.align 3
 virt_map:
-	.quad   virt_map	
+	.quad	virt_map
 hart_lottery:
 	.space	4
 
@@ -370,12 +370,12 @@ ENTRY(mpentry)
 	beqz	t1, 1b			//see __riscv_boot_ap
 
 	/* Setup stack pointer */	//now kernel is ready
-	lla	t0, secondary_stacks  //pa, size: #core x #pages/kernel x pg_size
+	lla	t0, secondary_stacks	//pa, size: #core x #pages/kernel x pg_size
 	li	t1, (PAGE_SIZE * KSTACK_PAGES)	// size of kernel stack for one core
 	mulw	t2, t1, a0			//offset for this hart
 	add	t0, t0, t2			//end of stack for this hart
 	add	t0, t0, t1			//start of stack for this hart
-	sub	t0, t0, s9			//s9 is phymem base, t0 is now relative addr 
+	sub	t0, t0, s9			//s9 is phymem base, t0 is now relative addr
 	li	t1, KERNBASE			//t1 is virtual addr
 	add	sp, t0, t1			//now sp is set to the right virtual address.
 
diff --git a/sys/arch/riscv64/riscv64/machdep.c b/sys/arch/riscv64/riscv64/machdep.c
index 8a971c32451..c7ed96f98ef 100644
--- a/sys/arch/riscv64/riscv64/machdep.c
+++ b/sys/arch/riscv64/riscv64/machdep.c
@@ -89,7 +89,7 @@ struct uvm_constraint_range *uvm_md_constraints[] = {
 };
 
 /* the following is used externally (sysctl_hw) */
-char    machine[] = MACHINE;            /* from <machine/param.h> */
+char    machine[] = MACHINE;		/* from <machine/param.h> */
 
 int safepri = 0;
 
@@ -260,7 +260,7 @@ cpu_startup(void)
 	 * Allocate a submap for physio
 	 */
 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
-				   VM_PHYS_SIZE, 0, FALSE, NULL);
+	    VM_PHYS_SIZE, 0, FALSE, NULL);
 
 	/*
 	 * Set up buffers, so they can be used to read disk labels.
@@ -303,7 +303,7 @@ cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
 		node = OF_finddevice("/");
 		len = OF_getproplen(node, "compatible");
 		if (len <= 0)
-			return (EOPNOTSUPP); 
+			return (EOPNOTSUPP);
 		compatible = malloc(len, M_TEMP, M_WAITOK | M_ZERO);
 		OF_getprop(node, "compatible", compatible, len);
 		compatible[len - 1] = 0;
@@ -418,7 +418,7 @@ need_resched(struct cpu_info *ci)
  * Size of memory segments, before any memory is stolen.
  */
 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
-int     mem_cluster_cnt;
+int	mem_cluster_cnt;
 
 /*
  * cpu_dumpsize: calculate size of machine-dependent kernel core dump headers.
@@ -460,8 +460,8 @@ cpu_dump_mempagecnt(void)
  * These variables are needed by /sbin/savecore
  */
 u_long	dumpmag = 0x8fca0101;	/* magic number */
-int 	dumpsize = 0;		/* pages */
-long	dumplo = 0; 		/* blocks */
+int	dumpsize = 0;		/* pages */
+long	dumplo = 0;		/* blocks */
 
 /*
  * This is called by main to set dumplo and dumpsize.
@@ -794,7 +794,7 @@ initriscv(struct riscv_bootparams *rbp)
 	node = fdt_find_node("/reserved-memory");
 	if (node) {
 		for (node = fdt_child_node(node); node;
-		     node = fdt_next_node(node)) {
+		    node = fdt_next_node(node)) {
 			if (fdt_get_reg(node, 0, &reg))
 				continue;
 			if (reg.size == 0)
diff --git a/sys/arch/riscv64/riscv64/mem.c b/sys/arch/riscv64/riscv64/mem.c
index 3ec59a16018..56c0addc2dd 100644
--- a/sys/arch/riscv64/riscv64/mem.c
+++ b/sys/arch/riscv64/riscv64/mem.c
@@ -244,12 +244,12 @@ mmmmap(dev_t dev, off_t off, int prot)
 int
 mmioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct proc *p)
 {
-        switch (cmd) {
-        case FIONBIO:
-        case FIOASYNC:
-                /* handled by fd layer */
-                return 0;
-        }
+	switch (cmd) {
+	case FIONBIO:
+	case FIOASYNC:
+		/* handled by fd layer */
+		return 0;
+	}
 
 	return (EOPNOTSUPP);
 }
diff --git a/sys/arch/riscv64/riscv64/pmap.c b/sys/arch/riscv64/riscv64/pmap.c
index 2d462025f78..e86bba0daa7 100644
--- a/sys/arch/riscv64/riscv64/pmap.c
+++ b/sys/arch/riscv64/riscv64/pmap.c
@@ -1029,7 +1029,7 @@ pmap_kpted_alloc(void)
 			if (pted == NULL)
 				return NULL;
 		}
-				
+
 		npted = PAGE_SIZE / sizeof(struct pte_desc);
 	}
 
@@ -1108,7 +1108,7 @@ pmap_growkernel(vaddr_t maxkvaddr)
 
 fail:
 	splx(s);
-	
+
 	return pmap_maxkvaddr;
 }
 
diff --git a/sys/arch/riscv64/riscv64/process_machdep.c b/sys/arch/riscv64/riscv64/process_machdep.c
index 6578cef76f8..4a442ea2f26 100644
--- a/sys/arch/riscv64/riscv64/process_machdep.c
+++ b/sys/arch/riscv64/riscv64/process_machdep.c
@@ -59,9 +59,9 @@ process_read_regs(struct proc *p, struct reg *regs)
 	regs->r_ra = tf->tf_ra;
 	regs->r_sp = tf->tf_sp;
 	regs->r_gp = tf->tf_gp;
-	regs->r_tp = tf->tf_tp;//following Freebsd 
+	regs->r_tp = tf->tf_tp;//following Freebsd
 	//regs->r_tp = (uint64_t)p->p_addr->u_pcb.pcb_tcb;//XXX why?
-	//XXX freebsd adds the following two fields so we just follow. 
+	//XXX freebsd adds the following two fields so we just follow.
 	regs->r_sepc = tf->tf_sepc;
 	regs->r_sstatus = tf->tf_sstatus;
 
@@ -93,7 +93,7 @@ process_write_regs(struct proc *p, struct reg *regs)
 	tf->tf_ra = regs->r_ra;
 	tf->tf_sp = regs->r_sp;
 	tf->tf_gp = regs->r_gp;
-	tf->tf_tp = regs->r_tp; //XXX 
+	tf->tf_tp = regs->r_tp; //XXX
 	tf->tf_sepc = regs->r_sepc;
 	//p->p_addr->u_pcb.pcb_tcb = (void *)regs->r_tp;//XXX why? freebsd just copied r_tp to tf_tp
 	//XXX should we add r_sepc and sstatus also?
diff --git a/sys/arch/riscv64/riscv64/sig_machdep.c b/sys/arch/riscv64/riscv64/sig_machdep.c
index 8c2399ffba0..49a0be2fbd5 100644
--- a/sys/arch/riscv64/riscv64/sig_machdep.c
+++ b/sys/arch/riscv64/riscv64/sig_machdep.c
@@ -88,17 +88,17 @@ void dumpframe (char *msg, struct trapframe *tf, void *p)
 	int i;
 	printf("%s\n",msg);
 	printf("pc %lx ra %lx sp %lx tp %lx\n", tf->tf_sepc, tf->tf_ra, tf->tf_sp, tf->tf_tp);
-	for(i = 0; i < 7; i++) 
+	for(i = 0; i < 7; i++)
 		printf("%st%d %lx", (i==0)?"":", ", i, tf->tf_t[i]);
 	printf("\n");
-	for(i = 0; i < 12; i++) 
+	for(i = 0; i < 12; i++)
 		printf("%ss%d %lx", (i==0)?"":", ", i, tf->tf_s[i]);
 	printf("\n");
-	for(i = 0; i < 8; i++) 
+	for(i = 0; i < 8; i++)
 		printf("%sa%d %lx", (i==0)?"":", ", i, tf->tf_a[i]);
 	printf("\n");
 	if (p != NULL)
-	   printf("fp %p\n", p);
+		printf("fp %p\n", p);
 }
 
 /*
diff --git a/sys/arch/riscv64/riscv64/syscall.c b/sys/arch/riscv64/riscv64/syscall.c
index a37d46cd332..23783c75779 100644
--- a/sys/arch/riscv64/riscv64/syscall.c
+++ b/sys/arch/riscv64/riscv64/syscall.c
@@ -60,12 +60,12 @@ svc_handler(trapframe_t *frame)
 	code = frame->tf_t[0]; // Syscall code
 	callp = p->p_p->ps_emul->e_sysent;
 
-	switch (code) {	
+	switch (code) {
 	case SYS_syscall:
 		code = *ap++;
 		nap--;
 		break;
-        case SYS___syscall:
+	case SYS___syscall:
 		code = *ap++;
 		nap--;
 		break;
diff --git a/sys/arch/riscv64/riscv64/trap.c b/sys/arch/riscv64/riscv64/trap.c
index 66177ed85e8..6a9c41028e3 100644
--- a/sys/arch/riscv64/riscv64/trap.c
+++ b/sys/arch/riscv64/riscv64/trap.c
@@ -88,7 +88,7 @@ do_trap_supervisor(struct trapframe *frame)
 	case EXCP_BREAKPOINT:
 #ifdef DDB
 		// kdb_trap(exception, 0, frame);
-                db_trapper(frame->tf_sepc,0/*XXX*/, frame, exception);         
+		db_trapper(frame->tf_sepc,0/*XXX*/, frame, exception);
 #else
 		dump_regs(frame);
 		panic("No debugger in kernel.\n");
@@ -109,13 +109,13 @@ void
 do_trap_user(struct trapframe *frame)
 {
 	uint64_t exception;
-	union sigval sv; 
+	union sigval sv;
 	struct proc *p;
 	struct pcb *pcb;
 
 	p = curcpu()->ci_curproc;
 	p->p_addr->u_pcb.pcb_tf = frame;
-	pcb = curcpu()->ci_curpcb; 
+	pcb = curcpu()->ci_curpcb;
 
 	/* Ensure we came from usermode, interrupts disabled */
 	KASSERTMSG((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == 0,