From: kettenis <kettenis@openbsd.org>
Date: Fri, 26 Jan 2024 17:50:00 +0000 (+0000)
Subject: Initial clock support for Allwinner D1.
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=4e48f70da133cd6e0c19862a84d9916e4dca35a6;p=openbsd

Initial clock support for Allwinner D1.

ok dlg@, mlarkin@
---

diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c
index d4c2e767d6b..0707009b648 100644
--- a/sys/dev/fdt/sxiccmu.c
+++ b/sys/dev/fdt/sxiccmu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiccmu.c,v 1.32 2023/08/15 08:27:30 miod Exp $	*/
+/*	$OpenBSD: sxiccmu.c,v 1.33 2024/01/26 17:50:00 kettenis Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -98,6 +98,8 @@ uint32_t sxiccmu_a64_get_frequency(struct sxiccmu_softc *, uint32_t);
 int	sxiccmu_a64_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 uint32_t sxiccmu_a80_get_frequency(struct sxiccmu_softc *, uint32_t);
 int	sxiccmu_a80_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_d1_get_frequency(struct sxiccmu_softc *, uint32_t);
+int	sxiccmu_d1_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 uint32_t sxiccmu_h3_get_frequency(struct sxiccmu_softc *, uint32_t);
 int	sxiccmu_h3_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
@@ -145,6 +147,7 @@ sxiccmu_match(struct device *parent, void *match, void *aux)
 	    OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
 	    OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
+	    OF_is_compatible(node, "allwinner,sun20i-d1-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-a64-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
@@ -252,6 +255,14 @@ sxiccmu_attach(struct device *parent, struct device *self, void *aux)
 		sc->sc_nresets = nitems(sun9i_a80_mmc_resets);
 		sc->sc_get_frequency = sxiccmu_nop_get_frequency;
 		sc->sc_set_frequency = sxiccmu_nop_set_frequency;
+	} else if (OF_is_compatible(node, "allwinner,sun20i-d1-ccu")) {
+		KASSERT(faa->fa_nreg > 0);
+		sc->sc_gates = sun20i_d1_gates;
+		sc->sc_ngates = nitems(sun20i_d1_gates);
+		sc->sc_resets = sun20i_d1_resets;
+		sc->sc_nresets = nitems(sun20i_d1_resets);
+		sc->sc_get_frequency = sxiccmu_d1_get_frequency;
+		sc->sc_set_frequency = sxiccmu_d1_set_frequency;
 	} else if (OF_is_compatible(node, "allwinner,sun50i-a64-ccu")) {
 		KASSERT(faa->fa_nreg > 0);
 		sc->sc_gates = sun50i_a64_gates;
@@ -1156,6 +1167,21 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
 	return 0;
 }
 
+/* Allwinner D1 */
+
+uint32_t
+sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+	switch (idx) {
+	case D1_CLK_APB1:
+		/* XXX Controlled by a MUX. */
+		return 24000000;
+	}
+
+	printf("%s: 0x%08x\n", __func__, idx);
+	return 0;
+}
+
 /* Allwinner H3/H5 */
 #define H3_PLL_CPUX_CTRL_REG		0x0000
 #define H3_PLL_CPUX_ENABLE		(1U << 31)
@@ -1645,6 +1671,13 @@ sxiccmu_a80_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
 	return -1;
 }
 
+int
+sxiccmu_d1_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
+{
+	printf("%s: 0x%08x\n", __func__, idx);
+	return -1;
+}
+
 int
 sxiccmu_h3_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
 {
diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h
index 041162d0ee4..7dc5a90f1d4 100644
--- a/sys/dev/fdt/sxiccmu_clocks.h
+++ b/sys/dev/fdt/sxiccmu_clocks.h
@@ -302,6 +302,37 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
 	{ 0x000c, 16 },
 };
 
+/* D1 */
+
+#define D1_CLK_APB1		25
+#define D1_CLK_BUS_UART0	62
+#define D1_CLK_BUS_UART1	63
+#define D1_CLK_BUS_UART2	64
+#define D1_CLK_BUS_UART3	65
+#define D1_CLK_BUS_UART4	66
+#define D1_CLK_BUS_UART5	67
+#define D1_CLK_USB_OHCI0	97
+#define D1_CLK_USB_OHCI1	98
+#define D1_CLK_BUS_OHCI0	99
+#define D1_CLK_BUS_OHCI1	100
+#define D1_CLK_BUS_EHCI0	101
+#define D1_CLK_BUS_EHCI1	102
+
+const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
+	[D1_CLK_BUS_UART0] = { 0x090c, 0, D1_CLK_APB1 },
+	[D1_CLK_BUS_UART1] = { 0x090c, 1, D1_CLK_APB1 },
+	[D1_CLK_BUS_UART2] = { 0x090c, 2, D1_CLK_APB1 },
+	[D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
+	[D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
+	[D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
+	[D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
+	[D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
+	[D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
+	[D1_CLK_BUS_OHCI1] = { 0x0a8c, 1 },
+	[D1_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
+	[D1_CLK_BUS_EHCI1] = { 0x0a8c, 5 },
+};
+
 /* H3/H5 */
 
 #define H3_CLK_PLL_CPUX		0
@@ -768,6 +799,36 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
 	{ 0x000c, 18 },
 };
 
+/* D1 */
+
+#define D1_RST_BUS_UART0	18
+#define D1_RST_BUS_UART1	19
+#define D1_RST_BUS_UART2	20
+#define D1_RST_BUS_UART3	21
+#define D1_RST_BUS_UART4	22
+#define D1_RST_BUS_UART5	23
+#define D1_RST_USB_PHY0		40
+#define D1_RST_USB_PHY1		41
+#define D1_RST_BUS_OHCI0	42
+#define D1_RST_BUS_OHCI1	43
+#define D1_RST_BUS_EHCI0	44
+#define D1_RST_BUS_EHCI1	45
+
+const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
+	[D1_RST_BUS_UART0] = { 0x090c, 16 },
+	[D1_RST_BUS_UART1] = { 0x090c, 17 },
+	[D1_RST_BUS_UART2] = { 0x090c, 18 },
+	[D1_RST_BUS_UART3] = { 0x090c, 19 },
+	[D1_RST_BUS_UART4] = { 0x090c, 20 },
+	[D1_RST_BUS_UART5] = { 0x090c, 21 },
+	[D1_RST_USB_PHY0] =  { 0x0a70, 30 },
+	[D1_RST_USB_PHY1] =  { 0x0a74, 30 },
+	[D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },
+	[D1_RST_BUS_OHCI1] = { 0x0a8c, 17 },
+	[D1_RST_BUS_EHCI0] = { 0x0a8c, 20 },
+	[D1_RST_BUS_EHCI1] = { 0x0a8c, 21 },
+};
+
 /* H3/H5 */
 
 #define H3_RST_USB_PHY0		0