From: kettenis <kettenis@openbsd.org>
Date: Thu, 10 Jul 2008 09:29:33 +0000 (+0000)
Subject: Add support for Fujitsu SPARC64-VI CPUs.
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=48e59a2bb097dad9a9bdd17aadbfbe54354ce9c7;p=openbsd

Add support for Fujitsu SPARC64-VI CPUs.

UltraSPARC I/II has a 41-bit physical address space, UltraSPARC III/IV has a
43-bit physical address space.  The Fujitsu SPARC64-VI extends this to 46 bits.
Adjust the TTE masks to take this into account and adjust some locore code
that truncated physical addresses to 41 bits (fixing a potential bug for
UltraSPARC III/IV too).

While there, fix the locore code for UltraSPARC Architecture 2007 CPUs, which
may support up to 56 bits of physical address space.
---

diff --git a/sys/arch/sparc64/include/pte.h b/sys/arch/sparc64/include/pte.h
index 9d453fafd54..bcc04d693ef 100644
--- a/sys/arch/sparc64/include/pte.h
+++ b/sys/arch/sparc64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.11 2008/04/20 09:18:52 kettenis Exp $	*/
+/*	$OpenBSD: pte.h,v 1.12 2008/07/10 09:29:33 kettenis Exp $	*/
 /*	$NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */
 
 /*
@@ -168,7 +168,7 @@ void smp_tlb_flush_ctx(int);
 #define SUN4U_TLB_IE		0x0800000000000000LL
 #define SUN4U_TLB_SOFT2_MASK	0x07fc000000000000LL
 #define SUN4U_TLB_RESERVED_MASK	0x0003f80000000000LL
-#define SUN4U_TLB_PA_MASK	0x000007ffffffe000LL
+#define SUN4U_TLB_PA_MASK	0x00007fffffffe000LL
 #define SUN4U_TLB_SOFT_MASK	0x0000000000001f80LL
 /* S/W bits */
 #define SUN4U_TLB_ACCESS	0x0000000000000200LL
diff --git a/sys/arch/sparc64/sparc64/locore.s b/sys/arch/sparc64/sparc64/locore.s
index 670c4e77acd..ae03b3b3a7d 100644
--- a/sys/arch/sparc64/sparc64/locore.s
+++ b/sys/arch/sparc64/sparc64/locore.s
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.s,v 1.144 2008/07/05 20:53:33 kettenis Exp $	*/
+/*	$OpenBSD: locore.s,v 1.145 2008/07/10 09:29:33 kettenis Exp $	*/
 /*	$NetBSD: locore.s,v 1.137 2001/08/13 06:10:10 jdolecek Exp $	*/
 
 /*
@@ -2086,9 +2086,9 @@ winfixspill:
 	brgez	%g7, 0f
 	 srlx	%g7, PGSHIFT, %g7			! Isolate PA part
 	sll	%g6, 32-PGSHIFT, %g6			! And offset
-	sllx	%g7, PGSHIFT+23, %g7			! There are 23 bits to the left of the PA in the TTE
+	sllx	%g7, PGSHIFT+17, %g7			! There are 17 bits to the left of the PA in the TTE
 	srl	%g6, 32-PGSHIFT, %g6
-	srax	%g7, 23, %g7
+	srax	%g7, 17, %g7
 	or	%g7, %g6, %g6				! Then combine them to form PA
 
 	wr	%g0, ASI_PHYS_CACHED, %asi		! Use ASI_PHYS_CACHED to prevent possible page faults
@@ -3287,9 +3287,9 @@ pcbspill:
 	brgez	%g7, pcbspill_fail
 	 srlx	%g7, PGSHIFT, %g7			! Isolate PA part
 	sll	%g6, 32-PGSHIFT, %g6			! And offset
-	sllx	%g7, PGSHIFT+23, %g7			! There are 23 bits to the left of the PA in the TTE
+	sllx	%g7, PGSHIFT+8, %g7			! There are 8 bits to the left of the PA in the TTE
 	srl	%g6, 32-PGSHIFT, %g6
-	srax	%g7, 23, %g7
+	srax	%g7, 8, %g7
 	or	%g7, %g6, %g6				! Then combine them to form PA
 
 !	wr	%g0, ASI_PHYS_CACHED, %asi		! Use ASI_PHYS_CACHED to prevent possible page faults