From: kettenis <kettenis@openbsd.org>
Date: Sat, 10 Feb 2018 22:31:34 +0000 (+0000)
Subject: More Allwinner A64 clocks.
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=45fbe8fb75f72154e29698e7c23e8cd978a216e3;p=openbsd

More Allwinner A64 clocks.
---

diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c
index 560adf6884c..5465f09b689 100644
--- a/sys/dev/fdt/sxiccmu.c
+++ b/sys/dev/fdt/sxiccmu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiccmu.c,v 1.17 2017/12/31 10:54:39 kettenis Exp $	*/
+/*	$OpenBSD: sxiccmu.c,v 1.18 2018/02/10 22:31:34 kettenis Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -135,6 +135,7 @@ sxiccmu_match(struct device *parent, void *match, void *aux)
 	    OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
 	    OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
 	    OF_is_compatible(node, "allwinner,sun50i-a64-ccu") ||
+	    OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-h5-ccu"));
 }
 
@@ -180,7 +181,8 @@ sxiccmu_attach(struct device *parent, struct device *self, void *aux)
 		sc->sc_nresets = nitems(sun8i_h3_resets);
 		sc->sc_get_frequency = sxiccmu_h3_get_frequency;
 		sc->sc_set_frequency = sxiccmu_h3_set_frequency;
-	} else if (OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu")) {
+	} else if (OF_is_compatible(node, "allwinner,sun8i-h3-r-ccu") ||	
+	    OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu")) {
 		KASSERT(faa->fa_nreg > 0);
 		sc->sc_gates = sun8i_h3_r_gates;
 		sc->sc_ngates = nitems(sun8i_h3_r_gates);
diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h
index 78c380a2317..41f269839a6 100644
--- a/sys/dev/fdt/sxiccmu_clocks.h
+++ b/sys/dev/fdt/sxiccmu_clocks.h
@@ -170,6 +170,7 @@ struct sxiccmu_ccu_bit sun8i_a23_gates[] = {
 #define A64_CLK_HOSC		253
 
 struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
+	[A64_CLK_PLL_PERIPH0] = { 0x0028, 31 },
 	[A64_CLK_BUS_MMC0] =  { 0x0060, 8 },
 	[A64_CLK_BUS_MMC1] =  { 0x0060, 9 },
 	[A64_CLK_BUS_MMC2] =  { 0x0060, 10 },
@@ -352,10 +353,12 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
 #define H3_R_CLK_APB0		2
 
 #define H3_R_CLK_APB0_PIO	3
+#define H3_R_CLK_APB0_RSB	6
 #define H3_R_CLK_APB0_I2C	9
 
 struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
 	[H3_R_CLK_APB0_PIO] = { 0x0028, 0 },
+	[H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 },
 	[H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 },
 };
 
@@ -624,9 +627,11 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
 	[H3_RST_BUS_I2C2]  = { 0x02d8, 2 },
 };
 
+#define H3_R_RST_APB0_RSB	2
 #define H3_R_RST_APB0_I2C	5
 
 struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
+	[H3_R_RST_APB0_RSB] = { 0x00b0, 3 },
 	[H3_R_RST_APB0_I2C] = { 0x00b0, 6 },
 };