From: jsg <jsg@openbsd.org>
Date: Fri, 20 Oct 2023 03:41:56 +0000 (+0000)
Subject: drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=42b1e46fc5f379aabe82a78e6e4decc82a88f034;p=openbsd

drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval

From Nirmoy Das
f175665385fe9fdd996080806aa67e666475d3d8 in linux-6.1.y/6.1.59
128c20eda73bd3e78505c574fb17adb46195c98b in mainline linux
---

diff --git a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
index cc846853687..efc22f9b17f 100644
--- a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
+++ b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
@@ -235,8 +235,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		u32 flags = 0;
 		u32 *cs;
 
+		/*
+		 * L3 fabric flush is needed for AUX CCS invalidation
+		 * which happens as part of pipe-control so we can
+		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
+		 * deals with Protected Memory which is not needed for
+		 * AUX CCS invalidation and lead to unwanted side effects.
+		 */
+		if (mode & EMIT_FLUSH)
+			flags |= PIPE_CONTROL_FLUSH_L3;
+
 		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
-		flags |= PIPE_CONTROL_FLUSH_L3;
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		/* Wa_1409600907:tgl,adl-p */