From: jsg <jsg@openbsd.org>
Date: Mon, 11 Apr 2022 04:08:37 +0000 (+0000)
Subject: drm/i915: Reject unsupported TMDS rates on ICL+
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=3d239ffef3e42966832515384d28d158c38729b7;p=openbsd

drm/i915: Reject unsupported TMDS rates on ICL+

From Ville Syrjala
f5a0cf225f8d3cf06aff181b291a0ff32f4ad2c8 in linux 5.15.y/5.15.33
9cddf03b2af07443bebdc73cba21acb360c079e8 in mainline linux
---

diff --git a/sys/dev/pci/drm/i915/display/intel_hdmi.c b/sys/dev/pci/drm/i915/display/intel_hdmi.c
index 1754a788e0c..2a70c515976 100644
--- a/sys/dev/pci/drm/i915/display/intel_hdmi.c
+++ b/sys/dev/pci/drm/i915/display/intel_hdmi.c
@@ -1831,6 +1831,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 		      bool has_hdmi_sink)
 {
 	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
+	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
 
 	if (clock < 25000)
 		return MODE_CLOCK_LOW;
@@ -1851,6 +1852,14 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
 		return MODE_CLOCK_RANGE;
 
+	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
+	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
+		return MODE_CLOCK_RANGE;
+
+	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
+	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
+		return MODE_CLOCK_RANGE;
+
 	/*
 	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
 	 * set of link rates.