From: miod <miod@openbsd.org>
Date: Fri, 29 Mar 2024 21:07:11 +0000 (+0000)
Subject: De-register fpu completion code.
X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=2c7a42e9b41a8ae3324bc681b3f68bfd6fe8c29a;p=openbsd

De-register fpu completion code.

There are pending changes to some of these files, and this would get in the
way.

ok claudio@ kettenis@
---

diff --git a/sys/arch/sparc64/fpu/fpu.c b/sys/arch/sparc64/fpu/fpu.c
index 27480142747..a928e1ddbfa 100644
--- a/sys/arch/sparc64/fpu/fpu.c
+++ b/sys/arch/sparc64/fpu/fpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu.c,v 1.23 2022/10/21 18:55:42 miod Exp $	*/
+/*	$OpenBSD: fpu.c,v 1.24 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu.c,v 1.11 2000/12/06 01:47:50 mrg Exp $ */
 
 /*
@@ -185,9 +185,9 @@ fpu_fcopy(u_int *src, u_int *dst, int type)
  * unknown FPops do enter the queue, however.
  */
 void
-fpu_cleanup(register struct proc *p, register struct fpstate *fs)
+fpu_cleanup(struct proc *p, struct fpstate *fs)
 {
-	register int i, fsr = fs->fs_fsr, error;
+	int i, fsr = fs->fs_fsr, error;
 	union instr instr;
 	union sigval sv;
 	struct fpemu fe;
diff --git a/sys/arch/sparc64/fpu/fpu_add.c b/sys/arch/sparc64/fpu/fpu_add.c
index f53210a45bb..21dae5a3f93 100644
--- a/sys/arch/sparc64/fpu/fpu_add.c
+++ b/sys/arch/sparc64/fpu/fpu_add.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_add.c,v 1.3 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_add.c,v 1.4 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_add.c,v 1.3 1996/03/14 19:41:52 christos Exp $ */
 
 /*
@@ -60,11 +60,11 @@
 #include <sparc64/fpu/fpu_extern.h>
 
 struct fpn *
-fpu_add(register struct fpemu *fe)
+fpu_add(struct fpemu *fe)
 {
-	register struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2, *r;
-	register u_int r0, r1, r2, r3;
-	register int rd;
+	struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2, *r;
+	u_int r0, r1, r2, r3;
+	int rd;
 
 	/*
 	 * Put the `heavier' operand on the right (see fpu_emu.h).
diff --git a/sys/arch/sparc64/fpu/fpu_compare.c b/sys/arch/sparc64/fpu/fpu_compare.c
index 398d033ee3b..d3f47427a64 100644
--- a/sys/arch/sparc64/fpu/fpu_compare.c
+++ b/sys/arch/sparc64/fpu/fpu_compare.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_compare.c,v 1.3 2003/06/02 23:27:55 millert Exp $	*/
+/*	$OpenBSD: fpu_compare.c,v 1.4 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_compare.c,v 1.3 2001/08/26 05:46:31 eeh Exp $ */
 
 /*
@@ -73,8 +73,8 @@
 void
 fpu_compare(struct fpemu *fe, int cmpe)
 {
-	register struct fpn *a, *b;
-	register int cc;
+	struct fpn *a, *b;
+	int cc;
 	FPU_DECL_CARRY
 
 	a = &fe->fe_f1;
diff --git a/sys/arch/sparc64/fpu/fpu_div.c b/sys/arch/sparc64/fpu/fpu_div.c
index e23321ec267..e20b1dd4be7 100644
--- a/sys/arch/sparc64/fpu/fpu_div.c
+++ b/sys/arch/sparc64/fpu/fpu_div.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_div.c,v 1.4 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_div.c,v 1.5 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_div.c,v 1.2 1994/11/20 20:52:38 deraadt Exp $ */
 
 /*
@@ -148,11 +148,11 @@
  */
 
 struct fpn *
-fpu_div(register struct fpemu *fe)
+fpu_div(struct fpemu *fe)
 {
-	register struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
-	register u_int q, bit;
-	register u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
+	struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
+	u_int q, bit;
+	u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
 	FPU_DECL_CARRY
 
 	/*
diff --git a/sys/arch/sparc64/fpu/fpu_emu.h b/sys/arch/sparc64/fpu/fpu_emu.h
index 629a7d73fab..eb9ee7bdba9 100644
--- a/sys/arch/sparc64/fpu/fpu_emu.h
+++ b/sys/arch/sparc64/fpu/fpu_emu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_emu.h,v 1.6 2022/10/21 18:55:42 miod Exp $	*/
+/*	$OpenBSD: fpu_emu.h,v 1.7 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ */
 
 /*
@@ -128,7 +128,7 @@ struct fpn {
 		SWAP(x, y); \
 }
 #define	SWAP(x, y) { \
-	register struct fpn *swap; \
+	struct fpn *swap; \
 	swap = (x), (x) = (y), (y) = swap; \
 }
 
diff --git a/sys/arch/sparc64/fpu/fpu_explode.c b/sys/arch/sparc64/fpu/fpu_explode.c
index 8a843074ca6..4f61fad85ad 100644
--- a/sys/arch/sparc64/fpu/fpu_explode.c
+++ b/sys/arch/sparc64/fpu/fpu_explode.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_explode.c,v 1.6 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_explode.c,v 1.7 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ */
 
 /*
@@ -80,7 +80,7 @@
  * int -> fpn.
  */
 int
-fpu_itof(register struct fpn *fp, register u_int i)
+fpu_itof(struct fpn *fp, u_int i)
 {
 
 	if (i == 0)
@@ -104,7 +104,7 @@ fpu_itof(register struct fpn *fp, register u_int i)
  * 64-bit int -> fpn.
  */
 int
-fpu_xtof(register struct fpn *fp, register u_int64_t i)
+fpu_xtof(struct fpn *fp, u_int64_t i)
 {
 	if (i == 0)
 		return (FPC_ZERO);
@@ -165,10 +165,10 @@ fpu_xtof(register struct fpn *fp, register u_int64_t i)
  * format: i.e., needs at most fp_mant[0] and fp_mant[1].
  */
 int
-fpu_stof(register struct fpn *fp, register u_int i)
+fpu_stof(struct fpn *fp, u_int i)
 {
-	register int exp;
-	register u_int frac, f0, f1;
+	int exp;
+	u_int frac, f0, f1;
 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
 
 	exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
@@ -183,10 +183,10 @@ fpu_stof(register struct fpn *fp, register u_int i)
  * We assume this uses at most (96-FP_LG) bits.
  */
 int
-fpu_dtof(register struct fpn *fp, register u_int i, register u_int j)
+fpu_dtof(struct fpn *fp, u_int i, u_int j)
 {
-	register int exp;
-	register u_int frac, f0, f1, f2;
+	int exp;
+	u_int frac, f0, f1, f2;
 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
 
 	exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
@@ -202,11 +202,10 @@ fpu_dtof(register struct fpn *fp, register u_int i, register u_int j)
  * 128-bit extended -> fpn.
  */
 int
-fpu_qtof(register struct fpn *fp, register u_int i, register u_int j,
-    register u_int k, register u_int l)
+fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l)
 {
-	register int exp;
-	register u_int frac, f0, f1, f2, f3;
+	int exp;
+	u_int frac, f0, f1, f2, f3;
 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG))	/* left shift! */
 
 	/*
@@ -229,10 +228,9 @@ fpu_qtof(register struct fpn *fp, register u_int i, register u_int j,
  * operations are performed.)
  */
 void
-fpu_explode(register struct fpemu *fe, register struct fpn *fp, int type,
-    int reg)
+fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
 {
-	register u_int s, *space;
+	u_int s, *space;
 	u_int64_t l, *xspace;
 
 	xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];
diff --git a/sys/arch/sparc64/fpu/fpu_extern.h b/sys/arch/sparc64/fpu/fpu_extern.h
index cdf483e60bb..8f7c907fc0d 100644
--- a/sys/arch/sparc64/fpu/fpu_extern.h
+++ b/sys/arch/sparc64/fpu/fpu_extern.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_extern.h,v 1.7 2022/10/21 18:55:42 miod Exp $	*/
+/*	$OpenBSD: fpu_extern.h,v 1.8 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_extern.h,v 1.4 2000/08/03 18:32:08 eeh Exp $	*/
 
 /*-
@@ -73,6 +73,6 @@ struct fpn *fpu_mul(struct fpemu *);
 struct fpn *fpu_sqrt(struct fpemu *);
 
 /* fpu_subr.c */
-int fpu_shr(register struct fpn *, register int);
-void fpu_norm(register struct fpn *);
-struct fpn *fpu_newnan(register struct fpemu *);
+int fpu_shr(struct fpn *, int);
+void fpu_norm(struct fpn *);
+struct fpn *fpu_newnan(struct fpemu *);
diff --git a/sys/arch/sparc64/fpu/fpu_implode.c b/sys/arch/sparc64/fpu/fpu_implode.c
index 6492c6667e2..7ffa449bff8 100644
--- a/sys/arch/sparc64/fpu/fpu_implode.c
+++ b/sys/arch/sparc64/fpu/fpu_implode.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_implode.c,v 1.9 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_implode.c,v 1.10 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */
 
 /*
@@ -57,7 +57,7 @@
 #include <sparc64/fpu/fpu_emu.h>
 #include <sparc64/fpu/fpu_extern.h>
 
-static int fpu_round(register struct fpemu *, register struct fpn *);
+static int fpu_round(struct fpemu *, struct fpn *);
 static int toinf(struct fpemu *, int);
 
 /*
@@ -73,10 +73,10 @@ static int toinf(struct fpemu *, int);
  * responsibility to fix this if necessary.
  */
 static int
-fpu_round(register struct fpemu *fe, register struct fpn *fp)
+fpu_round(struct fpemu *fe, struct fpn *fp)
 {
-	register u_int m0, m1, m2, m3;
-	register int gr, s;
+	u_int m0, m1, m2, m3;
+	int gr, s;
 
 	m0 = fp->fp_mant[0];
 	m1 = fp->fp_mant[1];
@@ -188,10 +188,10 @@ toinf(struct fpemu *fe, int sign)
  * of the SPARC instruction set).
  */
 u_int
-fpu_ftoi(struct fpemu *fe, register struct fpn *fp)
+fpu_ftoi(struct fpemu *fe, struct fpn *fp)
 {
-	register u_int i;
-	register int sign, exp;
+	u_int i;
+	int sign, exp;
 
 	sign = fp->fp_sign;
 	switch (fp->fp_class) {
@@ -235,10 +235,10 @@ fpu_ftoi(struct fpemu *fe, register struct fpn *fp)
  * of the SPARC instruction set).
  */
 u_int
-fpu_ftox(struct fpemu *fe, register struct fpn *fp, u_int *res)
+fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
 {
-	register u_int64_t i;
-	register int sign, exp;
+	u_int64_t i;
+	int sign, exp;
 
 	sign = fp->fp_sign;
 	switch (fp->fp_class) {
@@ -286,10 +286,10 @@ out:
  * We assume <= 29 bits in a single-precision fraction (1.f part).
  */
 u_int
-fpu_ftos(struct fpemu *fe, register struct fpn *fp)
+fpu_ftos(struct fpemu *fe, struct fpn *fp)
 {
-	register u_int sign = fp->fp_sign << 31;
-	register int exp;
+	u_int sign = fp->fp_sign << 31;
+	int exp;
 
 #define	SNG_EXP(e)	((e) << SNG_FRACBITS)	/* makes e an exponent */
 #define	SNG_MASK	(SNG_EXP(1) - 1)	/* mask for fraction */
@@ -368,10 +368,10 @@ done:
  * This code mimics fpu_ftos; see it for comments.
  */
 u_int
-fpu_ftod(struct fpemu *fe, register struct fpn *fp, u_int *res)
+fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
 {
-	register u_int sign = fp->fp_sign << 31;
-	register int exp;
+	u_int sign = fp->fp_sign << 31;
+	int exp;
 
 #define	DBL_EXP(e)	((e) << (DBL_FRACBITS & 31))
 #define	DBL_MASK	(DBL_EXP(1) - 1)
@@ -426,10 +426,10 @@ done:
  * so we can avoid a small bit of work.
  */
 u_int
-fpu_ftoq(struct fpemu *fe, register struct fpn *fp, u_int *res)
+fpu_ftoq(struct fpemu *fe, struct fpn *fp, u_int *res)
 {
-	register u_int sign = fp->fp_sign << 31;
-	register int exp;
+	u_int sign = fp->fp_sign << 31;
+	int exp;
 
 #define	EXT_EXP(e)	((e) << (EXT_FRACBITS & 31))
 #define	EXT_MASK	(EXT_EXP(1) - 1)
@@ -483,8 +483,7 @@ done:
  * Implode an fpn, writing the result into the given space.
  */
 void
-fpu_implode(struct fpemu *fe, register struct fpn *fp, int type,
-    register u_int *space)
+fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
 {
 	DPRINTF(FPE_INSN, ("fpu_implode: "));
 	switch (type) {
diff --git a/sys/arch/sparc64/fpu/fpu_mul.c b/sys/arch/sparc64/fpu/fpu_mul.c
index 1ea859df52f..9813ac5afa0 100644
--- a/sys/arch/sparc64/fpu/fpu_mul.c
+++ b/sys/arch/sparc64/fpu/fpu_mul.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_mul.c,v 1.3 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_mul.c,v 1.4 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_mul.c,v 1.2 1994/11/20 20:52:44 deraadt Exp $ */
 
 /*
@@ -75,8 +75,6 @@
  *
  * Since we do not have efficient multiword arithmetic, we code the
  * accumulator as four separate words, just like any other mantissa.
- * We use local `register' variables in the hope that this is faster
- * than memory.  We keep x->fp_mant in locals for the same reason.
  *
  * In the algorithm above, the bits in y are inspected one at a time.
  * We will pick them up 32 at a time and then deal with those 32, one
@@ -97,11 +95,11 @@
  * until we reach a nonzero word.
  */
 struct fpn *
-fpu_mul(register struct fpemu *fe)
+fpu_mul(struct fpemu *fe)
 {
-	register struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
-	register u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m;
-	register int sticky;
+	struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
+	u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m;
+	int sticky;
 	FPU_DECL_CARRY
 
 	/*
diff --git a/sys/arch/sparc64/fpu/fpu_sqrt.c b/sys/arch/sparc64/fpu/fpu_sqrt.c
index 33df951b007..0b5ccfc0f6e 100644
--- a/sys/arch/sparc64/fpu/fpu_sqrt.c
+++ b/sys/arch/sparc64/fpu/fpu_sqrt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_sqrt.c,v 1.6 2022/10/16 01:22:39 jsg Exp $	*/
+/*	$OpenBSD: fpu_sqrt.c,v 1.7 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_sqrt.c,v 1.2 1994/11/20 20:52:46 deraadt Exp $ */
 
 /*
@@ -186,12 +186,12 @@
 struct fpn *
 fpu_sqrt(struct fpemu *fe)
 {
-	register struct fpn *x = &fe->fe_f1;
-	register u_int bit, q, tt;
-	register u_int x0, x1, x2, x3;
-	register u_int y0, y1, y2, y3;
-	register u_int d0, d1, d2, d3;
-	register int e;
+	struct fpn *x = &fe->fe_f1;
+	u_int bit, q, tt;
+	u_int x0, x1, x2, x3;
+	u_int y0, y1, y2, y3;
+	u_int d0, d1, d2, d3;
+	int e;
 
 	/*
 	 * Take care of special cases first.  In order:
diff --git a/sys/arch/sparc64/fpu/fpu_subr.c b/sys/arch/sparc64/fpu/fpu_subr.c
index efc44e6a8cf..2109b360047 100644
--- a/sys/arch/sparc64/fpu/fpu_subr.c
+++ b/sys/arch/sparc64/fpu/fpu_subr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_subr.c,v 1.2 2003/06/02 23:27:55 millert Exp $	*/
+/*	$OpenBSD: fpu_subr.c,v 1.3 2024/03/29 21:07:11 miod Exp $	*/
 /*	$NetBSD: fpu_subr.c,v 1.3 1996/03/14 19:42:01 christos Exp $ */
 
 /*
@@ -64,10 +64,10 @@
  * sticky field is ignored anyway.
  */
 int
-fpu_shr(register struct fpn *fp, register int rsh)
+fpu_shr(struct fpn *fp, int rsh)
 {
-	register u_int m0, m1, m2, m3, s;
-	register int lsh;
+	u_int m0, m1, m2, m3, s;
+	int lsh;
 
 #ifdef DIAGNOSTIC
 	if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp)))
@@ -138,10 +138,10 @@ fpu_shr(register struct fpn *fp, register int rsh)
  * a supernormal and it will fix it (provided fp->fp_mant[3] == 0).
  */
 void
-fpu_norm(register struct fpn *fp)
+fpu_norm(struct fpn *fp)
 {
-	register u_int m0, m1, m2, m3, top, sup, nrm;
-	register int lsh, rsh, exp;
+	u_int m0, m1, m2, m3, top, sup, nrm;
+	int lsh, rsh, exp;
 
 	exp = fp->fp_exp;
 	m0 = fp->fp_mant[0];
@@ -206,9 +206,9 @@ fpu_norm(register struct fpn *fp)
  * As a side effect, we set NV (invalid) for the current exceptions.
  */
 struct fpn *
-fpu_newnan(register struct fpemu *fe)
+fpu_newnan(struct fpemu *fe)
 {
-	register struct fpn *fp;
+	struct fpn *fp;
 
 	fe->fe_cx = FSR_NV;
 	fp = &fe->fe_f3;