From: kettenis Date: Sun, 26 Aug 2018 16:52:16 +0000 (+0000) Subject: Add plgpio(4), a driver for the ARM PrimeCell GPIO (PL061) peripheral. X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=290c6ee55f65bf44c94412ea5f060f786270ffed;p=openbsd Add plgpio(4), a driver for the ARM PrimeCell GPIO (PL061) peripheral. ok jsg@, patrick@ --- diff --git a/sys/arch/arm64/conf/GENERIC b/sys/arch/arm64/conf/GENERIC index 928c4c6ce3b..f16dda3c4a1 100644 --- a/sys/arch/arm64/conf/GENERIC +++ b/sys/arch/arm64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.83 2018/08/22 15:38:46 mpi Exp $ +# $OpenBSD: GENERIC,v 1.84 2018/08/26 16:52:16 kettenis Exp $ # # GENERIC machine description file # @@ -77,9 +77,10 @@ ccp* at fdt? # AMD Cryptographic Co-processor # NS16550 compatible serial ports com* at fdt? -# Virt on-chip devices -pluart* at fdt? # onboard uarts +# Generic devices +plgpio* at fdt? early 1 plrtc* at fdt? +pluart* at fdt? psci* at fdt? early 1 syscon* at fdt? early 1 diff --git a/sys/arch/arm64/conf/RAMDISK b/sys/arch/arm64/conf/RAMDISK index 7ad78815bd3..35fe7b2f1e6 100644 --- a/sys/arch/arm64/conf/RAMDISK +++ b/sys/arch/arm64/conf/RAMDISK @@ -1,4 +1,4 @@ -# $OpenBSD: RAMDISK,v 1.67 2018/08/05 08:54:43 jsg Exp $ +# $OpenBSD: RAMDISK,v 1.68 2018/08/26 16:52:16 kettenis Exp $ # # GENERIC machine description file # @@ -86,9 +86,10 @@ xhci* at fdt? # NS16550 compatible serial ports com* at fdt? -# Virt on-chip devices -pluart* at fdt? # onboard uarts +# Generic devices +plgpio* at fdt? early 1 plrtc* at fdt? +pluart* at fdt? psci* at fdt? early 1 syscon* at fdt? early 1 diff --git a/sys/dev/fdt/files.fdt b/sys/dev/fdt/files.fdt index c918e448e2f..b7fc3dcbfaa 100644 --- a/sys/dev/fdt/files.fdt +++ b/sys/dev/fdt/files.fdt @@ -1,4 +1,4 @@ -# $OpenBSD: files.fdt,v 1.68 2018/08/02 14:09:32 patrick Exp $ +# $OpenBSD: files.fdt,v 1.69 2018/08/26 16:52:16 kettenis Exp $ # # Config file and device description for machine-independent FDT code. # Included by ports that need it. @@ -73,6 +73,11 @@ device exrtc attach exrtc at fdt file dev/fdt/exrtc.c exrtc +# ARM PrimeCell PL061 General Purpose Input/Output +device plgpio +attach plgpio at fdt +file dev/fdt/plgpio.c plgpio + # ARM PrimeCell PL031 Real-time clock device plrtc attach plrtc at fdt diff --git a/sys/dev/fdt/plgpio.c b/sys/dev/fdt/plgpio.c new file mode 100644 index 00000000000..c1ad923ec89 --- /dev/null +++ b/sys/dev/fdt/plgpio.c @@ -0,0 +1,153 @@ +/* $OpenBSD: plgpio.c,v 1.1 2018/08/26 16:52:16 kettenis Exp $ */ +/* + * Copyright (c) 2018 Mark Kettenis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* Registers. */ +#define GPIODATA(pin) ((1 << pin) << 2) +#define GPIODIR 0x400 + +#define HREAD1(sc, reg) \ + (bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))) +#define HWRITE1(sc, reg, val) \ + bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) +#define HSET1(sc, reg, bits) \ + HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits)) +#define HCLR1(sc, reg, bits) \ + HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits)) + +struct plgpio_softc { + struct device sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + + struct gpio_controller sc_gc; +}; + +int plgpio_match(struct device *, void *, void *); +void plgpio_attach(struct device *, struct device *, void *); + +struct cfattach plgpio_ca = { + sizeof (struct plgpio_softc), plgpio_match, plgpio_attach +}; + +struct cfdriver plgpio_cd = { + NULL, "plgpio", DV_DULL +}; + +void plgpio_config_pin(void *, uint32_t *, int); +int plgpio_get_pin(void *, uint32_t *); +void plgpio_set_pin(void *, uint32_t *, int); + +int +plgpio_match(struct device *parent, void *match, void *aux) +{ + struct fdt_attach_args *faa = aux; + + return OF_is_compatible(faa->fa_node, "arm,pl061"); +} + +void +plgpio_attach(struct device *parent, struct device *self, void *aux) +{ + struct plgpio_softc *sc = (struct plgpio_softc *)self; + struct fdt_attach_args *faa = aux; + + if (faa->fa_nreg < 1) { + printf(": no registers\n"); + return; + } + + sc->sc_iot = faa->fa_iot; + + if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, + faa->fa_reg[0].size, 0, &sc->sc_ioh)) { + printf(": can't map registers\n"); + return; + } + + sc->sc_gc.gc_node = faa->fa_node; + sc->sc_gc.gc_cookie = sc; + sc->sc_gc.gc_config_pin = plgpio_config_pin; + sc->sc_gc.gc_get_pin = plgpio_get_pin; + sc->sc_gc.gc_set_pin = plgpio_set_pin; + gpio_controller_register(&sc->sc_gc); + + printf("\n"); +} + +void +plgpio_config_pin(void *cookie, uint32_t *cells, int config) +{ + struct plgpio_softc *sc = cookie; + uint32_t pin = cells[0]; + + if (pin > 8) + return; + + if (config & GPIO_CONFIG_OUTPUT) + HSET1(sc, GPIODIR, (1 << pin)); + else + HCLR1(sc, GPIODIR, (1 << pin)); +} + +int +plgpio_get_pin(void *cookie, uint32_t *cells) +{ + struct plgpio_softc *sc = cookie; + uint32_t pin = cells[0]; + uint32_t flags = cells[1]; + uint32_t reg; + int val; + + if (pin > 8) + return 0; + + reg = HREAD1(sc, GPIODATA(pin)); + val = !!reg; + if (flags & GPIO_ACTIVE_LOW) + val = !val; + return val; +} + +void +plgpio_set_pin(void *cookie, uint32_t *cells, int val) +{ + struct plgpio_softc *sc = cookie; + uint32_t pin = cells[0]; + uint32_t flags = cells[1]; + + if (pin > 8) + return; + + if (flags & GPIO_ACTIVE_LOW) + val = !val; + if (val) + HWRITE1(sc, GPIODATA(pin), (1 << pin)); + else + HWRITE1(sc, GPIODATA(pin), 0); +}