From: kettenis Date: Fri, 3 Aug 2018 18:36:01 +0000 (+0000) Subject: Implement single-stepping. Based on an earlier diff from drahn@. X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=1ca21ddba7b166db00c776910cd5f01f54f7af28;p=openbsd Implement single-stepping. Based on an earlier diff from drahn@. Disable userland debug communication access while there. ok patrick@ --- diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c index 2daa3714c4c..74879ff8a48 100644 --- a/sys/arch/arm64/arm64/cpu.c +++ b/sys/arch/arm64/arm64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.20 2018/08/03 16:45:17 kettenis Exp $ */ +/* $OpenBSD: cpu.c,v 1.21 2018/08/03 18:36:01 kettenis Exp $ */ /* * Copyright (c) 2016 Dale Rahn @@ -296,6 +296,10 @@ cpu_attach(struct device *parent, struct device *dev, void *aux) cpu_node = ci->ci_node; cpu_cpuspeed = cpu_clockspeed; } + + /* Initialize debug registers. */ + WRITE_SPECIALREG(mdscr_el1, DBG_MDSCR_TDCC); + WRITE_SPECIALREG(oslar_el1, 0); #ifdef MULTIPROCESSOR } #endif @@ -445,6 +449,10 @@ cpu_start_secondary(struct cpu_info *ci) tcr |= TCR_A1; WRITE_SPECIALREG(tcr_el1, tcr); + /* Initialize debug registers. */ + WRITE_SPECIALREG(mdscr_el1, DBG_MDSCR_TDCC); + WRITE_SPECIALREG(oslar_el1, 0); + s = splhigh(); arm_intr_cpu_enable(); cpu_startclock(); diff --git a/sys/arch/arm64/arm64/exception.S b/sys/arch/arm64/arm64/exception.S index 33ad82f52c6..ee8b7454ed8 100644 --- a/sys/arch/arm64/arm64/exception.S +++ b/sys/arch/arm64/arm64/exception.S @@ -1,4 +1,4 @@ -/* $OpenBSD: exception.S,v 1.7 2018/07/19 17:38:12 drahn Exp $ */ +/* $OpenBSD: exception.S,v 1.8 2018/08/03 18:36:01 kettenis Exp $ */ /*- * Copyright (c) 2014 Andrew Turner * All rights reserved. @@ -31,6 +31,8 @@ __FBSDID("$FreeBSD: head/sys/arm64/arm64/exception.S 297028 2016-03-18 16:18:29Z andrew $"); #endif +#include + #include "assym.h" .text @@ -141,6 +143,23 @@ __FBSDID("$FreeBSD: head/sys/arm64/arm64/exception.S 297028 2016-03-18 16:18:29Z 2: .endm +.macro disable_ss + mrs x2, mdscr_el1 + and x2, x2, #(~DBG_MDSCR_SS) + msr mdscr_el1, x2 +.endm + +.macro allow_ss + mrs x2, tpidr_el1 + ldr x2, [x2, #(CI_CURPCB)] + ldr w2, [x2, #(PCB_FLAGS)] + tbz w2, #1, 1f /* PCB_SINGLESTEP bit */ + mrs x2, mdscr_el1 + orr x2, x2, #(DBG_MDSCR_SS) + msr mdscr_el1, x2 +1: +.endm + handle_el1h_sync: save_registers 1 mov x0, sp @@ -170,10 +189,12 @@ handle_el1h_error: .type handle_el0_sync,@function handle_el0_sync: save_registers 0 + disable_ss mov x0, sp bl do_el0_sync do_ast bl _C_LABEL(vfp_enable) + allow_ss restore_registers 0 return @@ -181,11 +202,13 @@ handle_el0_sync: .type handle_el0_irq,@function handle_el0_irq: save_registers 0 + disable_ss bl _C_LABEL(vfp_save) mov x0, sp bl arm_cpu_intr do_ast bl _C_LABEL(vfp_enable) + allow_ss restore_registers 0 return @@ -193,6 +216,7 @@ handle_el0_irq: .type handle_el0_error,@function handle_el0_error: save_registers 0 + disable_ss mov x0, sp bl do_el0_error brk 0xf23 diff --git a/sys/arch/arm64/arm64/process_machdep.c b/sys/arch/arm64/arm64/process_machdep.c index 0c6e0c444ac..0d19fe8b3d3 100644 --- a/sys/arch/arm64/arm64/process_machdep.c +++ b/sys/arch/arm64/arm64/process_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: process_machdep.c,v 1.4 2018/07/04 17:52:29 drahn Exp $ */ +/* $OpenBSD: process_machdep.c,v 1.5 2018/08/03 18:36:01 kettenis Exp $ */ /* * Copyright (c) 2014 Patrick Wildt * @@ -87,7 +87,7 @@ process_write_regs(struct proc *p, struct reg *regs) tf->tf_lr = regs->r_lr; tf->tf_sp = regs->r_sp; tf->tf_elr = regs->r_pc; - tf->tf_spsr = (0xff0f0000 & regs->r_spsr) | (tf->tf_spsr & 0x0000ffff); + tf->tf_spsr = (0xff0f0000 & regs->r_spsr) | (tf->tf_spsr & 0x0020ffff); p->p_addr->u_pcb.pcb_tcb = (void *)regs->r_tpidr; return(0); } @@ -104,10 +104,14 @@ process_write_fpregs(struct proc *p, struct fpreg *regs) int process_sstep(struct proc *p, int sstep) { + struct trapframe *tf = p->p_addr->u_pcb.pcb_tf; + if (sstep) { p->p_addr->u_pcb.pcb_flags |= PCB_SINGLESTEP; + tf->tf_spsr |= PSR_SS; } else { p->p_addr->u_pcb.pcb_flags &= ~(PCB_SINGLESTEP); + tf->tf_spsr &= ~PSR_SS; } return 0; } diff --git a/sys/arch/arm64/arm64/trap.c b/sys/arch/arm64/arm64/trap.c index 6e493a4e15f..56000bcaec6 100644 --- a/sys/arch/arm64/arm64/trap.c +++ b/sys/arch/arm64/arm64/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.19 2018/04/12 17:13:43 deraadt Exp $ */ +/* $OpenBSD: trap.c,v 1.20 2018/08/03 18:36:01 kettenis Exp $ */ /*- * Copyright (c) 2014 Andrew Turner * All rights reserved. @@ -299,6 +299,13 @@ do_el0_sync(struct trapframe *frame) trapsignal(p, SIGTRAP, 0, TRAP_BRKPT, sv); KERNEL_UNLOCK(); break; + case EXCP_SOFTSTP_EL0: + vfp_save(); + sv.sival_ptr = (void *)frame->tf_elr; + KERNEL_LOCK(); + trapsignal(p, SIGTRAP, 0, TRAP_TRACE, sv); + KERNEL_UNLOCK(); + break; default: // panic("Unknown userland exception %x esr_el1 %lx\n", exception, // esr); diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h index 4cdbd25c40f..3700c3c8792 100644 --- a/sys/arch/arm64/include/armreg.h +++ b/sys/arch/arm64/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.5 2017/08/06 20:05:24 kettenis Exp $ */ +/* $OpenBSD: armreg.h,v 1.6 2018/08/03 18:36:01 kettenis Exp $ */ /*- * Copyright (c) 2013, 2014 Andrew Turner * Copyright (c) 2015 The FreeBSD Foundation @@ -490,11 +490,9 @@ #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) -/* Saved Program Status Register */ -#define DBG_SPSR_SS (0x1 << 21) - /* Monitor Debug System Control Register */ #define DBG_MDSCR_SS (0x1 << 0) +#define DBG_MDSCR_TDCC (0x1 << 12) #define DBG_MDSCR_KDE (0x1 << 13) #define DBG_MDSCR_MDE (0x1 << 15)