From: jsg Date: Thu, 11 Apr 2024 03:40:05 +0000 (+0000) Subject: drm/i915/gt: Enable only one CCS for compute workload X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=0fe191bfa9a408aff4162f47f33bc20579dd6c7d;p=openbsd drm/i915/gt: Enable only one CCS for compute workload From Andi Shyti a7ff84a6fe5ae8889a5f1c97008358836bd7f947 in linux-6.6.y/6.6.26 6db31251bb265813994bfb104eb4b4d0f44d64fb in mainline linux --- diff --git a/sys/dev/pci/drm/files.drm b/sys/dev/pci/drm/files.drm index eafa82df5ea..c53c5117ac1 100644 --- a/sys/dev/pci/drm/files.drm +++ b/sys/dev/pci/drm/files.drm @@ -1,4 +1,4 @@ -# $OpenBSD: files.drm,v 1.62 2024/01/22 18:54:01 kettenis Exp $ +# $OpenBSD: files.drm,v 1.63 2024/04/11 03:40:05 jsg Exp $ #file dev/pci/drm/aperture.c drm file dev/pci/drm/dma-resv.c drm @@ -292,6 +292,7 @@ file dev/pci/drm/i915/gt/intel_ggtt_gmch.c inteldrm file dev/pci/drm/i915/gt/intel_gsc.c inteldrm file dev/pci/drm/i915/gt/intel_gt.c inteldrm file dev/pci/drm/i915/gt/intel_gt_buffer_pool.c inteldrm +file dev/pci/drm/i915/gt/intel_gt_ccs_mode.c inteldrm file dev/pci/drm/i915/gt/intel_gt_clock_utils.c inteldrm file dev/pci/drm/i915/gt/intel_gt_debugfs.c inteldrm file dev/pci/drm/i915/gt/intel_gt_engines_debugfs.c inteldrm diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c new file mode 100644 index 00000000000..044219c5960 --- /dev/null +++ b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "i915_drv.h" +#include "intel_gt.h" +#include "intel_gt_ccs_mode.h" +#include "intel_gt_regs.h" + +void intel_gt_apply_ccs_mode(struct intel_gt *gt) +{ + int cslice; + u32 mode = 0; + int first_ccs = __ffs(CCS_MASK(gt)); + + if (!IS_DG2(gt->i915)) + return; + + /* Build the value for the fixed CCS load balancing */ + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { + if (CCS_MASK(gt) & BIT(cslice)) + /* + * If available, assign the cslice + * to the first available engine... + */ + mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); + + else + /* + * ... otherwise, mark the cslice as + * unavailable if no CCS dispatches here + */ + mode |= XEHP_CCS_MODE_CSLICE(cslice, + XEHP_CCS_MODE_CSLICE_MASK); + } + + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); +} diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h new file mode 100644 index 00000000000..9e5549caeb2 --- /dev/null +++ b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_GT_CCS_MODE_H__ +#define __INTEL_GT_CCS_MODE_H__ + +struct intel_gt; + +void intel_gt_apply_ccs_mode(struct intel_gt *gt); + +#endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h index 62bee564ca4..64acab146b5 100644 --- a/sys/dev/pci/drm/i915/gt/intel_gt_regs.h +++ b/sys/dev/pci/drm/i915/gt/intel_gt_regs.h @@ -1471,6 +1471,11 @@ #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */ +#define XEHP_CCS_MODE_CSLICE_WIDTH ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1) +#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) + #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) #define CHV_FGT_DISABLE_SS1 (1 << 11) diff --git a/sys/dev/pci/drm/i915/gt/intel_workarounds.c b/sys/dev/pci/drm/i915/gt/intel_workarounds.c index 7d3dc854817..be060b32bd9 100644 --- a/sys/dev/pci/drm/i915/gt/intel_workarounds.c +++ b/sys/dev/pci/drm/i915/gt/intel_workarounds.c @@ -10,6 +10,7 @@ #include "intel_engine_regs.h" #include "intel_gpu_commands.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_mcr.h" #include "intel_gt_regs.h" #include "intel_ring.h" @@ -2838,6 +2839,12 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * made to completely disable automatic CCS load balancing. */ wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); + + /* + * After having disabled automatic load balancing we need to + * assign all slices to a single CCS. We will call it CCS mode 1 + */ + intel_gt_apply_ccs_mode(gt); } /*