From: kettenis Date: Sat, 23 Sep 2023 18:29:55 +0000 (+0000) Subject: Add stfrng(4), a driver for the random number generator on the JH7110 SoC. X-Git-Url: http://artulab.com/gitweb/?a=commitdiff_plain;h=009ac9880fffef6cf30783fc4a5e6a9ae7295205;p=openbsd Add stfrng(4), a driver for the random number generator on the JH7110 SoC. ok joel@, jca@ --- diff --git a/sys/arch/riscv64/conf/GENERIC b/sys/arch/riscv64/conf/GENERIC index 292cf35ed45..d06351a8323 100644 --- a/sys/arch/riscv64/conf/GENERIC +++ b/sys/arch/riscv64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.46 2023/08/29 16:04:21 kettenis Exp $ +# $OpenBSD: GENERIC,v 1.47 2023/09/23 18:29:55 kettenis Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -65,6 +65,7 @@ stfpcie* at fdt? pci* at stfpcie? stfpciephy* at fdt? early 1 stfpinctrl* at fdt? early 1 +stfrng* at fdt? stftemp* at fdt? virtio* at fdt? diff --git a/sys/arch/riscv64/conf/RAMDISK b/sys/arch/riscv64/conf/RAMDISK index 3c1d2cc5c95..ba4bd885557 100644 --- a/sys/arch/riscv64/conf/RAMDISK +++ b/sys/arch/riscv64/conf/RAMDISK @@ -1,4 +1,4 @@ -# $OpenBSD: RAMDISK,v 1.39 2023/07/08 10:06:13 kettenis Exp $ +# $OpenBSD: RAMDISK,v 1.40 2023/09/23 18:29:55 kettenis Exp $ machine riscv64 maxusers 4 @@ -56,6 +56,7 @@ stfpcie* at fdt? pci* at stfpcie? stfpciephy* at fdt? early 1 stfpinctrl* at fdt? early 1 +stfrng* at fdt? virtio* at fdt? virtio* at pci? diff --git a/sys/arch/riscv64/conf/files.riscv64 b/sys/arch/riscv64/conf/files.riscv64 index d69543ee356..b415c7e2db7 100644 --- a/sys/arch/riscv64/conf/files.riscv64 +++ b/sys/arch/riscv64/conf/files.riscv64 @@ -1,4 +1,4 @@ -# $OpenBSD: files.riscv64,v 1.26 2023/08/21 20:17:30 miod Exp $ +# $OpenBSD: files.riscv64,v 1.27 2023/09/23 18:29:55 kettenis Exp $ # Standard stanzas config(8) can't run without maxpartitions 16 @@ -138,6 +138,11 @@ device stfpinctrl attach stfpinctrl at fdt file arch/riscv64/dev/stfpinctrl.c stfpinctrl +# StarFive random number generator +device stfrng +attach stfrng at fdt +file arch/riscv64/dev/stfrng.c stfrng + # StarFive temperature sensor device stftemp attach stftemp at fdt diff --git a/sys/arch/riscv64/dev/stfclock.c b/sys/arch/riscv64/dev/stfclock.c index 8684cbd059f..c2dec12742f 100644 --- a/sys/arch/riscv64/dev/stfclock.c +++ b/sys/arch/riscv64/dev/stfclock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: stfclock.c,v 1.11 2023/09/19 19:15:08 kettenis Exp $ */ +/* $OpenBSD: stfclock.c,v 1.12 2023/09/23 18:29:55 kettenis Exp $ */ /* * Copyright (c) 2022 Mark Kettenis * Copyright (c) 2023 Joel Sing @@ -85,6 +85,8 @@ #define JH7110_STGCLK_PCIE1_AXI_MST0 11 #define JH7110_STGCLK_PCIE1_APB 12 #define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 #define JH7110_STGCLK_ASSERT_OFFSET 0x74 #define JH7110_STGCLK_STATUS_OFFSET 0x78 @@ -810,6 +812,8 @@ stfclock_enable_jh7110_stg(void *cookie, uint32_t *cells, int on) case JH7110_STGCLK_PCIE1_AXI_MST0: case JH7110_STGCLK_PCIE1_APB: case JH7110_STGCLK_PCIE1_TL: + case JH7110_STGCLK_SEC_AHB: + case JH7110_STGCLK_SEC_MISC_AHB: if (on) HSET4(sc, idx * 4, 1U << 31); else diff --git a/sys/arch/riscv64/dev/stfrng.c b/sys/arch/riscv64/dev/stfrng.c new file mode 100644 index 00000000000..721433e348e --- /dev/null +++ b/sys/arch/riscv64/dev/stfrng.c @@ -0,0 +1,146 @@ +/* $OpenBSD: stfrng.c,v 1.1 2023/09/23 18:29:55 kettenis Exp $ */ +/* + * Copyright (c) 2023 Mark Kettenis + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +/* Registers */ +#define RNG_CTRL 0x0000 +#define RNG_CTRL_RANDOMIZE 0x1 +#define RNG_CTRL_RESEED 0x2 +#define RNG_STAT 0x0004 +#define RNG_STAT_SEEDED (1 << 9) +#define RNG_MODE 0x000c +#define RNG_MODE_R256 (1 << 3) +#define RNG_ISTAT 0x0014 +#define RNG_ISTAT_RAND_RDY (1 << 0) +#define RNG_ISTAT_LFSR_LOCKUP (1 << 4) +#define RNG_DATA0 0x0020 +#define RNG_DATA1 0x0024 +#define RNG_DATA2 0x0028 +#define RNG_DATA3 0x002c +#define RNG_DATA4 0x0030 +#define RNG_DATA5 0x0034 +#define RNG_DATA6 0x0038 +#define RNG_DATA7 0x003c + +#define HREAD4(sc, reg) \ + (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) +#define HWRITE4(sc, reg, val) \ + bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) + +struct stfrng_softc { + struct device sc_dev; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + + struct timeout sc_to; +}; + +int stfrng_match(struct device *, void *, void *); +void stfrng_attach(struct device *, struct device *, void *); + +const struct cfattach stfrng_ca = { + sizeof (struct stfrng_softc), stfrng_match, stfrng_attach +}; + +struct cfdriver stfrng_cd = { + NULL, "stfrng", DV_DULL +}; + +void stfrng_rnd(void *); + +int +stfrng_match(struct device *parent, void *match, void *aux) +{ + struct fdt_attach_args *faa = aux; + + return OF_is_compatible(faa->fa_node, "starfive,jh7110-trng"); +} + +void +stfrng_attach(struct device *parent, struct device *self, void *aux) +{ + struct stfrng_softc *sc = (struct stfrng_softc *)self; + struct fdt_attach_args *faa = aux; + + if (faa->fa_nreg < 1) { + printf(": no registers\n"); + return; + } + + sc->sc_iot = faa->fa_iot; + if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, + faa->fa_reg[0].size, 0, &sc->sc_ioh)) { + printf(": can't map registers\n"); + return; + } + + printf("\n"); + + clock_enable(faa->fa_node, "hclk"); + clock_enable(faa->fa_node, "ahb"); + reset_deassert(faa->fa_node, NULL); + + /* Clear all interrupts. */ + HWRITE4(sc, RNG_ISTAT, 0xffffffff); + + HWRITE4(sc, RNG_MODE, RNG_MODE_R256); + HWRITE4(sc, RNG_CTRL, RNG_CTRL_RESEED); + + timeout_set(&sc->sc_to, stfrng_rnd, sc); + stfrng_rnd(sc); +} + +void +stfrng_rnd(void *arg) +{ + struct stfrng_softc *sc = arg; + uint32_t stat, istat; + + stat = HREAD4(sc, RNG_STAT); + if (stat & RNG_STAT_SEEDED) { + istat = HREAD4(sc, RNG_ISTAT); + if (istat & RNG_ISTAT_RAND_RDY) { + HWRITE4(sc, RNG_ISTAT, RNG_ISTAT_RAND_RDY); + enqueue_randomness(HREAD4(sc, RNG_DATA0)); + enqueue_randomness(HREAD4(sc, RNG_DATA1)); + enqueue_randomness(HREAD4(sc, RNG_DATA2)); + enqueue_randomness(HREAD4(sc, RNG_DATA3)); + enqueue_randomness(HREAD4(sc, RNG_DATA4)); + enqueue_randomness(HREAD4(sc, RNG_DATA5)); + enqueue_randomness(HREAD4(sc, RNG_DATA6)); + enqueue_randomness(HREAD4(sc, RNG_DATA7)); + } + + if (istat & RNG_ISTAT_LFSR_LOCKUP) + HWRITE4(sc, RNG_CTRL, RNG_CTRL_RESEED); + else + HWRITE4(sc, RNG_CTRL, RNG_CTRL_RANDOMIZE); + } + + timeout_add_sec(&sc->sc_to, 1); +}