drm/amdgpu: Reset IH OVERFLOW_CLEAR bit

From Friedrich Vock
8983397951b4b0bd51bb4b4ba9749424e1ccbb70 in linux-6.6.y/6.6.18
7330256268664ea0a7dd5b07a3fed363093477dd in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/cik_ih.c b/sys/dev/pci/drm/amd/amdgpu/cik_ih.c
index 6f7c031..f24e34d 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/cik_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/cik_ih.c
@@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
                tmp = RREG32(mmIH_RB_CNTL);
                tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
                WREG32(mmIH_RB_CNTL, tmp);
+
+               /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+                * can be detected.
+                */
+               tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
+               WREG32(mmIH_RB_CNTL, tmp);
        }
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/cz_ih.c b/sys/dev/pci/drm/amd/amdgpu/cz_ih.c
index b8c47e0..c196814 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/cz_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/cz_ih.c
@@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32(mmIH_RB_CNTL, tmp);
 
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32(mmIH_RB_CNTL, tmp);
 
 out:
        return (wptr & ih->ptr_mask);

diff --git a/sys/dev/pci/drm/amd/amdgpu/iceland_ih.c b/sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
index aecad53..2c02ae6 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
@@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32(mmIH_RB_CNTL, tmp);
 
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32(mmIH_RB_CNTL, tmp);
 
 out:
        return (wptr & ih->ptr_mask);

diff --git a/sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c b/sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
index ec0c8f8..f432dc7 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
@@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
        tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 out:
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c b/sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
index 8fb05ea..b8da0fc 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
+++ b/sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
@@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
        tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
 out:
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/navi10_ih.c b/sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
index b6a8478..737eff5 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
@@ -442,6 +442,12 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
        tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 out:
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/si_ih.c b/sys/dev/pci/drm/amd/amdgpu/si_ih.c
index 9a24f17..cada9f3 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/si_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/si_ih.c
@@ -119,6 +119,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
                tmp = RREG32(IH_RB_CNTL);
                tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
                WREG32(IH_RB_CNTL, tmp);
+
+               /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+                * can be detected.
+                */
+               tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
+               WREG32(IH_RB_CNTL, tmp);
        }
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/tonga_ih.c b/sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
index 917707b..450b6e8 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
@@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32(mmIH_RB_CNTL, tmp);
 
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32(mmIH_RB_CNTL, tmp);
+
 out:
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/vega10_ih.c b/sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
index d364c6d..bf68e18 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
@@ -373,6 +373,12 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
 out:
        return (wptr & ih->ptr_mask);
 }

diff --git a/sys/dev/pci/drm/amd/amdgpu/vega20_ih.c b/sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
index dbc9953..131e7b7 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
+++ b/sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
@@ -421,6 +421,12 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
        WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 
+       /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
+        * can be detected.
+        */
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
+       WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
+
 out:
        return (wptr & ih->ptr_mask);
 }