drm/amdgpu: Indicate CU havest info to CP

From Harish Kasiviswanathan
86a6a3964f600d458412295ac8d705b6b9a8efdb in linux-6.6.y/6.6.42
49c9ffabde555c841392858d8b9e6cf58998a50c in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
index d061928..b9c3e83 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4290,9 +4290,10 @@ static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_i
 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
                                 struct amdgpu_cu_info *cu_info)
 {
-       int i, j, k, counter, xcc_id, active_cu_number = 0;
-       u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
+       int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;
+       u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;
        unsigned disable_masks[4 * 4];
+       bool is_symmetric_cus;
 
        if (!adev || !cu_info)
                return -EINVAL;
@@ -4310,6 +4311,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
+               is_symmetric_cus = true;
                for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                        for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
                                mask = 1;
@@ -4337,6 +4339,15 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
                                        ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
                                cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
                        }
+                       if (i && is_symmetric_cus && prev_counter != counter)
+                               is_symmetric_cus = false;
+                       prev_counter = counter;
+               }
+               if (is_symmetric_cus) {
+                       tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);
+                       tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);
+                       tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);
+                       WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);
                }
                gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
                                            xcc_id);