drm/amdkfd: fix mes set shader debugger process management

From Jonathan Kim
3a950c56dea199d65bc98db348c017856aa2f194 in linux-6.6.y/6.6.16
bd33bb1409b494558a2935f7bbc7842def957fcd in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
index 93a59e9..a88eff2 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
@@ -885,6 +885,11 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
        op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
        op_input.set_shader_debugger.process_context_addr = process_context_addr;
        op_input.set_shader_debugger.flags.u32all = flags;
+
+       /* use amdgpu mes_flush_shader_debugger instead */
+       if (op_input.set_shader_debugger.flags.process_ctx_flush)
+               return -EINVAL;
+
        op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl;
        memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
                        sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
@@ -904,6 +909,32 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
        return r;
 }
 
+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
+                                    uint64_t process_context_addr)
+{
+       struct mes_misc_op_input op_input = {0};
+       int r;
+
+       if (!adev->mes.funcs->misc_op) {
+               DRM_ERROR("mes flush shader debugger is not supported!\n");
+               return -EINVAL;
+       }
+
+       op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
+       op_input.set_shader_debugger.process_context_addr = process_context_addr;
+       op_input.set_shader_debugger.flags.process_ctx_flush = true;
+
+       amdgpu_mes_lock(&adev->mes);
+
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       if (r)
+               DRM_ERROR("failed to set_shader_debugger\n");
+
+       amdgpu_mes_unlock(&adev->mes);
+
+       return r;
+}
+
 static void
 amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
                               struct amdgpu_ring *ring,

diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h b/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
index 2980873..f1683c5 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
@@ -293,9 +293,10 @@ struct mes_misc_op_input {
                        uint64_t process_context_addr;
                        union {
                                struct {
-                                       uint64_t single_memop : 1;
-                                       uint64_t single_alu_op : 1;
-                                       uint64_t reserved: 30;
+                                       uint32_t single_memop : 1;
+                                       uint32_t single_alu_op : 1;
+                                       uint32_t reserved: 29;
+                                       uint32_t process_ctx_flush: 1;
                                };
                                uint32_t u32all;
                        } flags;
@@ -371,7 +372,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
                                const uint32_t *tcp_watch_cntl,
                                uint32_t flags,
                                bool trap_en);
-
+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
+                               uint64_t process_context_addr);
 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
                        int queue_type, int idx,
                        struct amdgpu_mes_ctx_data *ctx_data,

diff --git a/sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c b/sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
index 77f4932..8e55e78 100644 (file)
--- a/sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -87,6 +87,7 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
                return;
 
        dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
+       amdgpu_mes_flush_shader_debugger(dev->adev, pdd->proc_ctx_gpu_addr);
        pdd->already_dequeued = true;
 }
 

diff --git a/sys/dev/pci/drm/amd/include/mes_v11_api_def.h b/sys/dev/pci/drm/amd/include/mes_v11_api_def.h
index b1db2b1..e07e931 100644 (file)
--- a/sys/dev/pci/drm/amd/include/mes_v11_api_def.h
+++ b/sys/dev/pci/drm/amd/include/mes_v11_api_def.h
@@ -571,7 +571,8 @@ struct SET_SHADER_DEBUGGER {
                struct {
                        uint32_t single_memop : 1;  /* SQ_DEBUG.single_memop */
                        uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
-                       uint32_t reserved : 30;
+                       uint32_t reserved : 29;
+                       uint32_t process_ctx_flush : 1;
                };
                uint32_t u32all;
        } flags;