drm/amdgpu: access RLC_SPM_MC_CNTL through MMIO in SRIOV runtime

From ZhenGuo Yin
ec71cc24b0d4cd0091fbb427bef1a6d3655793ca in linux-6.6.y/6.6.48
9f05cfc78c6880e06940ea78fbc43f6392710f17 in mainline linux

diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
index 744fd26..699e182 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
@@ -7892,22 +7892,15 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
                                               unsigned int vmid)
 {
-       u32 reg, data;
+       u32 data;
 
        /* not for *_SOC15 */
-       reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               data = RREG32_NO_KIQ(reg);
-       else
-               data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+       data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
-       else
-               WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)

diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
index 767e67b..e617c28 100644 (file)
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
@@ -4961,23 +4961,16 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 
 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
-       u32 reg, data;
+       u32 data;
 
        amdgpu_gfx_off_ctrl(adev, false);
 
-       reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               data = RREG32_NO_KIQ(reg);
-       else
-               data = RREG32(reg);
+       data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
-       else
-               WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
+       WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
 
        amdgpu_gfx_off_ctrl(adev, true);
 }