The ARMv7 ARM says that the TLB may hold translation table entries at any

level of the translation table, including entries that point to further
levels of the tables.  This means that we have to do a TLB flush whenever
we invalidate an L1 slot too.  Doing so fixes the pmap_fault_fixup
issue on Cortex-A7 processors.

diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c
index fbd7a13..9c61448 100644 (file)
--- a/sys/arch/arm/arm/pmap7.c
+++ b/sys/arch/arm/arm/pmap7.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pmap7.c,v 1.36 2016/08/09 13:13:51 kettenis Exp $     */
+/*     $OpenBSD: pmap7.c,v 1.37 2016/08/11 00:28:06 kettenis Exp $     */
 /*     $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $   */
 
 /*
@@ -850,6 +850,7 @@ pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
        if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
                *pl1pd = L1_TYPE_INV;
                PTE_SYNC(pl1pd);
+               pmap_tlb_flushID_SE(pm, l1idx << L1_S_SHIFT);
        }
 
        /*