Add a few missing sunxi-h3 clocks and resets.

diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 46e22af..af4784e 100644 (file)
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: sxiccmu.c,v 1.17 2016/08/27 16:41:52 kettenis Exp $   */
+/*     $OpenBSD: sxiccmu.c,v 1.18 2016/08/28 20:17:10 kettenis Exp $   */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -245,6 +245,10 @@ struct sxiccmu_device sxiccmu_devices[] = {
                .compat = "allwinner,sun6i-a31-ahb1-reset",
                .reset = sxiccmu_reset
        },
+       {
+               .compat = "allwinner,sun6i-a31-clock-reset",
+               .reset = sxiccmu_reset
+       },
        {
                .compat = "allwinner,sun7i-a20-ahb-gates-clk",
                .get_frequency = sxiccmu_gen_get_frequency,

diff --git a/sys/arch/armv7/sunxi/sxiccmu_clocks.h b/sys/arch/armv7/sunxi/sxiccmu_clocks.h
index bfe51fa..8d6b607 100644 (file)
--- a/sys/arch/armv7/sunxi/sxiccmu_clocks.h
+++ b/sys/arch/armv7/sunxi/sxiccmu_clocks.h
@@ -22,6 +22,8 @@
 #define H3_CLK_BUS_OHCI2       39
 #define H3_CLK_BUS_OHCI3       40
 
+#define H3_CLK_BUS_PIO         54
+
 #define H3_CLK_BUS_UART0       62
 #define H3_CLK_BUS_UART1       63
 #define H3_CLK_BUS_UART2       64
@@ -48,6 +50,7 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
        [H3_CLK_BUS_OHCI1] = { 0x0060, 29 },
        [H3_CLK_BUS_OHCI2] = { 0x0060, 30 },
        [H3_CLK_BUS_OHCI3] = { 0x0060, 31 },
+       [H3_CLK_BUS_PIO]   = { 0x0068, 5 },
        [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 },
        [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 },
        [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 },