Decode remaining ID_AA64ISAR1_EL1 features.

ok jsg@

diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c
index 112afeb..e8a762c 100644 (file)
--- a/sys/arch/arm64/arm64/cpu.c
+++ b/sys/arch/arm64/arm64/cpu.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: cpu.c,v 1.115 2024/05/26 13:37:31 kettenis Exp $      */
+/*     $OpenBSD: cpu.c,v 1.116 2024/05/27 06:20:59 kettenis Exp $      */
 
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
@@ -742,6 +742,37 @@ cpu_identify(struct cpu_info *ci)
         */
        id = READ_SPECIALREG(id_aa64isar1_el1);
 
+       if (ID_AA64ISAR1_LS64(id) >= ID_AA64ISAR1_LS64_BASE) {
+               printf("%sLS64", sep);
+               sep = ",";
+       }
+       if (ID_AA64ISAR1_LS64(id) >= ID_AA64ISAR1_LS64_V)
+               printf("+V");
+       if (ID_AA64ISAR1_LS64(id) >= ID_AA64ISAR1_LS64_ACCDATA)
+               printf("+ACCDATA");
+
+       if (ID_AA64ISAR1_XS(id) >= ID_AA64ISAR1_XS_IMPL) {
+               printf("%sXS", sep);
+               sep = ",";
+       }
+
+       if (ID_AA64ISAR1_I8MM(id) >= ID_AA64ISAR1_I8MM_IMPL) {
+               printf("%sI8MM", sep);
+               sep = ",";
+       }
+
+       if (ID_AA64ISAR1_DGH(id) >= ID_AA64ISAR1_DGH_IMPL) {
+               printf("%sDGH", sep);
+               sep = ",";
+       }
+
+       if (ID_AA64ISAR1_BF16(id) >= ID_AA64ISAR1_BF16_BASE) {
+               printf("%sBF16", sep);
+               sep = ",";
+       }
+       if (ID_AA64ISAR1_BF16(id) >= ID_AA64ISAR1_BF16_EBF)
+               printf("+EBF");
+
        if (ID_AA64ISAR1_SPECRES(id) >= ID_AA64ISAR1_SPECRES_IMPL) {
                printf("%sSPECRES", sep);
                sep = ",";

diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index 02ded6a..5ace1af 100644 (file)
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.33 2024/03/18 18:35:21 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.34 2024/05/27 06:20:59 kettenis Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -337,7 +337,7 @@
 #define         ID_AA64ISAR0_RNDR_IMPL         (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT)
 
 /* ID_AA64ISAR1_EL1 */
-#define        ID_AA64ISAR1_MASK               0x00000fffffffffffULL
+#define        ID_AA64ISAR1_MASK               0xffffffffffffffffULL
 #define        ID_AA64ISAR1_DPB_SHIFT          0
 #define        ID_AA64ISAR1_DPB_MASK           (0xfULL << ID_AA64ISAR1_DPB_SHIFT)
 #define        ID_AA64ISAR1_DPB(x)             ((x) & ID_AA64ISAR1_DPB_MASK)
@@ -396,6 +396,34 @@
 #define        ID_AA64ISAR1_SPECRES(x)         ((x) & ID_AA64ISAR1_SPECRES_MASK)
 #define         ID_AA64ISAR1_SPECRES_NONE      (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT)
 #define         ID_AA64ISAR1_SPECRES_IMPL      (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT)
+#define        ID_AA64ISAR1_BF16_SHIFT         44
+#define        ID_AA64ISAR1_BF16_MASK          (0xfULL << ID_AA64ISAR1_BF16_SHIFT)
+#define        ID_AA64ISAR1_BF16(x)            ((x) & ID_AA64ISAR1_BF16_MASK)
+#define         ID_AA64ISAR1_BF16_NONE         (0x0ULL << ID_AA64ISAR1_BF16_SHIFT)
+#define         ID_AA64ISAR1_BF16_BASE         (0x1ULL << ID_AA64ISAR1_BF16_SHIFT)
+#define         ID_AA64ISAR1_BF16_EBF          (0x2ULL << ID_AA64ISAR1_BF16_SHIFT)
+#define        ID_AA64ISAR1_DGH_SHIFT          48
+#define        ID_AA64ISAR1_DGH_MASK           (0xfULL << ID_AA64ISAR1_DGH_SHIFT)
+#define        ID_AA64ISAR1_DGH(x)             ((x) & ID_AA64ISAR1_DGH_MASK)
+#define         ID_AA64ISAR1_DGH_NONE          (0x0ULL << ID_AA64ISAR1_DGH_SHIFT)
+#define         ID_AA64ISAR1_DGH_IMPL          (0x1ULL << ID_AA64ISAR1_DGH_SHIFT)
+#define        ID_AA64ISAR1_I8MM_SHIFT         52
+#define        ID_AA64ISAR1_I8MM_MASK          (0xfULL << ID_AA64ISAR1_I8MM_SHIFT)
+#define        ID_AA64ISAR1_I8MM(x)            ((x) & ID_AA64ISAR1_I8MM_MASK)
+#define         ID_AA64ISAR1_I8MM_NONE         (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT)
+#define         ID_AA64ISAR1_I8MM_IMPL         (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT)
+#define        ID_AA64ISAR1_XS_SHIFT           56
+#define        ID_AA64ISAR1_XS_MASK            (0xfULL << ID_AA64ISAR1_XS_SHIFT)
+#define        ID_AA64ISAR1_XS(x)              ((x) & ID_AA64ISAR1_XS_MASK)
+#define         ID_AA64ISAR1_XS_NONE           (0x0ULL << ID_AA64ISAR1_XS_SHIFT)
+#define         ID_AA64ISAR1_XS_IMPL           (0x1ULL << ID_AA64ISAR1_XS_SHIFT)
+#define        ID_AA64ISAR1_LS64_SHIFT         60
+#define        ID_AA64ISAR1_LS64_MASK          (0xfULL << ID_AA64ISAR1_LS64_SHIFT)
+#define        ID_AA64ISAR1_LS64(x)            ((x) & ID_AA64ISAR1_LS64_MASK)
+#define         ID_AA64ISAR1_LS64_NONE         (0x0ULL << ID_AA64ISAR1_LS64_SHIFT)
+#define         ID_AA64ISAR1_LS64_BASE         (0x1ULL << ID_AA64ISAR1_LS64_SHIFT)
+#define         ID_AA64ISAR1_LS64_V            (0x2ULL << ID_AA64ISAR1_LS64_SHIFT)
+#define         ID_AA64ISAR1_LS64_ACCDATA      (0x3ULL << ID_AA64ISAR1_LS64_SHIFT)
 
 /* ID_AA64ISAR2_EL1 */
 #define        ID_AA64ISAR2_MASK               0x00000000f0000000ULL