Transactions on the AXI bus contain a Stream ID. SMMUs filter

based on Stream IDs.  On the Armada 8040 these Stream IDs can
be configured in different registers.  The PCIe controller has
a register which maps root port, bus, dev and func number to
the Stream ID.  This should be set up by TF-A firmware, but on
the 8040 the current images don't do this.  For chips with more
than one PCIe controller this register must be setup correctly
depending on the implementation, but on the 8040 there only is
one controller, so we can configure a fixed value to match what
is defined in the device tree.  This allows the SMMU to properly
track the PCIe controller's transactions.

ok kettenis@

diff --git a/sys/dev/fdt/dwpcie.c b/sys/dev/fdt/dwpcie.c
index 9da1473..9d87788 100644 (file)
--- a/sys/dev/fdt/dwpcie.c
+++ b/sys/dev/fdt/dwpcie.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: dwpcie.c,v 1.26 2021/02/28 21:06:58 patrick Exp $     */
+/*     $OpenBSD: dwpcie.c,v 1.27 2021/03/01 21:03:24 patrick Exp $     */
 /*
  * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -100,6 +100,14 @@
 #define  PCIE_AXUSER_DOMAIN_MASK               (0x3 << 4)
 #define  PCIE_AXUSER_DOMAIN_INNER_SHARABLE     (0x1 << 4)
 #define  PCIE_AXUSER_DOMAIN_OUTER_SHARABLE     (0x2 << 4)
+#define PCIE_STREAMID          0x8064
+#define  PCIE_STREAMID_FUNC_BITS(x)            ((x) << 0)
+#define  PCIE_STREAMID_DEV_BITS(x)             ((x) << 4)
+#define  PCIE_STREAMID_BUS_BITS(x)             ((x) << 8)
+#define  PCIE_STREAMID_ROOTPORT(x)             ((x) << 12)
+#define  PCIE_STREAMID_8040                    \
+    (PCIE_STREAMID_ROOTPORT(0x80) | PCIE_STREAMID_BUS_BITS(2) | \
+     PCIE_STREAMID_DEV_BITS(2) | PCIE_STREAMID_FUNC_BITS(3))
 
 /* Amlogic G12A registers */
 #define PCIE_CFG0              0x0000
@@ -621,6 +629,12 @@ dwpcie_armada8k_init(struct dwpcie_softc *sc)
                HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);
        }
 
+       /*
+        * Setup Requester-ID to Stream-ID mapping
+        * XXX: TF-A is supposed to set this up, but doesn't!
+        */
+       HWRITE4(sc, PCIE_STREAMID, PCIE_STREAMID_8040);
+
        /* Enable Root Complex mode. */
        reg = HREAD4(sc, PCIE_GLOBAL_CTRL);
        reg &= ~PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK;