-/* $OpenBSD: cpu.c,v 1.53 2021/03/17 12:03:40 kettenis Exp $ */
+/* $OpenBSD: cpu.c,v 1.54 2021/03/27 19:57:19 kettenis Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
id = READ_SPECIALREG(id_aa64isar0_el1);
sep = "";
+ if (ID_AA64ISAR0_RNDR(id) >= ID_AA64ISAR0_RNDR_IMPL) {
+ printf("%sRNDR", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR0_TLB(id) >= ID_AA64ISAR0_TLB_IOS) {
+ printf("%sTLBIOS", sep);
+ sep = ",";
+ }
+ if (ID_AA64ISAR0_TLB(id) >= ID_AA64ISAR0_TLB_IRANGE)
+ printf("+IRANGE");
+
+ if (ID_AA64ISAR0_TS(id) >= ID_AA64ISAR0_TS_BASE) {
+ printf("%sTS", sep);
+ sep = ",";
+ }
+ if (ID_AA64ISAR0_TS(id) >= ID_AA64ISAR0_TS_AXFLAG)
+ printf("+AXFLAG");
+
+ if (ID_AA64ISAR0_FHM(id) >= ID_AA64ISAR0_FHM_IMPL) {
+ printf("%sFHM", sep);
+ sep = ",";
+ }
+
if (ID_AA64ISAR0_DP(id) >= ID_AA64ISAR0_DP_IMPL) {
printf("%sDP", sep);
sep = ",";
*/
id = READ_SPECIALREG(id_aa64isar1_el1);
+ if (ID_AA64ISAR1_SPECRES(id) >= ID_AA64ISAR1_SPECRES_IMPL) {
+ printf("%sSPECRES", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_SB(id) >= ID_AA64ISAR1_SB_IMPL) {
+ printf("%sSB", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_FRINTTS(id) >= ID_AA64ISAR1_FRINTTS_IMPL) {
+ printf("%sFRINTTS", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_GPI(id) >= ID_AA64ISAR1_GPI_IMPL) {
+ printf("%sGPI", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_GPA(id) >= ID_AA64ISAR1_GPA_IMPL) {
+ printf("%sGPA", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_LRCPC(id) >= ID_AA64ISAR1_LRCPC_BASE) {
+ printf("%sLRCPC", sep);
+ sep = ",";
+ }
+ if (ID_AA64ISAR1_LRCPC(id) >= ID_AA64ISAR1_LRCPC_LDAPUR)
+ printf("+LDAPUR");
+
+ if (ID_AA64ISAR1_FCMA(id) >= ID_AA64ISAR1_FCMA_IMPL) {
+ printf("%sFCMA", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_JSCVT(id) >= ID_AA64ISAR1_JSCVT_IMPL) {
+ printf("%sJSCVT", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR1_API(id) >= ID_AA64ISAR1_API_BASE) {
+ printf("%sAPI", sep);
+ sep = ",";
+ }
+ if (ID_AA64ISAR1_API(id) >= ID_AA64ISAR1_API_PAC)
+ printf("+PAC");
+
+ if (ID_AA64ISAR1_APA(id) >= ID_AA64ISAR1_APA_BASE) {
+ printf("%sAPA", sep);
+ sep = ",";
+ }
+ if (ID_AA64ISAR1_APA(id) >= ID_AA64ISAR1_APA_PAC)
+ printf("+PAC");
+
if (ID_AA64ISAR1_DPB(id) >= ID_AA64ISAR1_DPB_IMPL) {
printf("%sDPB", sep);
sep = ",";
}
if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_SCXT)
printf("+SCTX");
+
+#ifdef CPU_DEBUG
+ id = READ_SPECIALREG(id_aa64afr0_el1);
+ printf("\nID_AA64AFR0_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64afr1_el1);
+ printf("\nID_AA64AFR1_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64dfr0_el1);
+ printf("\nID_AA64DFR0_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64dfr1_el1);
+ printf("\nID_AA64DFR1_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64isar0_el1);
+ printf("\nID_AA64ISAR0_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64isar1_el1);
+ printf("\nID_AA64ISAR1_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64mmfr0_el1);
+ printf("\nID_AA64MMFR0_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64mmfr1_el1);
+ printf("\nID_AA64MMFR1_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64mmfr2_el1);
+ printf("\nID_AA64MMFR2_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64pfr0_el1);
+ printf("\nID_AA64PFR0_EL1: 0x%016llx", id);
+ id = READ_SPECIALREG(id_aa64pfr1_el1);
+ printf("\nID_AA64PFR1_EL1: 0x%016llx", id);
+#endif
}
int cpu_hatch_secondary(struct cpu_info *ci, int, uint64_t);
-/* $OpenBSD: armreg.h,v 1.14 2021/03/11 11:16:56 jsg Exp $ */
+/* $OpenBSD: armreg.h,v 1.15 2021/03/27 19:57:19 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* Copyright (c) 2015 The FreeBSD Foundation
((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
/* ID_AA64ISAR0_EL1 */
-#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ULL
+#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT)
+#define ID_AA64ISAR0_FHM_SHIFT 48
+#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK)
+#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_TS_SHIFT 52
+#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK)
+#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TLB_SHIFT 56
+#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK)
+#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_RNDR_SHIFT 60
+#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
+#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT)
/* ID_AA64ISAR1_EL1 */
-#define ID_AA64ISAR1_MASK 0x000000000000000fULL
+#define ID_AA64ISAR1_MASK 0x00000fffffffffffULL
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_APA_SHIFT 4
+#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
+#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA_BASE (0x1 << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA_PAC (0x2 << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_API_SHIFT 8
+#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
+#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API_BASE (0x1 << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API_PAC (0x2 << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_JSCVT_SHIFT 12
+#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
+#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_FCMA_SHIFT 16
+#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
+#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_LRCPC_SHIFT 20
+#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
+#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_BASE (0x1 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_GPA_SHIFT 24
+#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
+#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPI_SHIFT 28
+#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
+#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_SHIFT 32
+#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK)
+#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_SB_SHIFT 36
+#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK)
+#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SPECRES_SHIFT 40
+#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK)
+#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_MASK 0x00000000ffffffffULL
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