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drm/amd/display: Add logging for display MALL refresh setting
author
jsg
<jsg@openbsd.org>
Thu, 20 Jul 2023 08:19:19 +0000
(08:19 +0000)
committer
jsg
<jsg@openbsd.org>
Thu, 20 Jul 2023 08:19:19 +0000
(08:19 +0000)
From Wesley Chalmers
064e33b3591ee43f07776ce64f8a027e8a96f60f
in linux-6.1.y/6.1.39
cd8f067a46d34dee3188da184912ae3d64d98444
in mainline linux
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
patch
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diff --git
a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index
eb6a935
..
11dbe3f
100644
(file)
--- a/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@
-312,6
+312,9
@@
void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, b
/* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit 0 = 1 for enable, = 0 for disable */
uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);
+ smu_print("SMU Set display refresh from mall: enable = %d, cache_timer_delay = %d, cache_timer_scale = %d\n",
+ enable, cache_timer_delay, cache_timer_scale);
+
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL);
}