drm/i915/gt: Fix CCS id's calculation for CCS mode setting

From Andi Shyti
0b01a41e2ce40fda06dd46d9baf8523b95080ac8 in linux-6.6.y/6.6.33
ee01b6a386eaf9984b58a2476e8f531149679da9 in mainline linux

diff --git a/sys/dev/pci/drm/i915/gt/intel_engine_cs.c b/sys/dev/pci/drm/i915/gt/intel_engine_cs.c
index 32506b6..1f1973f 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_engine_cs.c
+++ b/sys/dev/pci/drm/i915/gt/intel_engine_cs.c
@@ -927,6 +927,12 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
        if (IS_DG2(gt->i915)) {
                u8 first_ccs = __ffs(CCS_MASK(gt));
 
+               /*
+                * Store the number of active cslices before
+                * changing the CCS engine configuration
+                */
+               gt->ccs.cslices = CCS_MASK(gt);
+
                /* Mask off all the CCS engine */
                info->engine_mask &= ~GENMASK(CCS3, CCS0);
                /* Put back in the first CCS engine */

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
index 99b71bb..3c62a44 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c
@@ -19,7 +19,7 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
 
        /* Build the value for the fixed CCS load balancing */
        for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
-               if (CCS_MASK(gt) & BIT(cslice))
+               if (gt->ccs.cslices & BIT(cslice))
                        /*
                         * If available, assign the cslice
                         * to the first available engine...

diff --git a/sys/dev/pci/drm/i915/gt/intel_gt_types.h b/sys/dev/pci/drm/i915/gt/intel_gt_types.h
index b7c2b22..7798398 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_gt_types.h
+++ b/sys/dev/pci/drm/i915/gt/intel_gt_types.h
@@ -207,6 +207,14 @@ struct intel_gt {
                                            [MAX_ENGINE_INSTANCE + 1];
        enum intel_submission_method submission_method;
 
+       struct {
+               /*
+                * Mask of the non fused CCS slices
+                * to be used for the load balancing
+                */
+               intel_engine_mask_t cslices;
+       } ccs;
+
        /*
         * Default address space (either GGTT or ppGTT depending on arch).
         *