Changes to io macros were done to handle sparse bus addressing dynamically.
This is a first cut (rough).
--- /dev/null
+/* $OpenBSD: algor.h,v 1.1 1997/03/12 19:16:33 pefo Exp $ */
+
+/*
+ * Copyright (c) 1996 Per Fogelstrom
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef _ALGOR_H_
+#define _ALGOR_H_ 1
+
+/*
+ * P-4032's Physical address space
+ */
+
+#define P4032_PHYS_MIN 0x00000000 /* 256 Meg */
+#define P4032_PHYS_MAX 0x0fffffff
+
+/*
+ * Memory map
+ */
+
+#define P4032_PHYS_MEMORY_START 0x00000000
+#define P4032_PHYS_MEMORY_END 0x0fffffff /* 256 Meg in 2 slots */
+
+/*
+ * I/O map
+ */
+
+#define P4032_V96x 0xbef00000 /* PCI Bus bridge ctrlregs */
+
+#define P4032_CLOCK 0xbff00000 /* RTC clock ptr reg */
+#define P4032_KEYB 0xbff10000 /* PC Keyboard controller */
+#define P4032_LED 0xbff20010 /* 4 Char LED display */
+#define P4032_LCD 0xbff30000 /* LCD option display */
+#define P4032_GPIO 0xbff40000 /* General purpose I/O */
+#define P4032_GPIO_IACK 0xbff50000 /* General purpose I/O Iack */
+#define P4032_FPY 0xbff807c0 /* Floppy controller */
+#define P4032_COM1 0xbff80fe0
+#define P4032_COM2 0xbff80be0
+#define P4032_IMR 0xbff90000 /* Int mask reg (wr) */
+#define P4032_IRR 0xbff90000 /* Int request reg (rd) */
+#define P4032_EIRR 0xbff90004 /* Error int request reg (rd) */
+#define P4032_ICR 0xbff90004 /* Int clear register (wr) */
+#define P4032_PCIIMR 0xbff90008 /* PCI Int mask reg (wr) */
+#define P4032_PCIIRR 0xbff90008 /* PCI Int req reg (rd) */
+#define P4032_IXR0 0xbff9000c /* Int crossbar register 0 */
+#define P4032_IXR1 0xbff90010 /* Int crossbar register 0 */
+#define P4032_IXR2 0xbff90014 /* Int crossbar register 0 */
+
+/*
+ * Interrupt controller interrupt masks
+ */
+
+#define P4032_IM_RTC 0x80 /* RT Clock */
+#define P4032_IM_GPIO 0x40 /* General purpose I/O */
+#define P4032_IM_CENTR 0x20 /* Centronics paralell port */
+#define P4032_IM_COM2 0x10 /* Serial port 2 */
+#define P4032_IM_COM1 0x08 /* Serial port 1 */
+#define P4032_IM_KEYB 0x04 /* PC Keyboard IFC */
+#define P4032_IM_FPY 0x02 /* Floppy disk */
+#define P4032_IM_PCI 0x01 /* PCI controller */
+
+#define P4032_IRR_BER 0x04 /* Bus error */
+#define P4032_IRR_PFAIL 0x02 /* Power fail */
+#define P4032_IRR_DBG 0x01 /* Debug switch */
+
+#define P4032_PCI_IRQ3 0x80 /* PCI interrupt request 3 */
+#define P4032_PCI_IRQ2 0x40 /* PCI interrupt request 2 */
+#define P4032_PCI_IRQ1 0x20 /* PCI interrupt request 1 */
+#define P4032_PCI_IRQ0 0x10 /* PCI interrupt request 0 */
+#define P4032_FPY_DMA 0x08 /* FPY "DMA" interrupt request */
+/*
+ * Interrupt vector descriptor for device on pica bus.
+ */
+struct algor_int_desc {
+ int int_mask; /* Mask used in PICA_SYS_LB_IE */
+ intr_handler_t int_hand; /* Interrupt handler */
+ void *param; /* Parameter to send to handler */
+ int spl_mask; /* Spl mask for interrupt */
+};
+
+int algor_intrnull __P((void *));
+
+#endif /* _ALGOR_H_ */
--- /dev/null
+/* $OpenBSD: algorbus.c,v 1.1 1997/03/12 19:16:35 pefo Exp $ */
+
+/*
+ * Copyright (c) 1996 Per Fogelstrom
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/device.h>
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+#include <machine/intr.h>
+#include <machine/autoconf.h>
+
+#include <arc/arc/arctype.h>
+#include <arc/algor/algor.h>
+
+#include <dev/ic/mc146818reg.h>
+
+struct algor_softc {
+ struct device sc_dv;
+ struct abus sc_bus;
+ struct algor_dev *sc_devs;
+};
+
+/* Definition of the driver for autoconfig. */
+int algormatch(struct device *, void *, void *);
+void algorattach(struct device *, struct device *, void *);
+int algorprint(void *, const char *);
+
+struct cfattach algor_ca = {
+ sizeof(struct algor_softc), algormatch, algorattach
+};
+struct cfdriver algor_cd = {
+ NULL, "algor", DV_DULL, NULL, 0
+};
+
+void algor_intr_establish __P((struct confargs *, int (*)(void *), void *));
+void algor_intr_disestablish __P((struct confargs *));
+caddr_t algor_cvtaddr __P((struct confargs *));
+int algor_matchname __P((struct confargs *, char *));
+int algor_iointr __P((unsigned, struct clockframe *));
+int algor_clkintr __P((unsigned, struct clockframe *));
+int algor_errintr __P((unsigned, struct clockframe *));
+
+extern int cputype;
+
+int p4032_imask = 0;
+int p4032_ixr = 0;
+
+/*
+ * Interrupt dispatch table.
+ */
+static struct algor_int_desc int_table[] = {
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 0 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 1 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 2 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 3 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 4 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 5 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 6 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 7 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 8 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 9 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 10 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 11 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 12 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 13 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 14 */
+ {0, algor_intrnull, (void *)NULL, 0 }, /* 15 */
+};
+#define NUM_INT_SLOTS (sizeof(int_table) / sizeof(struct algor_int_desc))
+
+struct algor_dev {
+ struct confargs ps_ca;
+ u_int8_t ps_mask;
+ u_int8_t ps_ipl;
+ u_int16_t ps_route;
+ intr_handler_t ps_handler;
+ void *ps_base;
+};
+struct algor_dev algor_4032_cpu[] = {
+ {{ "dallas_rtc", 0, 0, },
+ P4032_IM_RTC, IPL_CLOCK, 0xc000, algor_intrnull, (void *)P4032_CLOCK, },
+ {{ "com", 1, 0, },
+ P4032_IM_COM1, IPL_TTY, 0x00c0, algor_intrnull, (void *)P4032_COM1, },
+ {{ "com", 2, 0, },
+ P4032_IM_COM2, IPL_TTY, 0x0300, algor_intrnull, (void *)P4032_COM2, },
+ {{ NULL, -1, NULL, },
+ 0, 0x0000, NULL, (void *)NULL, },
+};
+#define NUM_ALGOR_DEVS (sizeof(algor_4032_cpu) / sizeof(struct algor_dev))
+
+/* IPL routing values */
+static int ipxrtab[] = {
+ 0x000000, /* IPL_BIO */
+ 0x555555, /* IPL_NET */
+ 0xaaaaaa, /* IPL_TTY */
+ 0xffffff, /* IPL_CLOCK */
+};
+
+
+
+struct algor_dev *algor_cpu_devs[] = {
+ NULL, /* Unused */
+ NULL, /* Unused */
+ NULL, /* Unused */
+ NULL, /* Unused */
+ NULL, /* Unused */
+ NULL, /* Unused */
+ algor_4032_cpu, /* 6 = ALGORITHMICS R4032 Board */
+ NULL,
+};
+int nalgor_cpu_devs = sizeof algor_cpu_devs / sizeof algor_cpu_devs[0];
+
+int
+algormatch(parent, cfdata, aux)
+ struct device *parent;
+ void *cfdata;
+ void *aux;
+{
+ struct cfdata *cf = cfdata;
+ struct confargs *ca = aux;
+
+ /* Make sure that we're looking for a ALGORITHMICS BUS */
+ if (strcmp(ca->ca_name, algor_cd.cd_name) != 0)
+ return (0);
+
+ /* Make sure that unit exists. */
+ if (cf->cf_unit != 0 ||
+ cputype > nalgor_cpu_devs || algor_cpu_devs[cputype] == NULL)
+ return (0);
+
+ return (1);
+}
+
+void
+algorattach(parent, self, aux)
+ struct device *parent;
+ struct device *self;
+ void *aux;
+{
+ struct algor_softc *sc = (struct algor_softc *)self;
+ struct confargs *nca;
+ int i;
+
+ printf("\n");
+
+ /* keep our CPU device description handy */
+ sc->sc_devs = algor_cpu_devs[cputype];
+
+ /* set up interrupt handlers */
+ set_intr(INT_MASK_1, algor_iointr, 2);
+ set_intr(INT_MASK_4, algor_errintr, 0);
+
+ sc->sc_bus.ab_dv = (struct device *)sc;
+ sc->sc_bus.ab_type = BUS_ALGOR;
+ sc->sc_bus.ab_intr_establish = algor_intr_establish;
+ sc->sc_bus.ab_intr_disestablish = algor_intr_disestablish;
+ sc->sc_bus.ab_cvtaddr = algor_cvtaddr;
+ sc->sc_bus.ab_matchname = algor_matchname;
+
+ /* Try to configure each ALGOR attached device */
+ for (i = 0; sc->sc_devs[i].ps_ca.ca_slot >= 0; i++) {
+
+ if(sc->sc_devs[i].ps_ca.ca_name == NULL)
+ continue; /* Empty slot */
+
+ nca = &sc->sc_devs[i].ps_ca;
+ nca->ca_bus = &sc->sc_bus;
+
+ /* Tell the autoconfig machinery we've found the hardware. */
+ config_found(self, nca, algorprint);
+ }
+}
+
+int
+algorprint(aux, pnp)
+ void *aux;
+ const char *pnp;
+{
+ struct confargs *ca = aux;
+
+ if (pnp)
+ printf("%s at %s", ca->ca_name, pnp);
+ printf(" slot %ld offset 0x%lx", ca->ca_slot, ca->ca_offset);
+ return (UNCONF);
+}
+
+caddr_t
+algor_cvtaddr(ca)
+ struct confargs *ca;
+{
+ struct algor_softc *sc = algor_cd.cd_devs[0];
+
+ return(sc->sc_devs[ca->ca_slot].ps_base + ca->ca_offset);
+
+}
+
+void
+algor_intr_establish(ca, handler, arg)
+ struct confargs *ca;
+ intr_handler_t handler;
+ void *arg;
+{
+ struct algor_softc *sc = algor_cd.cd_devs[0];
+ int slot = ca->ca_slot;
+ struct algor_dev *dev = &sc->sc_devs[slot];
+ int ipl = dev->ps_ipl;
+
+ if(int_table[slot].int_mask != 0) {
+ panic("algor intr already set");
+ }
+ else {
+ int_table[slot].int_mask = dev->ps_mask;
+ int_table[slot].int_hand = handler;
+ int_table[slot].param = arg;
+ }
+ p4032_ixr |= ipxrtab[ipl] & dev->ps_route;
+ outb(P4032_IXR0, p4032_ixr);
+ outb(P4032_IXR1, p4032_ixr >> 8);
+ outb(P4032_IXR2, p4032_ixr >> 16);
+
+ if(slot == 0) { /* Slot 0 is special, clock */
+ set_intr(INT_MASK_0 << ipl, algor_clkintr, ipl + 1);
+ }
+ else {
+ set_intr(INT_MASK_0 << ipl, algor_iointr, ipl + 1);
+ }
+
+ p4032_imask |= dev->ps_mask;
+ outb(P4032_IMR, p4032_imask);
+ outb(P4032_PCIIMR, p4032_imask >> 8);
+}
+
+void *
+algor_pci_intr_establish(ih, level, handler, arg, name)
+ int level;
+ intr_handler_t handler;
+ void *arg;
+ void *name;
+{
+ int imask;
+ int route;
+ int slot;
+
+ if(level < IPL_BIO || level >= IPL_CLOCK) {
+ panic("pci intr: ipl level out of range");
+ }
+ if(ih < 0 || ih >= 4) {
+ panic("pci intr: irq out of range");
+ }
+
+ imask = (0x1000 << ih);
+ route = (0x30000 << ih+ih);
+
+ slot = NUM_INT_SLOTS;
+ while(slot > 0) {
+ if(int_table[slot].int_mask == 0)
+ break;
+ slot--;
+ }
+ if(slot < 0) {
+ panic("pci intr: out of int slots");
+ }
+
+ int_table[slot].int_mask = imask;
+ int_table[slot].int_hand = handler;
+ int_table[slot].param = arg;
+
+ p4032_ixr |= ipxrtab[level] & route;
+ outb(P4032_IXR0, p4032_ixr);
+ outb(P4032_IXR1, p4032_ixr >> 8);
+ outb(P4032_IXR2, p4032_ixr >> 16);
+
+ set_intr(INT_MASK_0 << level, algor_iointr, level + 1);
+
+ p4032_imask |= imask;
+ outb(P4032_IMR, p4032_imask);
+ outb(P4032_PCIIMR, p4032_imask >> 8);
+
+ return((void *)slot);
+}
+
+void
+algor_intr_disestablish(ca)
+ struct confargs *ca;
+{
+ struct algor_softc *sc = algor_cd.cd_devs[0];
+
+ int slot;
+
+ slot = ca->ca_slot;
+ p4032_imask &= ~int_table[slot].int_mask;
+ outb(P4032_IMR, p4032_imask);
+ outb(P4032_PCIIMR, p4032_imask >> 8);
+
+ if(slot = 0) { /* Slot 0 is special, clock */
+ }
+ else {
+ int_table[slot].int_mask = 0;
+ int_table[slot].int_hand = algor_intrnull;
+ int_table[slot].param = (void *)NULL;
+ }
+}
+
+void
+algor_pci_intr_disestablish(cookie)
+ void *cookie;
+{
+ int slot = (int)cookie;
+
+ p4032_imask &= ~int_table[slot].int_mask;
+ outb(P4032_IMR, p4032_imask);
+ outb(P4032_PCIIMR, p4032_imask >> 8);
+
+ int_table[slot].int_mask = 0;
+ int_table[slot].int_hand = algor_intrnull;
+ int_table[slot].param = (void *)NULL;
+}
+
+int
+algor_matchname(ca, name)
+ struct confargs *ca;
+ char *name;
+{
+ return (strcmp(name, ca->ca_name) == 0);
+}
+
+int
+algor_intrnull(val)
+ void *val;
+{
+ panic("uncaught ALGOR intr for slot %d\n", val);
+}
+
+/*
+ * Handle algor i/o interrupt.
+ */
+int
+algor_iointr(mask, cf)
+ unsigned mask;
+ struct clockframe *cf;
+{
+ int i;
+ int pend;
+
+ pend = inb(P4032_IRR);
+ pend |= inb(P4032_PCIIRR) << 8;
+ pend &= p4032_imask;
+
+ for(i = 0; i < NUM_INT_SLOTS; i++) {
+ if(pend & int_table[i].int_mask)
+ (*int_table[i].int_hand)(int_table[i].param);
+ }
+ return(~0); /* Dont reenable */
+}
+
+/*
+ * Handle algor interval clock interrupt.
+ */
+int
+algor_clkintr(mask, cf)
+ unsigned mask;
+ struct clockframe *cf;
+{
+ int temp;
+
+ /* Ack clock interrupt */
+ outb(P4032_CLOCK, MC_REGC);
+ (void) inb(P4032_CLOCK + 4);
+
+ hardclock(cf);
+
+ /* Re-enable clock interrupts */
+ splx(INT_MASK_0 << IPL_CLOCK | SR_INT_ENAB);
+
+ return(~(INT_MASK_0 << IPL_CLOCK)); /* Keep clock interrupts enabled */
+}
+
+/*
+ * Handle algor interval clock interrupt.
+ */
+int
+algor_errintr(mask, cf)
+ unsigned mask;
+ struct clockframe *cf;
+{
+ int why;
+
+ why = inb(P4032_EIRR);
+
+ if(why & P4032_IRR_BER) {
+ printf("Bus error interrupt\n");
+ outb(P4032_ICR, P4032_IRR_BER);
+ }
+ if(why & P4032_IRR_PFAIL) {
+ printf("Power failure!\n");
+ }
+ if(why & P4032_IRR_DBG) {
+ printf("Debug switch\n");
+ outb(P4032_ICR, P4032_IRR_DBG);
+#ifdef DEBUG
+ mdbpanic();
+#else
+ printf("Not DEBUG compiled, sorry!\n");
+#endif
+ }
+ return(~0);
+}
-/* $OpenBSD: arcbios.c,v 1.4 1996/09/24 19:37:23 pefo Exp $ */
+/* $OpenBSD: arcbios.c,v 1.5 1997/03/12 19:16:36 pefo Exp $ */
/*-
* Copyright (c) 1996 M. Warner Losh. All rights reserved.
*
arc_sid_t *sid;
int i;
+ if(bios_base->magic != ARC_PARAM_BLK_MAGIC) {
+ return(-1); /* This is not an ARC system */
+ }
+
sid = (arc_sid_t *)Bios_GetSystemId();
cf = (arc_config_t *)Bios_GetChild(NULL);
if(cf) {
bios_ident()
{
cputype = get_cpu_type();
+ if(cputype < 0) {
+ return;
+ }
bios_configure_memory();
displayinfo = *(arc_dsp_stat_t *)Bios_GetDisplayStatus(1);
}
-/* $OpenBSD: arctype.h,v 1.3 1996/09/02 11:33:22 pefo Exp $ */
-/*-
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * The Mach Operating System project at Carnegie-Mellon University,
- * Ralph Campbell and Rick Macklem.
- *
+/* $OpenBSD: arctype.h,v 1.4 1997/03/12 19:16:37 pefo Exp $ */
+/*
+ * Copyright (c) 1997 Per Fogelstrom
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * from: @(#)arctype.h 8.1 (Berkeley) 6/10/93
- * $Id: arctype.h,v 1.3 1996/09/02 11:33:22 pefo Exp $
*/
-
/*
* Mother board type byte of "systype" environment variable.
*/
#define MAGNUM 0x2 /* Mips MAGNUM R4000 */
#define DESKSTATION_RPC44 0x3 /* Deskstation xxx */
#define DESKSTATION_TYNE 0x4 /* Deskstation xxx */
+#define NKK_AQUARIUS 0x5 /* NKK R4{67}00 PC */
+#define ALGOR_P4032 0x6 /* ALGORITHMICS P-4032 VR4300 */
-/* $OpenBSD: clock.c,v 1.3 1996/09/19 00:30:34 imp Exp $ */
+/* $OpenBSD: clock.c,v 1.4 1997/03/12 19:16:38 pefo Exp $ */
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* from: Utah Hdr: clock.c 1.18 91/01/21
*
* from: @(#)clock.c 8.1 (Berkeley) 6/10/93
- * $Id: clock.c,v 1.3 1996/09/19 00:30:34 imp Exp $
+ * $Id: clock.c,v 1.4 1997/03/12 19:16:38 pefo Exp $
*/
#include <sys/param.h>
sizeof(struct clock_softc), clockmatch, clockattach
};
+struct cfattach clock_algor_ca = {
+ sizeof(struct clock_softc), clockmatch, clockattach
+};
+
void mcclock_attach __P((struct device *, struct device *, void *));
#define SECMIN ((unsigned)60) /* seconds per minute */
case DESKSTATION_RPC44:
case DESKSTATION_TYNE:
+ case ALGOR_P4032:
break;
default:
switch (cputype) {
case ACER_PICA_61:
+ case ALGOR_P4032:
BUS_INTR_ESTABLISH((struct confargs *)aux,
(intr_handler_t)hardclock, self);
break;
extern int tickadj;
struct clock_softc *csc = (struct clock_softc *)clock_cd.cd_devs[0];
- hz = 100; /* 100 Hz */
- tick = 1000000 / hz; /* number of micro-seconds between interrupts */
- /*
- * Start the clock.
- */
+ /* Assume 100 Hz */
+ hz = 100;
+
+ /* Start the clock. */
(*csc->sc_init)(csc);
+
+ /* Recalculate theese if clock init changed hz */
+ tick = 1000000 / hz; /* number of micro-seconds between interrupts */
+ tickadj = 240000 / (60 * hz); /* can adjust 240ms in 60s */
+
clock_started++;
}
-/* $OpenBSD: clock_mc.c,v 1.4 1996/09/19 00:30:35 imp Exp $ */
+/* $OpenBSD: clock_mc.c,v 1.5 1997/03/12 19:16:39 pefo Exp $ */
/* $NetBSD: clock_mc.c,v 1.2 1995/06/28 04:30:30 cgd Exp $ */
/*
#include <arc/arc/clockvar.h>
#include <arc/arc/arctype.h>
#include <arc/pica/pica.h>
+#include <arc/algor/algor.h>
#include <arc/isa/isa_machdep.h>
#include <arc/isa/timerreg.h>
struct device *self, void *aux));
static void mcclock_init_pica __P((struct clock_softc *csc));
static void mcclock_init_tyne __P((struct clock_softc *csc));
+static void mcclock_init_p4032 __P((struct clock_softc *csc));
static void mcclock_get __P((struct clock_softc *csc, time_t base,
struct tod_time *ct));
static void mcclock_set __P((struct clock_softc *csc,
static u_int mc_read_tyne __P((struct clock_softc *csc, u_int reg));
static struct mcclockdata mcclockdata_tyne = { mc_write_tyne, mc_read_tyne };
+/* Algorithmics P4032 clock read code */
+static void mc_write_p4032 __P((struct clock_softc *csc, u_int reg,
+ u_int datum));
+static u_int mc_read_p4032 __P((struct clock_softc *csc, u_int reg));
+static struct mcclockdata mcclockdata_p4032 = { mc_write_p4032, mc_read_p4032 };
+
void
mcclock_attach(parent, self, aux)
struct device *parent;
csc->sc_init = mcclock_init_pica;
csc->sc_data = &mcclockdata_pica;
mcclockdata_tyne.mc_addr = BUS_CVTADDR(ca);
+ mc146818_write(csc, MC_REGB, MC_REGB_BINARY | MC_REGB_24HR);
break;
case DESKSTATION_RPC44:
case DESKSTATION_TYNE:
csc->sc_init = mcclock_init_tyne;
csc->sc_data = &mcclockdata_tyne;
+ mc146818_write(csc, MC_REGB, MC_REGB_BINARY | MC_REGB_24HR);
+ break;
+
+ case ALGOR_P4032:
+ csc->sc_init = mcclock_init_p4032;
+ csc->sc_data = &mcclockdata_p4032;
+ mc146818_write(csc, MC_REGB, MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_SQWE);
break;
default:
printf("\n");
panic("don't know how to set up for other system types.");
}
-
- /* Turn interrupts off, just in case. */
- mc146818_write(csc, MC_REGB, MC_REGB_BINARY | MC_REGB_24HR);
}
static void
isa_outb(TIMER_CNTR0, TIMER_DIV(hz) / 256);
}
+static void
+mcclock_init_p4032(csc)
+ struct clock_softc *csc;
+{
+ int s;
+ char cv;
+
+ hz = 256; /* NOTE! We are going at 256 Hz! */
+ s = splclock();
+ cv = mc146818_read(csc, MC_REGA) & ~MC_REGA_RSMASK;
+ mc146818_write(csc, MC_REGA, cv | MC_RATE_256_Hz);
+ cv = mc146818_read(csc, MC_REGB);
+ mc146818_write(csc, MC_REGB, cv | MC_REGB_PIE);
+ splx(s);
+}
+
/*
* Get the time of day, based on the clock's value and/or the base value.
*/
ct->day = regs[MC_DOM];
ct->mon = regs[MC_MONTH];
ct->year = regs[MC_YEAR];
+ if(cputype == ALGOR_P4032)
+ ct->year -= 80;
}
/*
regs[MC_DOW] = ct->dow;
regs[MC_DOM] = ct->day;
regs[MC_MONTH] = ct->mon;
- regs[MC_YEAR] = ct->year;
+ if(cputype == ALGOR_P4032)
+ regs[MC_YEAR] = ct->year + 80;
+ else
+ regs[MC_YEAR] = ct->year;
MC146818_PUTTOD(csc, ®s);
splx(s);
i = isa_inb(IO_RTC+1);
return(i);
}
+
+static void
+mc_write_p4032(csc, reg, datum)
+ struct clock_softc *csc;
+ u_int reg, datum;
+{
+ outb(P4032_CLOCK, reg);
+ outb(P4032_CLOCK+4, datum);
+}
+
+static u_int
+mc_read_p4032(csc, reg)
+ struct clock_softc *csc;
+ u_int reg;
+{
+ int i;
+
+ outb(P4032_CLOCK, reg);
+ i = inb(P4032_CLOCK+4) & 0xff;
+ return(i);
+}
-/* $OpenBSD: conf.c,v 1.11 1996/11/28 23:35:38 niklas Exp $ */
+/* $OpenBSD: conf.c,v 1.12 1997/03/12 19:16:40 pefo Exp $ */
/*
* Copyright (c) 1992, 1993
* SUCH DAMAGE.
*
* from: @(#)conf.c 8.2 (Berkeley) 11/14/93
- * $Id: conf.c,v 1.11 1996/11/28 23:35:38 niklas Exp $
+ * $Id: conf.c,v 1.12 1997/03/12 19:16:40 pefo Exp $
*/
#include <sys/param.h>
#if NPC + NVT > 0
cons_init(pc),
#endif
-#if NACE > 0
+#if NCOM > 0
cons_init(com),
#endif
{ 0 },
-/* $OpenBSD: cpu.c,v 1.4 1996/11/23 21:45:27 kstailey Exp $ */
+/* $OpenBSD: cpu.c,v 1.5 1997/03/12 19:16:41 pefo Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
printf("MIPS R10000 CPU");
break;
case MIPS_R4200:
- printf("MIPS R4200 CPU (ICE)");
+ printf("NEC VR4200 CPU (ICE)");
+ break;
+ case MIPS_R4300:
+ printf("NEC VR4300 CPU");
break;
case MIPS_R8000:
printf("MIPS R8000 Blackbird/TFP CPU");
case MIPS_R4600:
printf("QED R4600 Orion CPU");
break;
- case MIPS_R3SONY:
- printf("Sony R3000 based CPU");
+ case MIPS_R4700:
+ printf("QED R4700 Orion CPU");
break;
case MIPS_R3TOSH:
printf("Toshiba R3000 based CPU");
case MIPS_R3NKK:
printf("NKK R3000 based CPU");
break;
- case MIPS_UNKC1:
case MIPS_UNKC2:
default:
printf("Unknown CPU type (0x%x)",cpu_id.cpu.cp_imp);
printf("MIPS R10000 FPU");
break;
case MIPS_R4210:
- printf("MIPS R4200 FPC (ICE)");
+ printf("NEC VR4200 FPC (ICE)");
+ break;
case MIPS_R8000:
printf("MIPS R8000 Blackbird/TFP");
break;
case MIPS_R4600:
printf("QED R4600 Orion FPC");
break;
- case MIPS_R3SONY:
- printf("Sony R3000 based FPC");
+ case MIPS_R4700:
+ printf("QED R4700 Orion FPC");
break;
case MIPS_R3TOSH:
printf("Toshiba R3000 based FPC");
-/* $OpenBSD: locore.S,v 1.8 1997/02/15 17:40:21 mickey Exp $ */
+/* $OpenBSD: locore.S,v 1.9 1997/03/12 19:16:42 pefo Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
* v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
*
* from: @(#)locore.s 8.5 (Berkeley) 1/4/94
- * $Id: locore.S,v 1.8 1997/02/15 17:40:21 mickey Exp $
+ * $Id: locore.S,v 1.9 1997/03/12 19:16:42 pefo Exp $
*/
/*
*
* Flush the "random" entries from the TLB.
* Uses "wired" register to determine what register to start with.
+ * Arg "tlbsize" is the number of entries to flush.
*
- * R4K_TLBFlush()
+ * R4K_TLBFlush(tlbsize)
*
* Results:
* None.
mfc0 v1, COP_0_STATUS_REG # Save the status register.
mtc0 zero, COP_0_STATUS_REG # Disable interrupts
mfc0 t1, COP_0_TLB_WIRED
- li t2, VMNUM_TLB_ENTRIES
li v0, CACHED_MEMORY_ADDR # invalid address
dmfc0 t0, COP_0_TLB_HI # Save the PID
dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry1.
mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry.
/*
- * Align the starting value (t1) and the upper bound (t2).
+ * Align the starting value (t1) and the upper bound (a0).
*/
1:
mtc0 t1, COP_0_TLB_INDEX # Set the index register.
tlbwi # Write the TLB entry.
nop
nop
- bne t1, t2, 1b
+ bne t1, a0, 1b
nop
dmtc0 t0, COP_0_TLB_HI # Restore the PID
and t1, 3
li t2, 4096
sllv t2, t2, t1
- sw t2, CpuPrimaryDataCacheSize
+ sw t2, CpuPrimaryInstCacheSize
addiu t2, -1
and t2, ~(NBPG - 1)
sw t2, CpuCacheAliasMask
and t2, v0, 0x20
srl t2, t2, 1
addu t2, t2, 16
- sw t2, CpuPrimaryDataCacheLSize
+ sw t2, CpuPrimaryInstCacheLSize
- srl t1, v0, 6 # Get I cache size.
+ srl t1, v0, 6 # Get D cache size.
and t1, 3
li t2, 4096
sllv t2, t2, t1
- sw t2, CpuPrimaryInstCacheSize
+ sw t2, CpuPrimaryDataCacheSize
and t2, v0, 0x10
addu t2, t2, 16
- sw t2, CpuPrimaryInstCacheLSize
+ sw t2, CpuPrimaryDataCacheLSize
and v1, 0xff00
li t1, (MIPS_R4600 << 8)
li t2, 1
-/* $OpenBSD: machdep.c,v 1.20 1997/02/03 15:05:08 deraadt Exp $ */
+/* $OpenBSD: machdep.c,v 1.21 1997/03/12 19:16:43 pefo Exp $ */
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* SUCH DAMAGE.
*
* from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
- * $Id: machdep.c,v 1.20 1997/02/03 15:05:08 deraadt Exp $
+ * $Id: machdep.c,v 1.21 1997/03/12 19:16:43 pefo Exp $
*/
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
#include <machine/pio.h>
#include <machine/psl.h>
#include <machine/pte.h>
+#include <machine/bus.h>
#include <machine/autoconf.h>
#include <machine/memconf.h>
#include <arc/arc/arcbios.h>
#include <arc/pica/pica.h>
#include <arc/dti/desktech.h>
+#include <arc/algor/algor.h>
#include <asc.h>
#endif
extern struct consdev *cn_tab;
+extern char kernel_start[];
/* the following is used externally (sysctl_hw) */
char machine[] = "arc"; /* cpu "architecture" */
int physmem; /* max supported memory, changes to actual */
int cpucfg; /* Value of processor config register */
int cputype; /* Mother board type */
+int num_tlbentries = 48; /* Size of the CPU tlb */
int ncpu = 1; /* At least one cpu in the system */
-int isa_io_base; /* Base address of ISA io port space */
-int isa_mem_base; /* Base address of ISA memory space */
+int CONADDR; /* Well, ain't it just plain stupid... */
+struct arc_bus_space arc_bus;
struct mem_descriptor mem_layout[MAXMEMSEGS];
* entries as possible to do something useful :-).
*/
+ arc_bus.isa_io_sparse1 = 0;
+ arc_bus.isa_io_sparse2 = 0;
+ arc_bus.isa_io_sparse4 = 0;
+ arc_bus.isa_io_sparse8 = 0;
switch (cputype) {
case ACER_PICA_61: /* ALI PICA 61 and MAGNUM is almost the */
case MAGNUM: /* Same kind of hardware. NEC goes here too */
else {
strcpy(cpu_model, "Acer Pica-61");
}
- isa_io_base = PICA_V_ISA_IO;
- isa_mem_base = PICA_V_ISA_MEM;
+ arc_bus.isa_io_base = PICA_V_ISA_IO;
+ arc_bus.isa_mem_base = PICA_V_ISA_MEM;
+ CONADDR = PICA_SYS_COM1;
/*
* Set up interrupt handling and I/O addresses.
case DESKSTATION_RPC44:
strcpy(cpu_model, "Deskstation rPC44");
- isa_io_base = 0xb0000000; /*XXX*/
- isa_mem_base = 0xa0000000; /*XXX*/
+ arc_bus.isa_io_base = 0xb0000000; /*XXX*/
+ arc_bus.isa_mem_base = 0xa0000000; /*XXX*/
+ CONADDR = 0xa0000000+0x3f8; /* Standard PC Com0 address */
break;
case DESKSTATION_TYNE:
strcpy(cpu_model, "Deskstation Tyne");
- isa_io_base = TYNE_V_ISA_IO;
- isa_mem_base = TYNE_V_ISA_MEM;
+ arc_bus.isa_io_base = TYNE_V_ISA_IO;
+ arc_bus.isa_mem_base = TYNE_V_ISA_MEM;
+ CONADDR = TYNE_V_ISA_MEM+0x3f8; /* Standard PC Com0 address */
+ break;
+
+ case -1: /* Not identified as an ARC system. We have a couple */
+ /* of other options. Systems not having an ARC Bios */
+
+ /* Make this more fancy when more comes in here */
+ cputype = ALGOR_P4032;
+ strcpy(cpu_model, "Algorithmics P-4032");
+ arc_bus.isa_io_base = 0;
+ arc_bus.isa_io_sparse1 = 2;
+ arc_bus.isa_io_sparse2 = 1;
+ arc_bus.isa_io_sparse4 = 0;
+ arc_bus.isa_io_sparse8 = 0;
+ arc_bus.isa_mem_base = 0;
+ CONADDR = P4032_COM1;
+ num_tlbentries = 32;
+
+ mem_layout[0].mem_start = 0;
+ mem_layout[0].mem_size = mips_trunc_page(CACHED_TO_PHYS(kernel_start));
+ mem_layout[1].mem_start = CACHED_TO_PHYS((int)sysend);
+ mem_layout[1].mem_size = 0x800000 - (int)(CACHED_TO_PHYS(sysend));
+ physmem = 8192 * 1024;
+#if 0
+ mem_layout[2].mem_start = 0x800000;
+ mem_layout[2].mem_size = 0x1000000;
+ physmem += 8192 * 1024;
+#endif
+
break;
default:
* Start with cleaning out the TLB. Bye bye Microsoft....
*/
R4K_SetWIRED(0);
- R4K_TLBFlush();
+ R4K_TLBFlush(num_tlbentries);
R4K_SetWIRED(VMWIRED_ENTRIES);
switch (cputype) {
case DESKSTATION_RPC44:
break;
+
+ case ALGOR_P4032:
+ break;
}
/*
* Clear allocated memory.
*/
bzero(start, sysend - start);
+consinit();
+mdbpanic();
/*
* Initialize the virtual memory system.
-/* $OpenBSD: mainbus.c,v 1.4 1996/11/23 21:45:28 kstailey Exp $ */
-/* $NetBSD: mainbus.c,v 1.3 1995/06/28 02:45:10 cgd Exp $ */
+/* $OpenBSD: mainbus.c,v 1.5 1997/03/12 19:16:44 pefo Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
nca.ca_bus = &sc->sc_bus;
config_found(self, &nca, mbprint);
}
- /* XXX I think all ARC machines have this, no? XXX */
+ else if (cputype == ALGOR_P4032) {
+ /* we have an ALGOR bus! :-) */
+ nca.ca_name = "algor";
+ nca.ca_slot = 0;
+ nca.ca_offset = 0;
+ nca.ca_bus = &sc->sc_bus;
+ config_found(self, &nca, mbprint);
+ }
+
+ /* The following machines have a PCI bus */
+ if (cputype == ALGOR_P4032) {
+ nca.ca_name = "pbcpcibr";
+ nca.ca_slot = 0;
+ nca.ca_offset = 0;
+ nca.ca_bus = &sc->sc_bus;
+ config_found(self, &nca, mbprint);
+ }
+
+ /* The following machines have an ISA bus */
if (cputype == ACER_PICA_61 ||
cputype == DESKSTATION_TYNE ||
- cputype == DESKSTATION_RPC44) {
- /* we have an ISA bus! */
+ cputype == DESKSTATION_RPC44) {
nca.ca_name = "isabr";
nca.ca_slot = 0;
nca.ca_offset = 0;
-/* $OpenBSD: minidebug.c,v 1.3 1996/10/21 05:37:12 imp Exp $ */
+/* $OpenBSD: minidebug.c,v 1.4 1997/03/12 19:16:45 pefo Exp $ */
/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
* SUCH DAMAGE.
*
* from: @(#)kadb.c 8.1 (Berkeley) 6/10/93
- * $Id: minidebug.c,v 1.3 1996/10/21 05:37:12 imp Exp $
+ * $Id: minidebug.c,v 1.4 1997/03/12 19:16:45 pefo Exp $
*/
/*
u_int c;
*val = 0;
- while((c = cngetc()) != '\e' && c != '\n') {
+ while((c = cngetc()) != '\e' && c != '\n' && c != '\r') {
if(c >= '0' && c <= '9') {
*val = (*val << 4) + c - '0';
cnputc(c);
cnputc(c);
}
}
+ if(c == '\r')
+ c = '\n';
return(c);
}
-/* $OpenBSD: pmap.c,v 1.7 1997/01/22 22:23:19 pefo Exp $ */
+/* $OpenBSD: pmap.c,v 1.8 1997/03/12 19:16:46 pefo Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
* SUCH DAMAGE.
*
* from: @(#)pmap.c 8.4 (Berkeley) 1/26/94
- * $Id: pmap.c,v 1.7 1997/01/22 22:23:19 pefo Exp $
+ * $Id: pmap.c,v 1.8 1997/03/12 19:16:46 pefo Exp $
*/
/*
extern vm_page_t vm_page_alloc1 __P((void));
extern void vm_page_free1 __P((vm_page_t));
+extern int num_tlbentries;
/*
* For each vm_page_t, there is a list of all currently valid virtual
#define PDB_WIRING 0x4000
#define PDB_PVDUMP 0x8000
-extern int _ftext[];
+extern int kernel_start[];
extern int _end[];
int pmapdebug = 0x0;
mem_layout[i].mem_start = 0x20000; /* Adjust to be above vec's */
}
/* Adjust for the kernel expansion area (bufs etc) */
- if((mem_layout[i].mem_start + mem_layout[i].mem_size > CACHED_TO_PHYS(_ftext)) &&
+ if((mem_layout[i].mem_start + mem_layout[i].mem_size > CACHED_TO_PHYS(kernel_start)) &&
(mem_layout[i].mem_start < CACHED_TO_PHYS(avail_start))) {
mem_layout[i].mem_size -= CACHED_TO_PHYS(avail_start) - mem_layout[i].mem_start;
mem_layout[i].mem_start = CACHED_TO_PHYS(avail_start);
nextpage += (pseg->end - pseg->start) / NBPG;
avail_remaining += (pseg->end - pseg->start) / NBPG;
#if 0
-/*XXX*/ sprintf(pbuf,"segment = %d start 0x%x end 0x%x avail %d page %d\n", i, pseg->start, pseg->end, avail_remaining, nextpage); bios_putstring(pbuf);
+/*XXX*/ sprintf(pbuf,"segment = %d start 0x%x end 0x%x avail %d page %d\n", i, pseg->start, pseg->end, avail_remaining, nextpage); printf(pbuf);
#endif
pseg++;
}
if (pmap->pm_tlbgen != tlbpid_gen) {
id = tlbpid_cnt;
if (id == VMNUM_PIDS) {
- R4K_TLBFlush();
+ R4K_TLBFlush(num_tlbentries);
/* reserve tlbpid_gen == 0 to alway mean invalid */
if (++tlbpid_gen == 0)
tlbpid_gen = 1;
-/* $OpenBSD: trap.c,v 1.9 1997/02/04 17:26:14 deraadt Exp $ */
+/* $OpenBSD: trap.c,v 1.10 1997/03/12 19:16:47 pefo Exp $ */
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* from: Utah Hdr: trap.c 1.32 91/04/06
*
* from: @(#)trap.c 8.5 (Berkeley) 1/11/94
- * $Id: trap.c,v 1.9 1997/02/04 17:26:14 deraadt Exp $
+ * $Id: trap.c,v 1.10 1997/03/12 19:16:47 pefo Exp $
*/
#include <sys/param.h>
trp = trapdebug;
#endif
- cnt.v_trap++;
type = (causeReg & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT;
if (USERMODE(statusReg)) {
type |= T_USER;
register int i;
struct clockframe cf;
+ cnt.v_trap++;
#ifdef DEBUG
trp->status = statusReg;
trp->cause = causeReg;
if(prio > 5)
panic("set_intr: to high priority");
- if(cpu_int_tab[prio].int_mask != 0)
+ if(cpu_int_tab[prio].int_mask != 0 &&
+ (cpu_int_tab[prio].int_mask != mask ||
+ cpu_int_tab[prio].int_hand != int_hand))
panic("set_intr: int already set");
cpu_int_tab[prio].int_hand = int_hand;
break;
case DESKSTATION_RPC44:
break;
+ case ALGOR_P4032:
+ break;
}
}
-# $OpenBSD: GENERIC,v 1.11 1996/11/28 23:35:39 niklas Exp $
+# $OpenBSD: GENERIC,v 1.12 1997/03/12 19:16:48 pefo Exp $
#
# Generic configuration file for MIPS R4x00 ARC Systems
#
mainbus0 at root
cpu* at mainbus0
-pica* at mainbus0
-isabr* at mainbus0
+#### Main local buses
+
+pica* at mainbus0 # ACER Pica systems local bus.
+algor* at mainbus0 # Algorithmics local bus.
+isabr* at mainbus0 # ISA Bus bridge (std ISA bus).
+pbcpcibr* at mainbus0 # PCI Bus bridge.
+
+#### PICA bus devices
clock0 at pica?
pc0 at pica?
asc0 at pica?
scsibus* at asc?
-#
-# ISA Bus.
-#
+#### Algor bus devices
+
+clock0 at algor?
+com0 at algor?
+com1 at algor?
+
+#### PCI Bus
+
+pci* at pbcpcibr?
-isa* at isabr?
+ncr* at pci? dev ? function ?
+scsibus* at ncr?
+de* at pci? dev ? function ?
-clock0 at isa? port 0x70 irq 0
+#### ISA Bus.
-pc0 at isa? port 0x60 irq 1 # generic PC console device
-com0 at isa? port 0x3f8 irq 4
-com1 at isa? port 0x2f8 irq 3
-com2 at isa? port 0x3e8 irq 4
-com3 at isa? port 0x2e8 irq 3
+isa* at isabr?
-wdc0 at isa? port 0x1f0 irq 14 # ST506, ESDI, and IDE controllers
-#wdc1 at isa? port 0x170 irq 15
-wd* at wdc? drive ?
+clock0 at isa? port 0x70 irq 0
-atapibus* at wdc?
-acd* at atapibus? drive?
+pc0 at isa? port 0x60 irq 1 # generic PC console device
+com0 at isa? port 0x3f8 irq 4
+com1 at isa? port 0x2f8 irq 3
+com2 at isa? port 0x3e8 irq 4
+com3 at isa? port 0x2e8 irq 3
-lpt0 at isa? port 0x378 irq 7
-ep0 at isa? port ? irq ? # 3C509 ethernet cards
-ed0 at isa? port 0x280 iomem 0xd0000 irq 9 # WD/SMC, 3C503, and NE[12]000
-ed1 at isa? port 0x250 iomem 0xd8000 irq 9 # ethernet cards
-ed2 at isa? port 0x300 iomem 0xcc000 irq 10 #
+wdc0 at isa? port 0x1f0 irq 14 # ST506, ESDI, IDE controllers
+#wdc1 at isa? port 0x170 irq 15
+wd* at wdc? drive ?
+
+atapibus* at wdc?
+acd* at atapibus? drive?
+
+lpt0 at isa? port 0x378 irq 7
+ep0 at isa? port ? irq ? # 3C509 ethernet cards
+ed0 at isa? port 0x280 iomem 0xd0000 irq 9 # WD/SMC, 3C503, NE[12]000
+ed1 at isa? port 0x250 iomem 0xd8000 irq 9 # ethernet cards
+ed2 at isa? port 0x300 iomem 0xcc000 irq 10 #
btl0 at isa? port 0x330 irq ? drq ?
scsibus* at btl?
-#
-# SCSI Bus devices
-#
+#### SCSI Bus devices
sd* at scsibus? target ? lun ?
st* at scsibus? target ? lun ?
ss* at scsibus? target ? lun ?
uk* at scsibus? target ? lun ?
-#
+#### PSEUDO Devices
+
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 8 # packet filter ports
pseudo-device sl 2 # serial-line IP ports
-# $OpenBSD: files.arc,v 1.11 1996/12/11 12:59:29 niklas Exp $
+# $OpenBSD: files.arc,v 1.12 1997/03/12 19:16:49 pefo Exp $
#
# maxpartitions must be first item in files.${ARCH}
#
# PICA bus autoconfiguration devices
#
device pica {}
-attach pica at mainbus #
+attach pica at mainbus # optional
file arch/arc/pica/picabus.c pica
+#
+# ALGOR bus autoconfiguration devices
+#
+device algor {}
+attach algor at mainbus # optional
+file arch/arc/algor/algorbus.c algor
+
#
# ISA Bus bridge
#
device isabr {} : isabus
-attach isabr at mainbus
+attach isabr at mainbus # optional
file arch/arc/isa/isabus.c isabr
-# Ethernet chip
+#
+# PCI Bus bridge
+#
+device pbcpcibr {} : pcibus
+attach pbcpcibr at mainbus # optional
+file arch/arc/pci/pbcpcibus.c pbcpcibr
+
+# Ethernet chip on PICA bus
device sn
attach sn at pica: ifnet, ether
file arch/arc/dev/if_sn.c sn needs-count
major {sd = 0}
major {cd = 3}
-# Machine dependent SCSI interface driver
+# Symbios 53C94 SCSI interface driver on PICA bus
device asc: scsi
attach asc at pica
file arch/arc/dev/asc.c asc needs-count
-# Floppy disk controller
+# Floppy disk controller on PICA bus
device fdc {drive = -1}
attach fdc at pica
device fd: disk
# Stock ISA bus support
#
define pcmcia {} # XXX dummy decl...
-define pci {} # XXX dummy decl...
+include "../../../dev/pci/files.pci"
include "../../../dev/isa/files.isa"
major { wd = 4 }
device clock
attach clock at pica with clock_pica
attach clock at isa with clock_isa
-file arch/arc/arc/clock.c clock & (clock_isa | clock_pica) needs-flag
+attach clock at algor with clock_algor
+file arch/arc/arc/clock.c clock & (clock_isa | clock_pica | clock_algor) needs-flag
file arch/arc/arc/clock_mc.c clock & (clock_isa | clock_pica) needs-flag
# Console driver on PC-style graphics
# 8250/16[45]50-based "com" ports
attach com at pica with com_pica
+attach com at algor with com_algor
file arch/arc/pica/com_pica.c com_pica
+
# National Semiconductor DS8390/WD83C690-based boards
# (WD/SMC 80x3 family, SMC Ultra [8216], 3Com 3C503, NE[12]000, and clones)
# XXX conflicts with other ports; can't be in files.isa
#
+#
+# PCI Bus support
+#
+
+#
+# Common files
+#
+
file dev/cons.c
file dev/cninit.c
file netinet/in_cksum.c
-/* $OpenBSD: if_sn.c,v 1.7 1996/10/19 10:02:51 niklas Exp $ */
+/* $OpenBSD: if_sn.c,v 1.8 1997/03/12 19:16:50 pefo Exp $ */
/*
* National Semiconductor SONIC Driver
* Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
#define sonicdataaddr(eh, off, type) ((type)(((caddr_t)((eh)+1)+(off))))
/*
- * munge the recieved packet into an mbuf chain
- * because we are using stupif buffer management this
+ * munge the received packet into a mbuf chain
+ * because we are using stupid buffer management this
* is slow.
*/
struct mbuf *
-/* $OpenBSD: pccons.c,v 1.11 1997/01/17 23:13:57 pefo Exp $ */
+/* $OpenBSD: pccons.c,v 1.12 1997/03/12 19:16:52 pefo Exp $ */
/* $NetBSD: pccons.c,v 1.89 1995/05/04 19:35:20 cgd Exp $ */
/*-
#include <machine/cpu.h>
#include <machine/pio.h>
+#include <machine/bus.h>
#include <machine/autoconf.h>
#include <machine/display.h>
#include <machine/pccons.h>
/* initialize required fields */
cp->cn_dev = makedev(maj, 0);
- cp->cn_pri = CN_INTERNAL;
+ if(cputype == ALGOR_P4032) {
+ cp->cn_pri = CN_DEAD; /* XXX For now... */
+ }
+ else {
+ cp->cn_pri = CN_INTERNAL;
+ }
}
/* ARGSUSED */
break;
case DESKSTATION_RPC44:
- mono_base += isa_io_base;
- mono_buf += isa_mem_base;
- cga_base += isa_io_base;
- cga_buf = isa_mem_base + 0xa0000;
- kbd_cmdp = isa_io_base + 0x64;
- kbd_datap = isa_io_base + 0x60;
+ mono_base += arc_bus.isa_io_base;
+ mono_buf += arc_bus.isa_mem_base;
+ cga_base += arc_bus.isa_io_base;
+ cga_buf = arc_bus.isa_mem_base + 0xa0000;
+ kbd_cmdp = arc_bus.isa_io_base + 0x64;
+ kbd_datap = arc_bus.isa_io_base + 0x60;
kbc_put8042cmd(CMDBYTE); /* Want XT codes.. */
break;
}
-/* $OpenBSD: autoconf.h,v 1.1.1.1 1996/06/24 09:07:17 pefo Exp $ */
+/* $OpenBSD: autoconf.h,v 1.2 1997/03/12 19:16:54 pefo Exp $ */
/* $NetBSD: autoconf.h,v 1.1 1995/02/13 23:07:31 cgd Exp $ */
/*
#define BUS_MAIN 1 /* mainbus */
#define BUS_PICA 2 /* PICA Bus */
#define BUS_ISABR 3 /* ISA Bridge Bus */
+#define BUS_ALGOR 4 /* Algorithmics local bus */
+#define BUS_PCIBR 5 /* Algorithmics PCI bridge */
#define BUS_INTR_ESTABLISH(ca, handler, val) \
(*(ca)->ca_bus->ab_intr_establish)((ca), (handler), (val))
-/* $OpenBSD: bus.h,v 1.9 1997/01/10 23:41:25 pefo Exp $ */
+/* $OpenBSD: bus.h,v 1.10 1997/03/12 19:16:55 pefo Exp $ */
/*
+ * Copyright (c) 1997 Per Fogelstrom. All rights reserved.
* Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#define CAT3(a,b,c) a/**/b/**/c
#endif
+#define HIT_FLUSH_DCACHE(addr, len) R4K_HitFlushDCache(addr, len)
+
/*
* Bus access types.
*/
typedef u_int32_t bus_addr_t;
typedef u_int32_t bus_size_t;
typedef u_int32_t bus_space_handle_t;
-typedef u_int32_t bus_space_tag_t;
+typedef struct arc_bus_space *bus_space_tag_t;
+
+struct arc_bus_space {
+ u_int32_t isa_io_base;
+ u_int32_t isa_mem_base;
+ u_int8_t isa_io_sparse1; /* Sparse addressing shift count */
+ u_int8_t isa_io_sparse2; /* Sparse addressing shift count */
+ u_int8_t isa_io_sparse4; /* Sparse addressing shift count */
+ u_int8_t isa_io_sparse8; /* Sparse addressing shift count */
+};
+
+extern struct arc_bus_space arc_bus;
/*
* Access methods for bus resources
*/
-#define bus_space_map(t, addr, size, cacheable, bshp) \
- ((*(bshp) = (t) + (addr)), 0)
+#define bus_space_map(t, addr, size, cacheable, bshp) \
+ ((*(bshp) = (t)->isa_io_base + (addr)), 0)
+
#define bus_space_unmap(t, bsh, size)
#define bus_space_read(n,m) \
CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba) \
{ \
- return *(volatile CAT3(u_int,m,_t) *)(bsh + ba); \
+ return *(volatile CAT3(u_int,m,_t) *)(bsh + ((ba) << CAT(bst->isa_io_sparse,n))); \
}
bus_space_read(1,8)
CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, CAT3(u_int,m,_t) x) \
{ \
- *(volatile CAT3(u_int,m,_t) *)(bsh + ba) = x; \
+ *(volatile CAT3(u_int,m,_t) *)(bsh + ((ba) << CAT(bst->isa_io_sparse,n))) = x; \
}
bus_space_write(1,8)
-/* $OpenBSD: cpu.h,v 1.4 1996/09/14 15:58:25 pefo Exp $ */
+/* $OpenBSD: cpu.h,v 1.5 1997/03/12 19:16:56 pefo Exp $ */
/*-
* Copyright (c) 1992, 1993
/*
* The number of TLB entries and the first one that write random hits.
*/
-#define VMNUM_TLB_ENTRIES 48
+/*#define VMNUM_TLB_ENTRIES 48 XXX We never use this... */
#define VMWIRED_ENTRIES 8
/*
#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
-#define MIPS_UNKC1 0x0b /* unnanounced product cpu ISA III */
+#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
-#define MIPS_R3SONY 0x21 /* Sony R3000 based CPU ISA I */
+#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
#define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */
-/* $OpenBSD: isa_machdep.h,v 1.2 1996/09/14 15:58:26 pefo Exp $ */
+/* $OpenBSD: isa_machdep.h,v 1.3 1997/03/12 19:16:58 pefo Exp $ */
/*
* Copyright (c) 1996 Per Fogelstrom
* However, the cpu executes an instruction every 7.5ns
* so the bus is much slower so it doesn't matter, really.
*/
-#define isa_outb(x,y) outb(isa_io_base + (x), y)
-#define isa_inb(x) inb(isa_io_base + (x))
+#define isa_outb(x,y) outb(arc_bus.isa_io_base + (x), y)
+#define isa_inb(x) inb(arc_bus.isa_io_base + (x))
-extern int isa_io_base; /* Base address for ISA I/O space */
-extern int isa_mem_base; /* Base address for ISA MEM space */
-
struct arc_isa_bus {
void *ic_data;
-/* $OpenBSD: isabus.c,v 1.7 1996/11/28 23:35:44 niklas Exp $ */
+/* $OpenBSD: isabus.c,v 1.8 1997/03/12 19:16:59 pefo Exp $ */
/* $NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp $ */
/*-
sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish;
iba.iba_busname = "isa";
- iba.iba_iot = (bus_space_tag_t)isa_io_base;
- iba.iba_memt = (bus_space_tag_t)isa_mem_base;
+ iba.iba_iot = (bus_space_tag_t)&arc_bus;
+ iba.iba_memt = (bus_space_tag_t)&arc_bus;
iba.iba_ic = &sc->arc_isa_cs;
config_found(self, &iba, isabrprint);
}
if (pnp)
printf("%s at %s", ca->ca_name, pnp);
- printf(" isa_io_base 0x%lx isa_mem_base 0x%lx", isa_io_base,
- isa_mem_base);
+ printf(" isa_io_base 0x%lx isa_mem_base 0x%lx",
+ arc_bus.isa_io_base, arc_bus.isa_mem_base);
return (UNCONF);
}
--- /dev/null
+/* $OpenBSD: pbcpcibus.c,v 1.1 1997/03/12 19:17:00 pefo Exp $ */
+
+/*
+ * Copyright (c) 1997 Per Fogelstrom
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*
+ * ARC PCI BUS Bridge driver.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+#include <sys/proc.h>
+#include <vm/vm.h>
+
+#include <machine/autoconf.h>
+#include <machine/cpu.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <arc/arc/arctype.h>
+#include <arc/algor/algor.h>
+#include <arc/pci/pcibrvar.h>
+#include <arc/pci/v962pcbreg.h>
+
+extern vm_map_t phys_map;
+extern int cputype;
+
+int pbcpcibrmatch __P((struct device *, void *, void *));
+void pbcpcibrattach __P((struct device *, struct device *, void *));
+
+void pbc_attach_hook __P((struct device *, struct device *,
+ struct pcibus_attach_args *));
+int pbc_bus_maxdevs __P((void *, int));
+pcitag_t pbc_make_tag __P((void *, int, int, int));
+void pbc_decompose_tag __P((void *, pcitag_t, int *, int *, int *));
+pcireg_t pbc_conf_read __P((void *, pcitag_t, int));
+void pbc_conf_write __P((void *, pcitag_t, int, pcireg_t));
+
+int pbc_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
+const char *pbc_intr_string __P((void *, pci_intr_handle_t));
+void *pbc_intr_establish __P((void *, pci_intr_handle_t,
+ int, int (*func)(void *), void *, char *));
+void pbc_intr_disestablish __P((void *, void *));
+int pbc_ether_hw_addr __P((u_int8_t *));
+
+extern void *algor_pci_intr_establish();
+
+struct cfattach pbcpcibr_ca = {
+ sizeof(struct pcibr_softc), pbcpcibrmatch, pbcpcibrattach,
+};
+
+struct cfdriver pbcpcibr_cd = {
+ NULL, "pbcpcibr", DV_DULL,
+};
+
+static int pbcpcibrprint __P((void *, const char *pnp));
+
+struct pcibr_config pbc_config;
+
+int
+pbcpcibrmatch(parent, match, aux)
+ struct device *parent;
+ void *match, *aux;
+{
+ struct cfdata *cf = match;
+ struct confargs *ca = aux;
+
+ /* Make sure that we're looking for a PCI bridge. */
+ if (strcmp(ca->ca_name, pbcpcibr_cd.cd_name) != 0)
+ return (0);
+
+ return (1);
+}
+
+void
+pbcpcibrattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct pcibr_softc *sc = (struct pcibr_softc *)self;
+ struct pcibr_config *lcp;
+ struct pcibus_attach_args pba;
+
+ switch(cputype) {
+ case ALGOR_P4032:
+ V96X_PCI_BASE0 = V96X_PCI_BASE0 & 0xffff0000;
+
+ lcp = sc->sc_pcibr = &pbc_config;
+
+ sc->sc_bus_space.isa_io_base = V96X_PCI_MEM_SPACE;
+ sc->sc_bus_space.isa_mem_base = V96X_PCI_MEM_SPACE;
+ sc->sc_bus_space.isa_io_sparse1 = 0;
+ sc->sc_bus_space.isa_io_sparse2 = 0;
+ sc->sc_bus_space.isa_io_sparse4 = 0;
+ sc->sc_bus_space.isa_io_sparse8 = 0;
+
+ lcp->lc_pc.pc_conf_v = lcp;
+ lcp->lc_pc.pc_attach_hook = pbc_attach_hook;
+ lcp->lc_pc.pc_bus_maxdevs = pbc_bus_maxdevs;
+ lcp->lc_pc.pc_make_tag = pbc_make_tag;
+ lcp->lc_pc.pc_decompose_tag = pbc_decompose_tag;
+ lcp->lc_pc.pc_conf_read = pbc_conf_read;
+ lcp->lc_pc.pc_conf_write = pbc_conf_write;
+ lcp->lc_pc.pc_ether_hw_addr = pbc_ether_hw_addr;
+
+ lcp->lc_pc.pc_intr_v = lcp;
+ lcp->lc_pc.pc_intr_map = pbc_intr_map;
+ lcp->lc_pc.pc_intr_string = pbc_intr_string;
+ lcp->lc_pc.pc_intr_establish = pbc_intr_establish;
+ lcp->lc_pc.pc_intr_disestablish = pbc_intr_disestablish;
+
+ printf(": V3 V962, Revision %x.\n", V96X_PCI_CC_REV);
+ break;
+ }
+
+ pba.pba_busname = "pci";
+ pba.pba_iot = &sc->sc_bus_space;
+ pba.pba_memt = &sc->sc_bus_space;
+ pba.pba_pc = &lcp->lc_pc;
+ pba.pba_bus = 0;
+ config_found(self, &pba, pbcpcibrprint);
+
+}
+
+static int
+pbcpcibrprint(aux, pnp)
+ void *aux;
+ const char *pnp;
+{
+ struct pcibus_attach_args *pba = aux;
+
+ if(pnp)
+ printf("%s at %s", pba->pba_busname, pnp);
+ printf(" bus %d", pba->pba_bus);
+ return(UNCONF);
+}
+
+/*
+ * Get PCI physical address from given viritual address.
+ */
+
+vm_offset_t
+vtophys(va)
+ vm_offset_t va;
+{
+ vm_offset_t pa;
+
+ if(va >= UADDR) { /* Stupid driver have buffer on stack!! */
+ va = (va & ~UADDR) + (vm_offset_t)(curproc->p_addr);
+ }
+ if(va < VM_MIN_KERNEL_ADDRESS) {
+ pa = CACHED_TO_PHYS(va);
+ }
+ else {
+ pa = pmap_extract(vm_map_pmap(phys_map), va);
+ }
+ return(pa);
+}
+
+void
+pbc_attach_hook(parent, self, pba)
+ struct device *parent, *self;
+ struct pcibus_attach_args *pba;
+{
+}
+
+int
+pbc_bus_maxdevs(cpv, busno)
+ void *cpv;
+ int busno;
+{
+ return(16);
+}
+
+pcitag_t
+pbc_make_tag(cpv, bus, dev, fnc)
+ void *cpv;
+ int bus, dev, fnc;
+{
+ return (bus << 16) | (dev << 11) | (fnc << 8);
+}
+
+void
+pbc_decompose_tag(cpv, tag, busp, devp, fncp)
+ void *cpv;
+ pcitag_t tag;
+ int *busp, *devp, *fncp;
+{
+ if (busp != NULL)
+ *busp = (tag >> 16) & 0xff;
+ if (devp != NULL)
+ *devp = (tag >> 11) & 0x1f;
+ if (fncp != NULL)
+ *fncp = (tag >> 8) & 0x7;
+}
+
+pcireg_t
+pbc_conf_read(cpv, tag, offset)
+ void *cpv;
+ pcitag_t tag;
+ int offset;
+{
+ pcireg_t data;
+ u_int32_t addr;
+ int device;
+ int s;
+
+ if((tag >> 16) != 0)
+ return(~0);
+ if(offset & 3 || offset < 0 || offset >= 0x100) {
+ printf ("pci_conf_read: bad reg %x\n", offset);
+ return(~0);
+ }
+
+ device = (tag >> 11) & 0x1f;
+ addr = (0x800 << device) | (tag & 0x380) | offset;
+
+ s = splhigh();
+
+ /* clear aborts */
+ V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
+
+ /* high 12 bits of address go in map register, and set for conf space */
+ V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
+ wbflush();
+
+ /* low 20 bits of address are in the actual address */
+ data = *(volatile pcireg_t *) (V96X_PCI_CONF_SPACE + (addr&0xfffff));
+
+ if (V96X_PCI_STAT & V96X_PCI_STAT_M_ABORT) {
+ V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT;
+ printf ("device %d: master abort\n", device);
+ return(~0);
+ }
+
+ if (V96X_PCI_STAT & V96X_PCI_STAT_T_ABORT) {
+ V96X_PCI_STAT |= V96X_PCI_STAT_T_ABORT;
+ printf ("PCI slot %d: target abort!\n", device);
+ return(~0);
+ }
+
+ splx(s);
+ return(data);
+}
+
+void
+pbc_conf_write(cpv, tag, offset, data)
+ void *cpv;
+ pcitag_t tag;
+ int offset;
+ pcireg_t data;
+{
+ u_int32_t addr;
+ int device;
+ int s;
+
+ device = (tag >> 11) & 0x1f;
+ addr = (0x800 << device) | (tag & 0x380) | offset;
+
+ s = splhigh();
+
+ /* clear aborts */
+ V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
+
+ /* high 12 bits of address go in map register, and set for conf space */
+ V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
+ wbflush();
+
+ /* low 20 bits of address are in the actual address */
+ *(volatile pcireg_t *) (V96X_PCI_CONF_SPACE + (addr&0xfffff)) = data;
+
+ /* wait for write FIFO to empty */
+ do {
+ } while (V96X_FIFO_STAT & V96X_FIFO_STAT_L2P_WR);
+
+ if (V96X_PCI_STAT & V96X_PCI_STAT_M_ABORT) {
+ V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT;
+ printf ("PCI slot %d: conf_write: master abort\n", device);
+ }
+
+ if (V96X_PCI_STAT & V96X_PCI_STAT_T_ABORT) {
+ V96X_PCI_STAT |= V96X_PCI_STAT_T_ABORT;
+ printf ("PCI slot %d: conf_write: target abort!\n", device);
+ }
+
+ splx(s);
+}
+
+/*
+ * Hook to get ethernet hardware address when not in dev rom
+ */
+int
+pbc_ether_hw_addr(cp)
+ u_int8_t *cp;
+{
+ if(cputype == ALGOR_P4032) {
+ cp[0] = 0x00;
+ cp[1] = 0x40;
+ cp[2] = 0xbc;
+ cp[3] = 0x03;
+ cp[4] = 0x00;
+ cp[5] = 0x33;
+ return(0);
+ }
+ return(-1);
+}
+
+int
+pbc_intr_map(lcv, bustag, buspin, line, ihp)
+ void *lcv;
+ pcitag_t bustag;
+ int buspin, line;
+ pci_intr_handle_t *ihp;
+{
+ struct pcibr_config *lcp = lcv;
+ pci_chipset_tag_t pc = &lcp->lc_pc;
+ int device, pirq;
+ u_int8_t pirqline;
+
+ if (buspin == 0) {
+ /* No IRQ used. */
+ *ihp = -1;
+ return 1;
+ }
+ if (buspin > 4) {
+ printf("pbc_intr_map: bad interrupt pin %d\n", buspin);
+ *ihp = -1;
+ return 1;
+ }
+
+ pci_decompose_tag(pc, bustag, NULL, &device, NULL);
+ pirq = buspin - 1;
+
+ switch(device) {
+ case 5: /* DC21041 */
+ pirq = 1;
+ break;
+ case 8: /* NCR SCSI */
+ pirq = 0;
+ break;
+ default:
+ switch (buspin) {
+ case PCI_INTERRUPT_PIN_A:
+ pirq = 0;
+ break;
+ case PCI_INTERRUPT_PIN_B:
+ pirq = 1;
+ break;
+ case PCI_INTERRUPT_PIN_C:
+ pirq = 2;
+ break;
+ case PCI_INTERRUPT_PIN_D:
+ pirq = 3;
+ break;
+ }
+ }
+ *ihp = pirq;
+ return 0;
+}
+
+const char *
+pbc_intr_string(lcv, ih)
+ void *lcv;
+ pci_intr_handle_t ih;
+{
+ static char str[16];
+ struct pcibr_config *lcp = lcv;
+
+ sprintf(str, "pciirq%d", ih);
+ return(str);
+}
+
+void *
+pbc_intr_establish(lcv, ih, level, func, arg, name)
+ void *lcv;
+ pci_intr_handle_t ih;
+ int level;
+ int (*func) __P((void *));
+ void *arg;
+ char *name;
+{
+ struct pcibr_config *lcp = lcv;
+
+ return algor_pci_intr_establish(ih, level, func, arg, name);
+}
+
+void
+pbc_intr_disestablish(lcv, cookie)
+ void *lcv, *cookie;
+{
+ struct pcibr_config *lcp = lcv;
+
+ algor_pci_intr_disestablish(cookie);
+}
--- /dev/null
+/* $OpenBSD: pci_machdep.h,v 1.1 1997/03/12 19:17:01 pefo Exp $ */
+
+/*
+ * Copyright (c) 1996 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+/*
+ * Machine-specific definitions for PCI autoconfiguration.
+ */
+
+/*
+ * Types provided to machine-independent PCI code
+ */
+typedef struct arc_pci_chipset *pci_chipset_tag_t;
+typedef u_long pcitag_t;
+typedef u_long pci_intr_handle_t;
+
+/*
+ * arc-specific PCI structure and type definitions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ */
+struct arc_pci_chipset {
+ void *pc_conf_v;
+ void (*pc_attach_hook) __P((struct device *,
+ struct device *, struct pcibus_attach_args *));
+ int (*pc_bus_maxdevs) __P((void *, int));
+ pcitag_t (*pc_make_tag) __P((void *, int, int, int));
+ void (*pc_decompose_tag) __P((void *, pcitag_t, int *,
+ int *, int *));
+ pcireg_t (*pc_conf_read) __P((void *, pcitag_t, int));
+ void (*pc_conf_write) __P((void *, pcitag_t, int, pcireg_t));
+
+ void *pc_intr_v;
+ int (*pc_intr_map) __P((void *, pcitag_t, int, int,
+ pci_intr_handle_t *));
+ const char *(*pc_intr_string) __P((void *, pci_intr_handle_t));
+ void *(*pc_intr_establish) __P((void *, pci_intr_handle_t,
+ int, int (*)(void *), void *, char *));
+ void (*pc_intr_disestablish) __P((void *, void *));
+ int (*pc_ether_hw_addr) __P((u_int8_t *));
+};
+
+/*
+ * Functions provided to machine-independent PCI code.
+ */
+#define pci_attach_hook(p, s, pba) \
+ (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
+#define pci_bus_maxdevs(c, b) \
+ (*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
+#define pci_make_tag(c, b, d, f) \
+ (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
+#define pci_decompose_tag(c, t, bp, dp, fp) \
+ (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
+#define pci_conf_read(c, t, r) \
+ (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
+#define pci_conf_write(c, t, r, v) \
+ (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
+#define pci_intr_map(c, it, ip, il, ihp) \
+ (*(c)->pc_intr_map)((c)->pc_intr_v, (it), (ip), (il), (ihp))
+#define pci_intr_string(c, ih) \
+ (*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
+#define pci_intr_establish(c, ih, l, h, a, nm) \
+ (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a), (nm))
+#define pci_intr_disestablish(c, iv) \
+ (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
+#define pci_ether_hw_addr(c, p) \
+ (*(c)->pc_ether_hw_addr)((p))
+
--- /dev/null
+/* $OpenBSD: pcibrvar.h,v 1.1 1997/03/12 19:17:02 pefo Exp $ */
+
+/*
+ * Copyright (c) 1997 Per Fogelstrom
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+struct pcibr_config {
+ bus_space_tag_t lc_iot;
+ bus_space_tag_t lc_memt;
+ struct arc_pci_chipset lc_pc;
+ int pci_init_done;
+};
+
+struct pcibr_softc {
+ struct device sc_dev;
+ struct pcibr_config *sc_pcibr;
+ struct arc_bus_space sc_bus_space;
+};
+
+
--- /dev/null
+/*
+ * v96xpbc.h: i960 to PCI bridge controller
+ */
+
+/* Where we map the config space */
+#define V96X_PCI_CONF_SPACE 0xbee00000
+
+/* Where we map the PCI memory space */
+#define V96X_PCI_MEM_SPACE 0xa0000000
+
+/* offsets from base pointer, this construct allows optimisation */
+static char * const _v96xp = (char *)P4032_V96x;
+
+#if #endian(little)
+#define V96XW(x) *(volatile unsigned long *)(_v96xp + (x))
+#define V96XH(x) *(volatile unsigned short *)(_v96xp + (x))
+#define V96XB(x) *(volatile unsigned char *)(_v96xp + (x))
+#else
+#define V96XW(x) *(volatile unsigned long *)(_v96xp + (x))
+#define V96XH(x) *(volatile unsigned short *)(_v96xp + ((x)^2))
+#define V96XB(x) *(volatile unsigned char *)(_v96xp + ((x)^3))
+#endif
+
+#define V96X_PCI_VENDOR V96XH(0x00)
+#define V96X_PCI_DEVICE V96XH(0x02)
+#define V96X_PCI_CMD V96XH(0x04)
+#define V96X_PCI_STAT V96XH(0x06)
+#define V96X_PCI_CC_REV V96XW(0x08)
+#define V96X_PCI_HDR_CFG V96XW(0x0c)
+#define V96X_PCI_IO_BASE V96XW(0x10)
+#define V96X_PCI_BASE0 V96XW(0x14)
+#define V96X_PCI_BASE1 V96XW(0x1c)
+#define V96X_PCI_BPARAM V96XW(0x3c)
+#define V96X_PCI_MAP0 V96XW(0x40)
+#define V96X_PCI_MAP1 V96XW(0x44)
+#define V96X_PCI_INT_STAT V96XW(0x48)
+#define V96X_PCI_INT_CFG V96XW(0x4c)
+#define V96X_LB_BASE0 V96XW(0x54)
+#define V96X_LB_BASE1 V96XW(0x58)
+#define V96X_LB_MAP0 V96XH(0x5e)
+#define V96X_LB_MAP1 V96XH(0x62)
+#define V96X_LB_IO_BASE V96XW(0x6c)
+#define V96X_FIFO_CFG V96XH(0x70)
+#define V96X_FIFO_PRIORITY V96XH(0x72)
+#define V96X_FIFO_STAT V96XH(0x74)
+#define V96X_LB_ISTAT V96XB(0x76)
+#define V96X_LB_IMASK V96XB(0x77)
+#define V96X_SYSTEM V96XH(0x78)
+#define V96X_LB_CFG V96XB(0x7b)
+#define V96X_DMA_PCI_ADDR0 V96XW(0x80)
+#define V96X_DMA_LOCAL_ADDR0 V96XW(0x84)
+#define V96X_DMA_LENGTH0 V96XW(0x88)
+#define V96X_DMA_CTLB_ADR0 V96XW(0x8c)
+#define V96X_DMA_PCI_ADDR1 V96XW(0x90)
+#define V96X_DMA_LOCAL_ADDR1 V96XW(0x94)
+#define V96X_DMA_LENGTH1 V96XW(0x98)
+#define V96X_DMA_CTLB_ADR1 V96XW(0x9c)
+#define V96X_MAIL_DATA(n) V96XB(0xc0+(n))
+#define V96X_LB_MAIL_IEWR V96XH(0xd0)
+#define V96X_LB_MAIL_IERD V96XH(0xd2)
+#define V96X_PCI_MAIL_IEWR V96XH(0xd4)
+#define V96X_PCI_MAIL_IERD V96XH(0xd6)
+#define V96X_MAIL_WR_STAT V96XH(0xd8)
+#define V96X_MAIL_RD_STAT V96XH(0xdc)
+
+#define V96X_PCI_CMD_FBB_EN 0x0200
+#define V96X_PCI_CMD_SERR_EN 0x0100
+#define V96X_PCI_CMD_PAR_EN 0x0040
+#define V96X_PCI_CMD_MASTER_EN 0x0004
+#define V96X_PCI_CMD_MEM_EN 0x0002
+#define V96X_PCI_CMD_IO_EN 0x0001
+
+#define V96X_PCI_STAT_PAR_ERR 0x8000
+#define V96X_PCI_STAT_SYS_ERR 0x4000
+#define V96X_PCI_STAT_M_ABORT 0x2000
+#define V96X_PCI_STAT_T_ABORT 0x1000
+#define V96X_PCI_STAT_DEVSEL 0x0600
+#define V96X_PCI_STAT_PAR_REP 0x0100
+#define V96X_PCI_STAT_FAST_BACK 0x0080
+
+#define V96X_PCI_CC_REV_BASE_CLASS 0xff000000
+#define V96X_PCI_CC_REV_SUB_CLASS 0x00ff0000
+#define V96X_PCI_CC_REV_PROG_IF 0x0000ff00
+#define V96X_PCI_CC_REV_UREV 0x000000f0
+#define V96X_PCI_CC_REV_VREV 0x0000000f
+
+#define V96X_VREV_A 0x0
+#define V96X_VREV_B0 0x1
+#define V96X_VREV_B1 0x2
+#define V96X_VREV_C0 0x3
+
+#define V96X_PCI_HDR_CFG_LT 0x0000ff00
+#define V96X_PCI_HDR_CFG_LT_SHIFT 8
+#define V96X_PCI_HDR_CFG_CLS 0x000000ff
+#define V96X_PCI_HDR_CFG_CLS_SHIFT 0
+
+/* pci access to internal v96xpbc registers */
+#define V96X_PCI_IO_BASE_ADR_BASE 0xfffffff0
+#define V96X_PCI_IO_BASE_PREFETCH 0x00000008
+#define V96X_PCI_IO_BASE_TYPE 0x00000006
+#define V96X_PCI_IO_BASE_IO 0x00000001
+#define V96X_PCI_IO_BASE_MEM 0x00000000
+
+/* pci to local bus aperture 0 base address */
+#define V96X_PCI_BASE0_ADR_BASE 0xfff00000
+#define V96X_PCI_BASE0_ADR_BASEL 0x000fff00
+
+/* pci to local bus aperture 1 base address */
+#define V96X_PCI_BASE1_ADR_BASE 0xfff00000
+#define V96X_PCI_BASE1_ADR_BASEL 0x000fc000
+#define V96X_PCI_BASE1_ADR_DOS_MEM 0x00000700
+
+#define V96X_PCI_BASEx_PREFETCH 0x00000008
+#define V96X_PCI_BASEx_IO 0x00000001
+#define V96X_PCI_BASEx_MEM 0x00000000
+
+/* pci bus parameter register */
+#define V96X_PCI_BPARAM_MAX_LAT 0xff000000
+#define V96X_PCI_BPARAM_MIN_GNT 0x00ff0000
+#define V96X_PCI_BPARAM_INT_PIN 0x00000700
+#define V96X_PCI_BPARAM_INT_LINE 0x0000000f
+
+/* pci bus to local bus address map 0 */
+#define V96X_PCI_MAPx_MAP_ADR 0xfff00000
+#define V96X_PCI_MAPx_RD_POST_INH 0x00008000
+#define V96X_PCI_MAP0_ROM_SIZE 0x00000c00
+#define V96X_PCI_MAPx_SWAP 0x00000300
+#define V96X_PCI_MAPx_ADR_SIZE 0x000000f0
+#define V96X_PCI_MAPx_REG_EN 0x00000002
+#define V96X_PCI_MAPx_ENABLE 0x00000001
+
+#define V96X_ADR_SIZE_1MB (0x0<<4)
+#define V96X_ADR_SIZE_2MB (0x1<<4)
+#define V96X_ADR_SIZE_4MB (0x2<<4)
+#define V96X_ADR_SIZE_8MB (0x3<<4)
+#define V96X_ADR_SIZE_16MB (0x4<<4)
+#define V96X_ADR_SIZE_32MB (0x5<<4)
+#define V96X_ADR_SIZE_64MB (0x6<<4)
+#define V96X_ADR_SIZE_128MB (0x7<<4)
+#define V96X_ADR_SIZE_256MB (0x8<<4)
+#define V96X_ADR_SIZE_DOSMODE (0xc<<4)
+
+#define V96X_SWAP_NONE (0x0<<8)
+#define V96X_SWAP_16BIT (0x1<<8)
+#define V96X_SWAP_8BIT (0x2<<8)
+
+/* pci interruprt status register */
+#define V96X_PCI_INT_STAT_MAILBOX 0x80000000
+#define V96X_PCI_INT_STAT_LOCAL 0x40000000
+#define V96X_PCI_INT_STAT_DMA1 0x02000000
+#define V96X_PCI_INT_STAT_DMA0 0x01000000
+#define V96X_PCI_INT_STAT_INTC_TO_D 0x00004000
+#define V96X_PCI_INT_STAT_INTB_TO_D 0x00002000
+#define V96X_PCI_INT_STAT_INTA_TO_D 0x00001000
+#define V96X_PCI_INT_STAT_INTD_TO_C 0x00000800
+#define V96X_PCI_INT_STAT_INTB_TO_C 0x00000200
+#define V96X_PCI_INT_STAT_INTA_TO_C 0x00000100
+#define V96X_PCI_INT_STAT_INTD_TO_B 0x00000080
+#define V96X_PCI_INT_STAT_INTC_TO_B 0x00000040
+#define V96X_PCI_INT_STAT_INTA_TO_B 0x00000010
+#define V96X_PCI_INT_STAT_INTD_TO_A 0x00000008
+#define V96X_PCI_INT_STAT_INTC_TO_A 0x00000004
+#define V96X_PCI_INT_STAT_INTB_TO_A 0x00000002
+
+/* pci interrupt config register */
+#define V96X_PCI_INT_CFG_MAILBOX 0x80000000
+#define V96X_PCI_INT_CFG_LOCAL 0x40000000
+#define V96X_PCI_INT_CFG_DMA1 0x02000000
+#define V96X_PCI_INT_CFG_DMA0 0x01000000
+#define V96X_PCI_INT_CFG_MODE_D 0x00c00000
+#define V96X_PCI_INT_CFG_MODE_D_SHIFT 22
+#define V96X_PCI_INT_CFG_MODE_C 0x00300000
+#define V96X_PCI_INT_CFG_MODE_C_SHIFT 20
+#define V96X_PCI_INT_CFG_MODE_B 0x000c0000
+#define V96X_PCI_INT_CFG_MODE_B_SHIFT 18
+#define V96X_PCI_INT_CFG_MODE_A 0x00030000
+#define V96X_PCI_INT_CFG_MODE_A_SHIFT 16
+#define V96X_PCI_INT_CFG_MODE_LEVEL 0x0
+#define V96X_PCI_INT_CFG_MODE_EDGE 0x1
+#define V96X_PCI_INT_CFG_MODE_SWCLR 0x2
+#define V96X_PCI_INT_CFG_MODE_HWCLR 0x3
+#define V96X_PCI_INT_CFG_INTD_TO_LB 0x00008000
+#define V96X_PCI_INT_CFG_INTC_TO_D 0x00004000
+#define V96X_PCI_INT_CFG_INTB_TO_D 0x00002000
+#define V96X_PCI_INT_CFG_INTA_TO_D 0x00001000
+#define V96X_PCI_INT_CFG_INTD_TO_C 0x00000800
+#define V96X_PCI_INT_CFG_INTC_TO_LB 0x00000400
+#define V96X_PCI_INT_CFG_INTB_TO_C 0x00000200
+#define V96X_PCI_INT_CFG_INTA_TO_C 0x00000100
+#define V96X_PCI_INT_CFG_INTD_TO_B 0x00000080
+#define V96X_PCI_INT_CFG_INTC_TO_B 0x00000040
+#define V96X_PCI_INT_CFG_INTB_TO_LB 0x00000020
+#define V96X_PCI_INT_CFG_INTA_TO_B 0x00000010
+#define V96X_PCI_INT_CFG_INTD_TO_A 0x00000008
+#define V96X_PCI_INT_CFG_INTC_TO_A 0x00000004
+#define V96X_PCI_INT_CFG_INTB_TO_A 0x00000002
+#define V96X_PCI_INT_CFG_INTA_TO_LB 0x00000001
+
+/* local bus to pci bus aperture 0,1 */
+#define V96X_LB_BASEx_ADR_BASE 0xfff00000
+#define V96X_LB_BASEx_SWAP 0x00000300
+#define V96X_LB_BASEx_ADR_SIZE 0x000000f0
+#define V96X_LB_BASEx_PREFETCH 0x00000008
+#define V96X_LB_BASEx_ENABLE 0x00000001
+
+/* local bus to pci bus address map 0,1 */
+#define V96X_LB_MAPx_MAP_ADR 0xfff0
+#define V96X_LB_MAPx_TYPE 0x0007
+#define V96X_LB_TYPE_IACK (0x0<<1)
+#define V96X_LB_TYPE_IO (0x1<<1)
+#define V96X_LB_TYPE_MEM (0x3<<1)
+#define V96X_LB_TYPE_CONF (0x5<<1)
+
+/* local bus interrupt control, status and masks */
+#define V96X_LB_INTR_MAILBOX 0x80
+#define V96X_LB_INTR_PCI_RD 0x40
+#define V96X_LB_INTR_PCI_WR 0x20
+#define V96X_LB_INTR_PCI_INT 0x10
+#define V96X_LB_INTR_DMA1 0x02
+#define V96X_LB_INTR_DMA0 0x01
+
+/* local bus configuration */
+#define V96X_LB_CFG_TO_256 0x20
+#define V96X_LB_CFG_TO_64 0x00
+#define V96X_LB_CFG_LB_INT 0x02
+#define V96X_LB_CFG_ERR_EN 0x02
+#define V96X_LB_CFG_RDY_EN 0x01
+
+/* fifo configuration register */
+#define V96X_FIFO_CFG_PBRST_MAX 0xc000
+#define V96X_FIFO_CFG_PBRST_MAX_SHIFT 14
+#define V96X_FIFO_CFG_WR_LB 0x3000
+#define V96X_FIFO_CFG_WR_LB_SHIFT 12
+#define V96X_FIFO_CFG_RD_LB1 0x0c00
+#define V96X_FIFO_CFG_RD_LB1_SHIFT 10
+#define V96X_FIFO_CFG_RD_LB0 0x0300
+#define V96X_FIFO_CFG_RD_LB0_SHIFT 8
+#define V96X_FIFO_CFG_LBRST_MAX 0x00c0
+#define V96X_FIFO_CFG_LBRST_MAX_SHIFT 6
+#define V96X_FIFO_CFG_WR_PCI 0x0030
+#define V96X_FIFO_CFG_WR_PCI_SHIFT 4
+#define V96X_FIFO_CFG_RD_PCI1 0x000c
+#define V96X_FIFO_CFG_RD_PCI1_SHIFT 2
+#define V96X_FIFO_CFG_RD_PCI0 0x0003
+#define V96X_FIFO_CFG_RD_PCI0_SHIFT 0
+
+/* meaning of above bitfields */
+
+/* max burst length */
+#define V96X_FIFO_CFG_BRST_4 0x0
+#define V96X_FIFO_CFG_BRST_8 0x1
+#define V96X_FIFO_CFG_BRST_16 0x2
+#define V96X_FIFO_CFG_BRST_256 0x3
+
+/* when to start refilling read fifo */
+#define V96X_FIFO_CFG_RD_NOTFULL 0x0
+#define V96X_FIFO_CFG_RD_HALF 0x1
+#define V96X_FIFO_CFG_RD_EMPTY 0x2
+
+/* when to start emptying write fifo */
+#define V96X_FIFO_CFG_WR_NOTEMPTY 0x0
+#define V96X_FIFO_CFG_WR_3WORDS 0x2
+#define V96X_FIFO_CFG_WR_ENDBRST 0x3
+
+/* fifo priority control */
+#define V96X_FIFO_PRIORITY_LOCAL_RD 0x1000
+#define V96X_FIFO_PRIORITY_LOCAL_WR 0x0000
+#define V96X_FIFO_PRIORITY_LB_RD1 0x0c00
+#define V96X_FIFO_PRIORITY_LB_RD1_SHIFT 10
+#define V96X_FIFO_PRIORITY_LB_RD0 0x0300
+#define V96X_FIFO_PRIORITY_LB_RD0_SHIFT 8
+#define V96X_FIFO_PRIORITY_PCI_RD 0x0010
+#define V96X_FIFO_PRIORITY_PCI_WR 0x0000
+#define V96X_FIFO_PRIORITY_PCI_RD1 0x000c
+#define V96X_FIFO_PRIORITY_PCI_RD1_SHIFT 2
+#define V96X_FIFO_PRIORITY_PCI_RD0 0x0003
+#define V96X_FIFO_PRIORITY_PCI_RD0_SHIFT 0
+
+/* meaning of above bitfields */
+#define V96X_FIFO_PRI_NOFLUSH 0x0
+#define V96X_FIFO_PRI_FLUSHME 0x2
+#define V96X_FIFO_PRI_FLUSHALL 0x3
+
+/* fifo status */
+#define V96X_FIFO_STAT_L2P_WR 0x3000
+#define V96X_FIFO_STAT_L2P_RD1 0x0c00
+#define V96X_FIFO_STAT_L2P_RD0 0x0300
+#define V96X_FIFO_STAT_P2L_WR 0x0030
+#define V96X_FIFO_STAT_P2L_RD1 0x000c
+#define V96X_FIFO_STAT_P2L_RD0 0x0003
+
+#define V96X_DMA_COUNT_CHAIN 0x80000000
+#define V96X_DMA_COUNT_PRIORITY 0x20000000
+#define V96X_DMA_COUNT_P2L 0x10000000
+#define V96X_DMA_COUNT_SWAP 0x0c000000
+#define V96X_DMA_COUNT_ABORT 0x02000000
+#define V96X_DMA_COUNT_DMA_IPR 0x01000000
+
+#define V96X_SYSTEM_RST_OUT 0x8000
+#define V96X_SYSTEM_LOCK 0x4000
+#define V96X_SYSTEM_SPROM_EN 0x2000
+#define V96X_SYSTEM_SCL 0x1000
+#define V96X_SYSTEM_SDA_OUT 0x0800
+#define V96X_SYSTEM_SDA_IN 0x0400
+#define V96X_SYSTEM_POE 0x0200
+#define V96X_SYSTEM_LB_RD_PCI1 0x0040
+#define V96X_SYSTEM_LB_RD_PCI0 0x0020
+#define V96X_SYSTEM_LB_WR_PCI 0x0010
+#define V96X_SYSTEM_PCI_RD_LB1 0x0004
+#define V96X_SYSTEM_PCI_RD_LB0 0x0002
+#define V96X_SYSTEM_PC_WR_LBI 0x0001
+
-/* $OpenBSD: com_pica.c,v 1.1 1996/11/30 13:39:44 niklas Exp $ */
+/* $OpenBSD: com_pica.c,v 1.2 1997/03/12 19:17:03 pefo Exp $ */
/*
* Copyright (c) 1993, 1994 Charles Hannum.
#define CLR(t, f) (t) &= ~(f)
#define ISSET(t, f) ((t) & (f))
-#undef CONADDR /* This is stupid but using devs before config .. */
-#define CONADDR 0xe0006000
-
int com_pica_probe __P((struct device *, void *, void *));
void com_pica_attach __P((struct device *, struct device *, void *));
sizeof(struct com_softc), com_pica_probe, com_pica_attach
};
+struct cfattach com_algor_ca = {
+ sizeof(struct com_softc), com_pica_probe, com_pica_attach
+};
+
int
com_pica_probe(parent, match, aux)
struct device *parent;
if(!BUS_MATCHNAME(ca, "com"))
return(0);
iobase = (long)BUS_CVTADDR(ca);
- iot = 0;
+ iot = &arc_bus;
needioh = 1;
/* if it's in use as console, it's there. */
sc->sc_swflags = 0;
sc->sc_iobase = iobase = (bus_addr_t)BUS_CVTADDR(ca);
sc->sc_ioh = ioh = (bus_space_handle_t)iobase;
- sc->sc_iot = iot = 0;
+ sc->sc_iot = iot = &arc_bus;
if (iobase == comconsaddr) {
comconsattached = 1;
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