The apic timer mode, mask, and divisor are set during lapic_timer_trigger().
We don't need to reset them when rearming the timer. On physical hardware
the difference is too small to measure, but skipping two apic writes may be
a bit faster when we're running in a VM.
Bochs also likes to log when the apic divisor is changed:
38569516308i[APIC0 ] set timer divide factor to 1
38569517335i[APIC0 ] set timer divide factor to 1
38569518042i[APIC0 ] set timer divide factor to 1
[...]
With this change, Bochs is a lot less noisy.
Idea from mlarkin@.
ok mlarkin@
-/* $OpenBSD: lapic.c,v 1.66 2023/01/31 19:11:47 cheloha Exp $ */
+/* $OpenBSD: lapic.c,v 1.67 2023/03/08 18:05:05 cheloha Exp $ */
/* $NetBSD: lapic.c,v 1.2 2003/05/08 01:04:35 fvdl Exp $ */
/*-
cycles = (nsecs * lapic_timer_nsec_cycle_ratio) >> 32;
if (cycles == 0)
cycles = 1;
- lapic_timer_oneshot(0, cycles);
+ lapic_writereg(LAPIC_ICR_TIMER, cycles);
}
void