The 486DLC is a 486-class CPU which we no longer support on i386.
The 6x86 (also known as the M1) did not support CPUID by default[*]
so extra support code is needed to differentiate between these early
Cyrix processors in order to apply some errata that the M1 needs.
However the 6x86 doesn't implement the RDTSC instruction so we can
remove support code for this CPU at this point.
Cyrix implemented RDTSC in the 6x86MX (also known as the M2). So
this is likely the earliest Cyrix CPU that we can support on i386.
We keep the support code in "cyrix6x86_cpu_setup" because early
6x86MX CPUs would continue to benefit from this fixup code.
[*]: CPUID can be enabled on the Cyrix 6x86 by setting bit 7 of
CCR4
ok mlarkin@, jsg@
-/* $OpenBSD: locore0.S,v 1.7 2022/08/15 04:17:50 daniel Exp $ */
+/* $OpenBSD: locore0.S,v 1.8 2022/08/20 23:33:53 daniel Exp $ */
/* $NetBSD: locore.s,v 1.145 1996/05/03 19:41:19 christos Exp $ */
/*-
jnz .Ltry586
.Lis486: movl $CPU_486,RELOC(_C_LABEL(cpu))
- /*
- * Check Cyrix CPU
- * Cyrix CPUs do not change the undefined flags following
- * execution of the divide instruction which divides 5 by 2.
- *
- * Note: CPUID is enabled on M2, so it passes another way.
- */
- pushfl
- movl $0x5555, %eax
- xorl %edx, %edx
- movl $2, %ecx
- clc
- divl %ecx
- jnc .Ltrycyrix486
- popfl
- jmp 2f
-.Ltrycyrix486:
- movl $CPU_6x86,RELOC(_C_LABEL(cpu)) # set CPU type
- /*
- * Check for Cyrix 486 CPU by seeing if the flags change during a
- * divide. This is documented in the Cx486SLC/e SMM Programmer's
- * Guide.
- */
- xorl %edx,%edx
- cmpl %edx,%edx # set flags to known state
- pushfl
- popl %ecx # store flags in ecx
- movl $-1,%eax
- movl $4,%ebx
- divl %ebx # do a long division
- pushfl
- popl %eax
- xorl %ecx,%eax # are the flags different?
- testl $0x8d5,%eax # only check C|PF|AF|Z|N|V
- jne 2f # yes; must not be Cyrix CPU
- movl $CPU_486DLC,RELOC(_C_LABEL(cpu)) # set CPU type
-
- /* Disable caching of the ISA hole only. */
- invd
- movb $CCR0,%al # Configuration Register index (CCR0)
- outb %al,$0x22
- inb $0x23,%al
- orb $(CCR0_NC1|CCR0_BARB),%al
- movb %al,%ah
- movb $CCR0,%al
- outb %al,$0x22
- movb %ah,%al
- outb %al,$0x23
- invd
-
jmp 2f
.Ltry586: /* Use the `cpuid' instruction. */
-/* $OpenBSD: machdep.c,v 1.653 2022/08/18 13:05:43 jsg Exp $ */
+/* $OpenBSD: machdep.c,v 1.654 2022/08/20 23:33:53 daniel Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
* We deal with the rest in a different way.
*/
const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
- { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486,
- NULL}, /* CPU_486SX */
{ CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486,
NULL}, /* CPU_486 */
- { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486,
- NULL}, /* CPU_486DLC */
- { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
- cyrix6x86_cpu_setup}, /* CPU_6x86 */
};
const char *classnames[] = {
ci->cpu_class = class;
- if (cpu == CPU_486DLC)
- printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
-
/*
* Enable ring 0 write protection.
*/
-/* $OpenBSD: cputypes.h,v 1.13 2022/08/15 04:17:51 daniel Exp $ */
+/* $OpenBSD: cputypes.h,v 1.14 2022/08/20 23:33:53 daniel Exp $ */
/* $NetBSD: cputypes.h,v 1.10 1997/10/18 04:51:03 mikel Exp $ */
/*
#define CPUCLASS_686 3
/*
- * Kinds of Processor. Only the first 7 are used, as they are processors
- * that might not have a cpuid instruction.
+ * Kind of Processor.
*/
-#define CPU_486SX 2 /* Intel 80486SX */
-#define CPU_486 3 /* Intel 80486DX */
-#define CPU_486DLC 4 /* Cyrix 486DLC */
-#define CPU_6x86 5 /* Cyrix/IBM 6x86 */
-#define CPU_586 7 /* Intel P.....m (I hate lawyers; it's TM) */
-#define CPU_AM586 8 /* AMD Am486 and Am5x86 */
-#define CPU_K5 9 /* AMD K5 */
-#define CPU_K6 10 /* AMD K6 */
-#define CPU_686 11 /* Intel P.....m Pro */
+#define CPU_486 0 /* Intel 80486DX */
/*
* CPU vendors
-/* $OpenBSD: specialreg.h,v 1.79 2022/02/21 10:06:35 jsg Exp $ */
+/* $OpenBSD: specialreg.h,v 1.80 2022/08/20 23:33:53 daniel Exp $ */
/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
/*-
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
-/*
- * Cyrix 486 DLC special registers, accessible as IO ports.
- */
-#define CCR0 0xc0 /* configuration control register 0 */
-#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
-#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
-#define CCR0_A20M 0x04 /* enables A20M# input pin */
-#define CCR0_KEN 0x08 /* enables KEN# input pin */
-#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
-#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
-#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
-#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
-
-#define CCR1 0xc1 /* configuration control register 1 */
-#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
-/* the remaining 7 bits of this register are reserved */
-
/*
* bits in CR3
*/
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