-/* $OpenBSD: dec_2100_a50.c,v 1.5 1996/10/30 22:38:01 niklas Exp $ */
-/* $NetBSD: dec_2100_a50.c,v 1.14 1996/10/13 02:59:28 christos Exp $ */
+/* $OpenBSD: dec_2100_a50.c,v 1.6 1996/12/08 00:20:14 niklas Exp $ */
+/* $NetBSD: dec_2100_a50.c,v 1.15 1996/10/23 04:12:13 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <machine/autoconf.h>
#include <dev/isa/isavar.h>
-#include <dev/isa/comreg.h>
-#include <dev/isa/comvar.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
/* serial console ... */
/* XXX */
{
- extern int comconsinit; /* set */
- extern int comdefaultrate;
- extern int comcngetc __P((dev_t));
- extern void comcnputc __P((dev_t, int));
- extern void comcnpollc __P((dev_t, int));
static struct consdev comcons = { NULL, NULL,
comcngetc, comcnputc, comcnpollc, NODEV, 1 };
comconsaddr = 0x3f8;
comconsinit = 0;
- comconsbc = &acp->ac_bc;
- if (bus_io_map(comconsbc, comconsaddr, COM_NPORTS,
- &comconsioh))
+ comconsiot = acp->ac_iot;
+ if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS,
+ 0, &comconsioh))
panic("can't map serial console I/O ports");
comconscflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
cn_tab = &comcons;
comcons.cn_dev = makedev(26, 0); /* XXX */
case 3:
/* display console ... */
/* XXX */
- pci_display_console(&acp->ac_bc, &acp->ac_pc,
+ pci_display_console(acp->ac_iot, acp->ac_memt, &acp->ac_pc,
(ctb->ctb_turboslot >> 8) & 0xff,
ctb->ctb_turboslot & 0xff, 0);
break;
-/* $OpenBSD: dec_axppci_33.c,v 1.4 1996/10/30 22:38:06 niklas Exp $ */
-/* $NetBSD: dec_axppci_33.c,v 1.12 1996/10/13 02:59:32 christos Exp $ */
+/* $OpenBSD: dec_axppci_33.c,v 1.5 1996/12/08 00:20:16 niklas Exp $ */
+/* $NetBSD: dec_axppci_33.c,v 1.13 1996/10/23 04:12:14 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <machine/autoconf.h>
#include <dev/isa/isavar.h>
-#include <dev/isa/comreg.h>
-#include <dev/isa/comvar.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
/* serial console ... */
/* XXX */
{
- extern int comconsinit; /* set */
- extern int comdefaultrate;
- extern int comcngetc __P((dev_t));
- extern void comcnputc __P((dev_t, int));
- extern void comcnpollc __P((dev_t, int));
static struct consdev comcons = { NULL, NULL,
comcngetc, comcnputc, comcnpollc, NODEV, 1 };
comconsaddr = 0x3f8;
comconsinit = 0;
- comconsbc = &lcp->lc_bc;
- if (bus_io_map(comconsbc, comconsaddr, COM_NPORTS,
- &comconsioh))
+ comconsiot = lcp->lc_iot;
+ if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS,
+ 0, &comconsioh))
panic("can't map serial console I/O ports");
comconscflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
cn_tab = &comcons;
comcons.cn_dev = makedev(26, 0); /* XXX */
case 3:
/* display console ... */
/* XXX */
- pci_display_console(&lcp->lc_bc, &lcp->lc_pc,
+ pci_display_console(lcp->lc_iot, lcp->lc_memt, &lcp->lc_pc,
(ctb->ctb_turboslot >> 8) & 0xff,
ctb->ctb_turboslot & 0xff, 0);
break;
-/* $OpenBSD: dec_kn20aa.c,v 1.4 1996/10/30 22:38:08 niklas Exp $ */
-/* $NetBSD: dec_kn20aa.c,v 1.12 1996/10/13 02:59:33 christos Exp $ */
+/* $OpenBSD: dec_kn20aa.c,v 1.5 1996/12/08 00:20:17 niklas Exp $ */
+/* $NetBSD: dec_kn20aa.c,v 1.13 1996/10/23 04:12:15 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <machine/autoconf.h>
#include <dev/isa/isavar.h>
-#include <dev/isa/comreg.h>
-#include <dev/isa/comvar.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
/* serial console ... */
/* XXX */
{
- extern int comconsinit; /* set */
- extern int comdefaultrate;
- extern int comcngetc __P((dev_t));
- extern void comcnputc __P((dev_t, int));
- extern void comcnpollc __P((dev_t, int));
static struct consdev comcons = { NULL, NULL,
comcngetc, comcnputc, comcnpollc, NODEV, 1 };
comconsaddr = 0x3f8;
comconsinit = 0;
- comconsbc = &ccp->cc_bc;
- if (bus_io_map(comconsbc, comconsaddr, COM_NPORTS,
- &comconsioh))
+ comconsiot = ccp->cc_iot;
+ if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS,
+ 0, &comconsioh))
panic("can't map serial console I/O ports");
comconscflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
- cominit(comconsbc, comconsioh, comdefaultrate);
+ cominit(comconsiot, comconsioh, comdefaultrate);
cn_tab = &comcons;
comcons.cn_dev = makedev(26, 0); /* XXX */
case 3:
/* display console ... */
/* XXX */
- pci_display_console(&ccp->cc_bc, &ccp->cc_pc,
+ pci_display_console(ccp->cc_iot, ccp->cc_memt, &ccp->cc_pc,
(ctb->ctb_turboslot >> 8) & 0xff,
ctb->ctb_turboslot & 0xff, 0);
break;
-/* $OpenBSD: machdep.c,v 1.12 1996/11/23 23:19:23 kstailey Exp $ */
-/* $NetBSD: machdep.c,v 1.49 1996/10/18 20:35:23 cgd Exp $ */
+/* $OpenBSD: machdep.c,v 1.13 1996/12/08 00:20:18 niklas Exp $ */
+/* $NetBSD: machdep.c,v 1.52 1996/11/06 20:19:19 cgd Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
/*
* The following primitives manipulate the run queues. _whichqs tells which
* of the 32 queues _qs have processes in them. Setrunqueue puts processes
- * into queues, Remrq removes them from queues. The running process is on
- * no queue, other processes are on a queue related to p->p_priority, divided
- * by 4 actually to shrink the 0-127 range of priorities into the 32 available
- * queues.
+ * into queues, Remrunqueue removes them from queues. The running process is
+ * on no queue, other processes are on a queue related to p->p_priority,
+ * divided by 4 actually to shrink the 0-127 range of priorities into the 32
+ * available queues.
*/
/*
* setrunqueue(p)
}
/*
- * Remrunqueue(p)
+ * remrunqueue(p)
*
* Call should be made at splclock().
*/
return 0;
}
#endif
+
+/* XXX XXX BEGIN XXX XXX */
+vm_offset_t alpha_XXX_dmamap_or; /* XXX */
+ /* XXX */
+vm_offset_t /* XXX */
+alpha_XXX_dmamap(v) /* XXX */
+ vm_offset_t v; /* XXX */
+{ /* XXX */
+ /* XXX */
+ return (vtophys(v) | alpha_XXX_dmamap_or); /* XXX */
+} /* XXX */
+/* XXX XXX END XXX XXX */
-# $OpenBSD: GENERIC,v 1.10 1996/11/11 19:43:28 kstailey Exp $
+# $OpenBSD: GENERIC,v 1.11 1996/12/08 00:20:20 niklas Exp $
# $NetBSD: GENERIC,v 1.24 1996/09/27 17:08:32 cgd Exp $
#
# Generic Alpha kernel. Enough to get booted, etc., but not much more.
# PCI devices
#ahc* at pci? dev ? function ? # AHA-28xx SCSI (NOT 64-BIT)
de* at pci? dev ? function ? # 21x4[012]-based Ethernet
-en* at pci? dev ? function ? # ENI PCI ATM (untested)
+#en* at pci? dev ? function ? # ENI PCI ATM (untested)
ep* at pci? dev ? function ? # 3COM 3c59x (untested)
fpa* at pci? dev ? function ? # DEC DEFPA FDDI cards
le* at pci? dev ? function ? # PCI LANCE Ethernet (untested)
-# $OpenBSD: Makefile.alpha,v 1.8 1996/10/30 22:38:41 niklas Exp $
+# $OpenBSD: Makefile.alpha,v 1.9 1996/12/08 00:20:21 niklas Exp $
# $NetBSD: Makefile.alpha,v 1.25 1996/09/27 17:33:04 cgd Exp $
# Makefile for OpenBSD
CPPFLAGS= ${INCLUDES} ${IDENT} ${PARAM} -D_KERNEL -Dalpha
CDIAGFLAGS?= -Werror -Wall -Wstrict-prototypes -Wmissing-prototypes \
- -Wno-uninitialized -Wno-format
+ -Wcast-qual -Wno-uninitialized -Wno-format
CMACHFLAGS= -mno-fp-regs
CFLAGS= ${DEBUG} -O2 ${CDIAGFLAGS} ${CMACHFLAGS} ${COPTS}
-# $OpenBSD: files.alpha,v 1.6 1996/10/30 22:38:45 niklas Exp $
-# $NetBSD: files.alpha,v 1.26 1996/09/27 17:14:35 cgd Exp $
+# $OpenBSD: files.alpha,v 1.7 1996/12/08 00:20:22 niklas Exp $
+# $NetBSD: files.alpha,v 1.27 1996/10/22 21:15:45 cgd Exp $
#
# alpha-specific configuration info
device tcasic: tcbus
attach tcasic at mainbus
file arch/alpha/tc/tcasic.c tcasic
-file arch/alpha/tc/tc_bus_io.c tcasic
file arch/alpha/tc/tc_bus_mem.c tcasic
file arch/alpha/tc/tc_3000_500.c tcasic & dec_3000_500
file arch/alpha/tc/tc_3000_300.c tcasic & dec_3000_300
-# $OpenBSD: std.alpha,v 1.3 1996/10/30 22:38:46 niklas Exp $
+# $OpenBSD: std.alpha,v 1.4 1996/12/08 00:20:23 niklas Exp $
# $NetBSD: std.alpha,v 1.8 1996/09/27 17:18:02 cgd Exp $
#
# Standard/required configuration info for OpenBSD/alpha.
machine alpha
makeoptions DEBUG="-g"
-#makeoptions CWARNFLAGS="-Werror"
+# NetBSD has these, OpenBSD has them in CDIAGFLAGS in Makefile.alpha instead.
+#makeoptions CWARNFLAGS="-Werror -Wcast-qual"
options EXEC_ECOFF
options EXEC_ELF64
+++ /dev/null
-/* $OpenBSD: bus.old.h,v 1.1 1996/11/12 20:29:27 niklas Exp $ */
-/* $NetBSD: bus.h,v 1.4 1996/06/11 21:16:21 cgd Exp $ */
-
-/*
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#ifndef _ALPHA_BUS_H_
-#define _ALPHA_BUS_H_
-
-/*
- * I/O addresses (in bus space)
- */
-typedef u_long bus_io_addr_t;
-typedef u_long bus_io_size_t;
-
-/*
- * Memory addresses (in bus space)
- */
-typedef u_long bus_mem_addr_t;
-typedef u_long bus_mem_size_t;
-
-/*
- * Access methods for bus resources, I/O space, and memory space.
- */
-typedef struct alpha_bus_chipset *bus_chipset_tag_t;
-typedef u_long bus_io_handle_t;
-typedef u_long bus_mem_handle_t;
-
-struct alpha_bus_chipset {
- /* I/O-space cookie */
- void *bc_i_v;
-
- /* I/O-space control functions */
- int (*bc_i_map) __P((void *v, bus_io_addr_t port,
- bus_io_size_t size, bus_io_handle_t *iohp));
- void (*bc_i_unmap) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t size));
- int (*bc_i_subregion) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t offset, bus_io_size_t size,
- bus_io_handle_t *nioh));
-
- /* I/O-space read functions */
- u_int8_t (*bc_ir1) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off));
- u_int16_t (*bc_ir2) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off));
- u_int32_t (*bc_ir4) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off));
- u_int64_t (*bc_ir8) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off));
-
- /* I/O-space read-multiple functions */
- void (*bc_irm1) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int8_t *addr,
- bus_io_size_t count));
- void (*bc_irm2) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int16_t *addr,
- bus_io_size_t count));
- void (*bc_irm4) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int32_t *addr,
- bus_io_size_t count));
- void (*bc_irm8) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int64_t *addr,
- bus_io_size_t count));
-
- /* I/O-space write functions */
- void (*bc_iw1) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int8_t val));
- void (*bc_iw2) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int16_t val));
- void (*bc_iw4) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int32_t val));
- void (*bc_iw8) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, u_int64_t val));
-
- /* I/O-space write-multiple functions */
- void (*bc_iwm1) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, const u_int8_t *addr,
- bus_io_size_t count));
- void (*bc_iwm2) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, const u_int16_t *addr,
- bus_io_size_t count));
- void (*bc_iwm4) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, const u_int32_t *addr,
- bus_io_size_t count));
- void (*bc_iwm8) __P((void *v, bus_io_handle_t ioh,
- bus_io_size_t off, const u_int64_t *addr,
- bus_io_size_t count));
-
- /* Mem-space cookie */
- void *bc_m_v;
-
- /* Mem-space control functions */
- int (*bc_m_map) __P((void *v, bus_mem_addr_t buspa,
- bus_mem_size_t size, int cacheable,
- bus_mem_handle_t *mhp));
- void (*bc_m_unmap) __P((void *v, bus_mem_handle_t mh,
- bus_mem_size_t size));
- int (*bc_m_subregion) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t offset, bus_mem_size_t size,
- bus_mem_handle_t *nmemh));
-
- /* Mem-space read functions */
- u_int8_t (*bc_mr1) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off));
- u_int16_t (*bc_mr2) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off));
- u_int32_t (*bc_mr4) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off));
- u_int64_t (*bc_mr8) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off));
-
- /* Mem-space write functions */
- void (*bc_mw1) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off, u_int8_t val));
- void (*bc_mw2) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off, u_int16_t val));
- void (*bc_mw4) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off, u_int32_t val));
- void (*bc_mw8) __P((void *v, bus_mem_handle_t memh,
- bus_mem_size_t off, u_int64_t val));
-
- /* XXX THIS DOES NOT YET BELONG HERE */
- vm_offset_t (*bc_XXX_dmamap) __P((void *addr));
-};
-
-#define __bc_CONCAT(A,B) __CONCAT(A,B)
-#define __bc_ABC(A,B,C) __bc_CONCAT(A,__bc_CONCAT(B,C))
-#define __bc_ABCD(A,B,C,D) __bc_CONCAT(__bc_ABC(A,B,C),D)
-
-#define __bc_rd(t, h, o, sz, sp) \
- (*(t)->__bc_ABCD(bc_,sp,r,sz))((t)->__bc_ABC(bc_,sp,_v), h, o)
-
-#define __bc_wr(t, h, o, v, sz, sp) \
- (*(t)->__bc_ABCD(bc_,sp,w,sz))((t)->__bc_ABC(bc_,sp,_v), h, o, v)
-
-#define bus_io_map(t, port, size, iohp) \
- (*(t)->bc_i_map)((t)->bc_i_v, (port), (size), (iohp))
-#define bus_io_unmap(t, ioh, size) \
- (*(t)->bc_i_unmap)((t)->bc_i_v, (ioh), (size))
-#define bus_io_subregion(t, ioh, offset, size, nioh) \
- (*(t)->bc_i_unmap)((t)->bc_i_v, (ioh), (offset), (size), (nioh))
-
-#define __bc_io_multi(t, h, o, a, s, dir, sz) \
- (*(t)->__bc_ABCD(bc_i,dir,m,sz))((t)->bc_i_v, h, o, a, s)
-
-#define bus_io_read_1(t, h, o) __bc_rd((t),(h),(o),1,i)
-#define bus_io_read_2(t, h, o) __bc_rd((t),(h),(o),2,i)
-#define bus_io_read_4(t, h, o) __bc_rd((t),(h),(o),4,i)
-#define bus_io_read_8(t, h, o) __bc_rd((t),(h),(o),8,i)
-
-#define bus_io_read_multi_1(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),r,1)
-#define bus_io_read_multi_2(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),r,2)
-#define bus_io_read_multi_4(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),r,4)
-#define bus_io_read_multi_8(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),r,8)
-
-#define bus_io_write_1(t, h, o, v) __bc_wr((t),(h),(o),(v),1,i)
-#define bus_io_write_2(t, h, o, v) __bc_wr((t),(h),(o),(v),2,i)
-#define bus_io_write_4(t, h, o, v) __bc_wr((t),(h),(o),(v),4,i)
-#define bus_io_write_8(t, h, o, v) __bc_wr((t),(h),(o),(v),8,i)
-
-#define bus_io_write_multi_1(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),w,1)
-#define bus_io_write_multi_2(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),w,2)
-#define bus_io_write_multi_4(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),w,4)
-#define bus_io_write_multi_8(t, h, o, a, s) \
- __bc_io_multi((t),(h),(o),(a),(s),w,8)
-
-#define bus_mem_map(t, bpa, size, cacheable, mhp) \
- (*(t)->bc_m_map)((t)->bc_m_v, (bpa), (size), (cacheable), (mhp))
-#define bus_mem_unmap(t, memh, size) \
- (*(t)->bc_m_unmap)((t)->bc_m_v, (memh), (size))
-#define bus_mem_subregion(t, memh, offset, size, nmemh) \
- (*(t)->bc_m_unmap)((t)->bc_i_v, (memh), (offset), (size), (nmemh))
-
-#define bus_mem_read_1(t, h, o) __bc_rd((t),(h),(o),1,m)
-#define bus_mem_read_2(t, h, o) __bc_rd((t),(h),(o),2,m)
-#define bus_mem_read_4(t, h, o) __bc_rd((t),(h),(o),4,m)
-#define bus_mem_read_8(t, h, o) __bc_rd((t),(h),(o),8,m)
-
-#define bus_mem_write_1(t, h, o, v) __bc_wr((t),(h),(o),(v),1,m)
-#define bus_mem_write_2(t, h, o, v) __bc_wr((t),(h),(o),(v),2,m)
-#define bus_mem_write_4(t, h, o, v) __bc_wr((t),(h),(o),(v),4,m)
-#define bus_mem_write_8(t, h, o, v) __bc_wr((t),(h),(o),(v),8,m)
-
-/* XXX THIS DOES NOT BELONG HERE YET. */
-#define __alpha_bus_XXX_dmamap(t, va) (*(t)->bc_XXX_dmamap)((va))
-
-#endif /* _ALPHA_BUS_H_ */
-/* $OpenBSD: param.h,v 1.6 1996/10/30 22:39:13 niklas Exp $ */
-/* $NetBSD: param.h,v 1.13 1996/07/09 00:33:23 cgd Exp $ */
+/* $OpenBSD: param.h,v 1.7 1996/12/08 00:20:25 niklas Exp $ */
+/* $NetBSD: param.h,v 1.14 1996/10/25 20:48:59 cgd Exp $ */
/*
* Copyright (c) 1988 University of Utah.
void delay __P((unsigned long));
#define DELAY(n) delay(n)
-/* XXX ALL OF THE FOLLOWING BELONG IN INTR.H */
+/* XXX THE FOLLOWING PROTOTYPE BELONGS IN INTR.H */
int spl0 __P((void)); /* drop ipl to zero */
/* XXX END INTR.H */
+/* XXX THE FOLLOWING PROTOTYPE SHOULD BE A BUS.H INTERFACE */
+vm_offset_t alpha_XXX_dmamap __P((vm_offset_t));
+/* XXX END BUS.H */
+
#endif
#endif /* !_KERNEL */
-/* $OpenBSD: mcclock_isa.c,v 1.4 1996/11/12 20:29:31 niklas Exp $ */
-/* $NetBSD: mcclock_isa.c,v 1.2 1996/04/17 22:22:46 cgd Exp $ */
+/* $OpenBSD: mcclock_isa.c,v 1.5 1996/12/08 00:20:27 niklas Exp $ */
+/* $NetBSD: mcclock_isa.c,v 1.3 1996/10/23 04:12:19 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <sys/systm.h>
#include <sys/device.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <alpha/alpha/clockvar.h>
#include <alpha/alpha/mcclockvar.h>
struct mcclock_isa_softc {
struct mcclock_softc sc_mcclock;
- bus_chipset_tag_t sc_bc;
- bus_io_handle_t sc_ioh;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
};
int mcclock_isa_match __P((struct device *, void *, void *));
struct isa_attach_args *ia = aux;
struct mcclock_isa_softc *sc = (struct mcclock_isa_softc *)self;
- sc->sc_bc = ia->ia_bc;
- if (bus_io_map(sc->sc_bc, ia->ia_iobase, ia->ia_iosize, &sc->sc_ioh))
+ sc->sc_iot = ia->ia_iot;
+ if (bus_space_map(sc->sc_iot, ia->ia_iobase, ia->ia_iosize, 0,
+ &sc->sc_ioh))
panic("mcclock_isa_attach: couldn't map clock I/O space");
mcclock_attach(&sc->sc_mcclock, &mcclock_isa_busfns);
u_int reg, datum;
{
struct mcclock_isa_softc *sc = (struct mcclock_isa_softc *)mcsc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
- bus_io_write_1(bc, ioh, 0, reg);
- bus_io_write_1(bc, ioh, 1, datum);
+ bus_space_write_1(iot, ioh, 0, reg);
+ bus_space_write_1(iot, ioh, 1, datum);
}
u_int
u_int reg;
{
struct mcclock_isa_softc *sc = (struct mcclock_isa_softc *)mcsc;
- bus_chipset_tag_t bc = sc->sc_bc;
- bus_io_handle_t ioh = sc->sc_ioh;
+ bus_space_tag_t iot = sc->sc_iot;
+ bus_space_handle_t ioh = sc->sc_ioh;
- bus_io_write_1(bc, ioh, 0, reg);
- return bus_io_read_1(bc, ioh, 1);
+ bus_space_write_1(iot, ioh, 0, reg);
+ return bus_space_read_1(iot, ioh, 1);
}
-/* $OpenBSD: pckbd.c,v 1.7 1996/11/12 20:29:32 niklas Exp $ */
-/* $NetBSD: pckbd.c,v 1.9 1996/10/13 02:59:56 christos Exp $ */
+/* $OpenBSD: pckbd.c,v 1.8 1996/12/08 00:20:28 niklas Exp $ */
+/* $NetBSD: pckbd.c,v 1.10 1996/10/23 04:12:20 cgd Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995 Charles Hannum. All rights reserved.
#include <sys/device.h>
#include <machine/intr.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
typematic_rate = 0xff, /* don't update until set by user */
old_typematic_rate = 0xff;
-bus_chipset_tag_t pckbd_bc;
+bus_space_tag_t pckbd_iot;
isa_chipset_tag_t pckbd_ic;
-bus_io_handle_t pckbd_data_ioh;
+bus_space_handle_t pckbd_data_ioh;
#define pckbd_out_ioh pckbd_data_ioh
-bus_io_handle_t pckbd_status_ioh;
+bus_space_handle_t pckbd_status_ioh;
#define pckbd_cmd_ioh pckbd_status_ioh
-bus_io_handle_t pckbd_timer_ioh;
-bus_io_handle_t pckbd_pitaux_ioh;
-bus_io_handle_t pckbd_delay_ioh;
+bus_space_handle_t pckbd_timer_ioh;
+bus_space_handle_t pckbd_pitaux_ioh;
+bus_space_handle_t pckbd_delay_ioh;
struct pckbd_softc {
struct device sc_dev;
#define KBD_DELAY \
do { \
- bus_io_read_1(pckbd_bc, pckbd_delay_ioh, 0); \
- bus_io_read_1(pckbd_bc, pckbd_delay_ioh, 0); \
- bus_io_read_1(pckbd_bc, pckbd_delay_ioh, 0); \
- bus_io_read_1(pckbd_bc, pckbd_delay_ioh, 0); \
+ bus_space_read_1(pckbd_iot, pckbd_delay_ioh, 0); \
+ bus_space_read_1(pckbd_iot, pckbd_delay_ioh, 0); \
+ bus_space_read_1(pckbd_iot, pckbd_delay_ioh, 0); \
+ bus_space_read_1(pckbd_iot, pckbd_delay_ioh, 0); \
} while(0)
static __inline int
u_int i;
for (i = 100000; i; i--)
- if ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_IBF)
+ if ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_IBF)
== 0) {
KBD_DELAY;
return 1;
u_int i;
for (i = 100000; i; i--)
- if ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB)
+ if ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB)
!= 0) {
KBD_DELAY;
return 1;
u_int i;
for (i = 10; i; i--) {
- if ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB)
+ if ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB)
== 0)
return;
KBD_DELAY;
- (void) bus_io_read_1(pckbd_bc, pckbd_data_ioh, 0);
+ (void) bus_space_read_1(pckbd_iot, pckbd_data_ioh, 0);
}
}
if (!kbd_wait_output())
return -1;
- bus_io_write_1(pckbd_bc, pckbd_cmd_ioh, 0, K_RDCMDBYTE);
+ bus_space_write_1(pckbd_iot, pckbd_cmd_ioh, 0, K_RDCMDBYTE);
if (!kbd_wait_input())
return -1;
- return bus_io_read_1(pckbd_bc, pckbd_data_ioh, 0);
+ return bus_space_read_1(pckbd_iot, pckbd_data_ioh, 0);
}
#endif
if (!kbd_wait_output())
return 0;
- bus_io_write_1(pckbd_bc, pckbd_cmd_ioh, 0, K_LDCMDBYTE);
+ bus_space_write_1(pckbd_iot, pckbd_cmd_ioh, 0, K_LDCMDBYTE);
if (!kbd_wait_output())
return 0;
- bus_io_write_1(pckbd_bc, pckbd_out_ioh, 0, val);
+ bus_space_write_1(pckbd_iot, pckbd_out_ioh, 0, val);
return 1;
}
if (!kbd_wait_output())
return 0;
ack = nak = 0;
- bus_io_write_1(pckbd_bc, pckbd_out_ioh, 0, val);
+ bus_space_write_1(pckbd_iot, pckbd_out_ioh, 0, val);
if (polling)
for (i = 100000; i; i--) {
- if (bus_io_read_1(pckbd_bc,
+ if (bus_space_read_1(pckbd_iot,
pckbd_status_ioh, 0) & KBS_DIB) {
register u_char c;
KBD_DELAY;
- c = bus_io_read_1(pckbd_bc,
+ c = bus_space_read_1(pckbd_iot,
pckbd_data_ioh, 0);
if (c == KBR_ACK || c == KBR_ECHO) {
ack = 1;
}
else
for (i = 100000; i; i--) {
- (void) bus_io_read_1(pckbd_bc,
+ (void) bus_space_read_1(pckbd_iot,
pckbd_status_ioh, 0);
if (ack)
return 1;
struct isa_attach_args *ia = aux;
u_int i;
- pckbd_bc = ia->ia_bc;
+ pckbd_iot = ia->ia_iot;
pckbd_ic = ia->ia_ic;
- if (bus_io_map(pckbd_bc, KBDATAP, 1, &pckbd_data_ioh) ||
- bus_io_map(pckbd_bc, KBSTATP, 1, &pckbd_status_ioh) ||
- bus_io_map(pckbd_bc, IO_TIMER1, 4, &pckbd_timer_ioh) ||
- bus_io_map(pckbd_bc, PITAUX_PORT, 1, &pckbd_pitaux_ioh))
+ if (bus_space_map(pckbd_iot, KBDATAP, 1, 0, &pckbd_data_ioh) ||
+ bus_space_map(pckbd_iot, KBSTATP, 1, 0, &pckbd_status_ioh) ||
+ bus_space_map(pckbd_iot, IO_TIMER1, 4, 0, &pckbd_timer_ioh) ||
+ bus_space_map(pckbd_iot, PITAUX_PORT, 1, 0, &pckbd_pitaux_ioh))
return 0;
- pckbd_delay_ioh = ia->ia_delayioh;
+ pckbd_delay_ioh = ia->ia_delaybah;
/* Enable interrupts and keyboard, etc. */
if (!kbc_put8042cmd(CMDBYTE)) {
goto lose;
}
for (i = 600000; i; i--)
- if ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB)
+ if ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB)
!= 0) {
KBD_DELAY;
break;
}
- if (i == 0 || bus_io_read_1(pckbd_bc, pckbd_data_ioh, 0)
+ if (i == 0 || bus_space_read_1(pckbd_iot, pckbd_data_ioh, 0)
!= KBR_RSTDONE) {
printf("pcprobe: reset error %d\n", 2);
goto lose;
struct pckbd_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- pckbd_bc = ia->ia_bc;
+ pckbd_iot = ia->ia_iot;
pckbd_ic = ia->ia_ic;
- if (bus_io_map(pckbd_bc, KBDATAP, 1, &pckbd_data_ioh) ||
- bus_io_map(pckbd_bc, KBSTATP, 1, &pckbd_status_ioh) ||
- bus_io_map(pckbd_bc, IO_TIMER1, 4, &pckbd_timer_ioh) ||
- bus_io_map(pckbd_bc, PITAUX_PORT, 1, &pckbd_pitaux_ioh))
+ if (bus_space_map(pckbd_iot, KBDATAP, 1, 0, &pckbd_data_ioh) ||
+ bus_space_map(pckbd_iot, KBSTATP, 1, 0, &pckbd_status_ioh) ||
+ bus_space_map(pckbd_iot, IO_TIMER1, 4, 0, &pckbd_timer_ioh) ||
+ bus_space_map(pckbd_iot, PITAUX_PORT, 1, 0, &pckbd_pitaux_ioh))
panic("pckbdattach couldn't map");
- pckbd_delay_ioh = ia->ia_delayioh;
+ pckbd_delay_ioh = ia->ia_delaybah;
sc->sc_ih = isa_intr_establish(pckbd_ic, ia->ia_irq, IST_EDGE,
IPL_TTY, pckbdintr, sc, sc->sc_dev.dv_xname);
u_char data;
static u_char last;
- if ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB) == 0)
+ if ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB) == 0)
return 0;
if (polling)
return 1;
do {
KBD_DELAY;
- data = bus_io_read_1(pckbd_bc, pckbd_data_ioh, 0);
+ data = bus_space_read_1(pckbd_iot, pckbd_data_ioh, 0);
switch (data) {
case KBR_ACK:
#endif
break;
}
- } while (bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB);
+ } while (bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB);
return 1;
}
do {
/* wait for byte */
- while ((bus_io_read_1(pckbd_bc, pckbd_status_ioh, 0) & KBS_DIB)
+ while ((bus_space_read_1(pckbd_iot, pckbd_status_ioh, 0) & KBS_DIB)
== 0)
KBD_DELAY;
KBD_DELAY;
- data = bus_io_read_1(pckbd_bc, pckbd_data_ioh, 0);
+ data = bus_space_read_1(pckbd_iot, pckbd_data_ioh, 0);
if (data == KBR_ACK) {
ack = 1;
}
if (!sc->sc_bellactive || sc->sc_bellpitch != pitch) {
s = splhigh();
- bus_io_write_1(pckbd_bc, pckbd_timer_ioh, TIMER_MODE,
+ bus_space_write_1(pckbd_iot, pckbd_timer_ioh, TIMER_MODE,
TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE);
- bus_io_write_1(pckbd_bc, pckbd_timer_ioh, TIMER_CNTR2,
+ bus_space_write_1(pckbd_iot, pckbd_timer_ioh, TIMER_CNTR2,
TIMER_DIV(pitch) % 256);
- bus_io_write_1(pckbd_bc, pckbd_timer_ioh, TIMER_CNTR2,
+ bus_space_write_1(pckbd_iot, pckbd_timer_ioh, TIMER_CNTR2,
TIMER_DIV(pitch) / 256);
/* enable speaker */
- bus_io_write_1(pckbd_bc, pckbd_pitaux_ioh, 0,
- bus_io_read_1(pckbd_bc, pckbd_pitaux_ioh, 0) |
+ bus_space_write_1(pckbd_iot, pckbd_pitaux_ioh, 0,
+ bus_space_read_1(pckbd_iot, pckbd_pitaux_ioh, 0) |
PIT_SPKR);
splx(s);
}
/* disable bell */
s = splhigh();
- bus_io_write_1(pckbd_bc, pckbd_pitaux_ioh, 0,
- bus_io_read_1(pckbd_bc, pckbd_pitaux_ioh, 0) & ~PIT_SPKR);
+ bus_space_write_1(pckbd_iot, pckbd_pitaux_ioh, 0,
+ bus_space_read_1(pckbd_iot, pckbd_pitaux_ioh, 0) & ~PIT_SPKR);
sc->sc_bellactive = 0;
splx(s);
}
-/* $OpenBSD: pms.c,v 1.3 1996/10/30 22:39:42 niklas Exp $ */
-/* $NetBSD: pms.c,v 1.3 1996/10/13 02:59:58 christos Exp $ */
+/* $OpenBSD: pms.c,v 1.4 1996/12/08 00:20:29 niklas Exp $ */
+/* $NetBSD: pms.c,v 1.4 1996/10/23 04:12:21 cgd Exp $ */
/*-
* Copyright (c) 1994 Charles Hannum.
int sc_x, sc_y; /* accumulated motion in the X,Y axis */
};
-bus_chipset_tag_t pms_bc;
+bus_space_tag_t pms_iot;
isa_chipset_tag_t pms_ic;
-bus_io_handle_t pms_cntrl_ioh;
+bus_space_handle_t pms_cntrl_ioh;
#define pms_status_ioh pms_cntrl_ioh
-bus_io_handle_t pms_data_ioh;
+bus_space_handle_t pms_data_ioh;
int pmsprobe __P((struct device *, void *, void *));
void pmsattach __P((struct device *, struct device *, void *));
{
u_char c;
- while ((c = bus_io_read_1(pms_bc, pms_status_ioh, 0)) & 0x03)
+ while ((c = bus_space_read_1(pms_iot, pms_status_ioh, 0) & 0x03) != 0)
if ((c & PMS_OBUF_FULL) == PMS_OBUF_FULL) {
/* XXX - delay is needed to prevent some keyboards from
wedging when the system boots */
delay(6);
- (void) bus_io_read_1(pms_bc, pms_data_ioh, 0);
+ (void) bus_space_read_1(pms_iot, pms_data_ioh, 0);
}
}
{
pms_flush();
- bus_io_write_1(pms_bc, pms_cntrl_ioh, 0, 0xd4);
+ bus_space_write_1(pms_iot, pms_cntrl_ioh, 0, 0xd4);
pms_flush();
- bus_io_write_1(pms_bc, pms_data_ioh, 0, value);
+ bus_space_write_1(pms_iot, pms_data_ioh, 0, value);
}
static __inline void
{
pms_flush();
- bus_io_write_1(pms_bc, pms_cntrl_ioh, 0, value);
+ bus_space_write_1(pms_iot, pms_cntrl_ioh, 0, value);
}
static __inline void
{
pms_flush();
- bus_io_write_1(pms_bc, pms_cntrl_ioh, 0, 0x60);
+ bus_space_write_1(pms_iot, pms_cntrl_ioh, 0, 0x60);
pms_flush();
- bus_io_write_1(pms_bc, pms_data_ioh, 0, value);
+ bus_space_write_1(pms_iot, pms_data_ioh, 0, value);
}
int
struct isa_attach_args *ia = aux;
u_char x;
- pms_bc = ia->ia_bc;
+ pms_iot = ia->ia_iot;
if (ia->ia_iobase != 0x60)
return 0;
- if (bus_io_map(pms_bc, PMS_DATA, 1, &pms_data_ioh) ||
- bus_io_map(pms_bc, PMS_CNTRL, 1, &pms_cntrl_ioh))
+ if (bus_space_map(pms_iot, PMS_DATA, 1, 0, &pms_data_ioh) ||
+ bus_space_map(pms_iot, PMS_CNTRL, 1, 0, &pms_cntrl_ioh))
return 0;
pms_dev_cmd(PMS_RESET);
pms_aux_cmd(PMS_AUX_TEST);
delay(1000);
- x = bus_io_read_1(pms_bc, pms_data_ioh, 0);
+ x = bus_space_read_1(pms_iot, pms_data_ioh, 0);
pms_pit_cmd(PMS_INT_DISABLE);
if (x & 0x04)
return 0;
struct pms_softc *sc = (void *)self;
struct isa_attach_args *ia = aux;
- pms_bc = ia->ia_bc;
+ pms_iot = ia->ia_iot;
pms_ic = ia->ia_ic;
- if (bus_io_map(pms_bc, PMS_DATA, 1, &pms_data_ioh) ||
- bus_io_map(pms_bc, PMS_CNTRL, 1, &pms_cntrl_ioh)) {
+ if (bus_space_map(pms_iot, PMS_DATA, 1, 0, &pms_data_ioh) ||
+ bus_space_map(pms_iot, PMS_CNTRL, 1, 0, &pms_cntrl_ioh)) {
printf(": can't map I/O ports!\n");
return;
}
switch (state) {
case 0:
- buttons = bus_io_read_1(pms_bc, pms_data_ioh, 0);
+ buttons = bus_space_read_1(pms_iot, pms_data_ioh, 0);
if ((buttons & 0xc0) == 0)
++state;
break;
case 1:
- dx = bus_io_read_1(pms_bc, pms_data_ioh, 0);
+ dx = bus_space_read_1(pms_iot, pms_data_ioh, 0);
/* Bounding at -127 avoids a bug in XFree86. */
dx = (dx == -128) ? -127 : dx;
++state;
break;
case 2:
- dy = bus_io_read_1(pms_bc, pms_data_ioh, 0);
+ dy = bus_space_read_1(pms_iot, pms_data_ioh, 0);
dy = (dy == -128) ? -127 : dy;
state = 0;
-/* $OpenBSD: apecs.c,v 1.6 1996/11/23 21:44:53 kstailey Exp $ */
-/* $NetBSD: apecs.c,v 1.12 1996/10/13 03:00:00 christos Exp $ */
+/* $OpenBSD: apecs.c,v 1.7 1996/12/08 00:20:30 niklas Exp $ */
+/* $NetBSD: apecs.c,v 1.13 1996/10/23 04:12:22 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <dev/pci/pcivar.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/apecsvar.h>
-#include <alpha/pci/apecs_lca.h>
#if defined(DEC_2100_A50)
#include <alpha/pci/pci_2100_a50.h>
#endif
* Can't set up SGMAP data here; can be called before malloc().
*/
- apecs_lca_bus_io_init(&acp->ac_bc, acp);
- apecs_lca_bus_mem_init(&acp->ac_bc, acp);
+ acp->ac_iot = apecs_lca_bus_io_init(acp);
+ acp->ac_memt = apecs_lca_bus_mem_init(acp);
apecs_pci_init(&acp->ac_pc, acp);
/* Turn off DMA window enables in PCI Base Reg 1. */
alpha_mb();
/* XXX SGMAP? */
+
+ /* XXX XXX BEGIN XXX XXX */
+ { /* XXX */
+ extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */
+ alpha_XXX_dmamap_or = 0x40000000; /* XXX */
+ } /* XXX */
+ /* XXX XXX END XXX XXX */
}
void
}
pba.pba_busname = "pci";
- pba.pba_bc = &acp->ac_bc;
+ pba.pba_iot = acp->ac_iot;
+ pba.pba_memt = acp->ac_memt;
pba.pba_pc = &acp->ac_pc;
pba.pba_bus = 0;
config_found(self, &pba, apecsprint);
+++ /dev/null
-/* $OpenBSD: apecs_lca.h,v 1.1 1996/10/30 22:39:47 niklas Exp $ */
-
-/*
- * Copyright (c) 1996 Niklas Hallqvist
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Niklas Hallqvist.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-void apecs_lca_bus_io_init __P((bus_chipset_tag_t, void *));
-void apecs_lca_bus_mem_init __P((bus_chipset_tag_t, void *));
-/* $OpenBSD: apecs_lca_bus_io.c,v 1.4 1996/11/12 20:29:33 niklas Exp $ */
+/* $OpenBSD: apecs_lca_bus_io.c,v 1.5 1996/12/08 00:20:32 niklas Exp $ */
/* $NetBSD: apecs_lca_bus_io.c,v 1.4 1996/08/27 16:29:23 cgd Exp $ */
/*
#include <sys/device.h>
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/lcareg.h>
-#include <alpha/pci/apecs_lca.h>
+#include <alpha/pci/lcavar.h>
#if (APECS_PCI_SIO != LCA_PCI_SIO)
#error Sparse I/O addresses do not match up?
-/* $OpenBSD: apecs_lca_bus_mem.c,v 1.4 1996/11/12 20:29:34 niklas Exp $ */
+/* $OpenBSD: apecs_lca_bus_mem.c,v 1.5 1996/12/08 00:20:33 niklas Exp $ */
/* $NetBSD: apecs_lca_bus_mem.c,v 1.5 1996/08/27 16:29:24 cgd Exp $ */
/*
#include <sys/device.h>
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/lcareg.h>
-#include <alpha/pci/apecs_lca.h>
+#include <alpha/pci/lcavar.h>
#if (APECS_PCI_SPARSE != LCA_PCI_SPARSE) || (APECS_PCI_DENSE != LCA_PCI_DENSE)
#error Memory addresses do not match up?
-/* $OpenBSD: apecsvar.h,v 1.4 1996/10/30 22:39:51 niklas Exp $ */
-/* $NetBSD: apecsvar.h,v 1.3 1996/04/12 06:08:14 cgd Exp $ */
+/* $OpenBSD: apecsvar.h,v 1.5 1996/12/08 00:20:34 niklas Exp $ */
+/* $NetBSD: apecsvar.h,v 1.4 1996/10/23 04:12:23 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
int ac_epic_pass2;
int ac_memwidth;
- struct alpha_bus_chipset ac_bc;
+ bus_space_tag_t ac_iot, ac_memt;
struct alpha_pci_chipset ac_pc;
};
void apecs_init __P((struct apecs_config *));
void apecs_pci_init __P((pci_chipset_tag_t, void *));
+
+bus_space_tag_t apecs_lca_bus_io_init __P((void *iov));
+bus_space_tag_t apecs_lca_bus_mem_init __P((void *memv));
-/* $OpenBSD: cia.c,v 1.5 1996/11/23 21:44:54 kstailey Exp $ */
-/* $NetBSD: cia.c,v 1.11 1996/10/13 03:00:03 christos Exp $ */
+/* $OpenBSD: cia.c,v 1.6 1996/12/08 00:20:34 niklas Exp $ */
+/* $NetBSD: cia.c,v 1.12 1996/10/23 04:12:24 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* Can't set up SGMAP data here; can be called before malloc().
*/
- cia_bus_io_init(&ccp->cc_bc, ccp);
- cia_bus_mem_init(&ccp->cc_bc, ccp);
+ ccp->cc_iot = cia_bus_io_init(ccp);
+ ccp->cc_memt = cia_bus_mem_init(ccp);
cia_pci_init(&ccp->cc_pc, ccp);
ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
+
+ /* XXX XXX BEGIN XXX XXX */
+ { /* XXX */
+ extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */
+ alpha_XXX_dmamap_or = 0x40000000; /* XXX */
+ } /* XXX */
+ /* XXX XXX END XXX XXX */
}
void
}
pba.pba_busname = "pci";
- pba.pba_bc = &ccp->cc_bc;
+ pba.pba_iot = ccp->cc_iot;
+ pba.pba_memt = ccp->cc_memt;
pba.pba_pc = &ccp->cc_pc;
pba.pba_bus = 0;
config_found(self, &pba, ciaprint);
-/* $OpenBSD: cia_bus_io.c,v 1.4 1996/11/12 20:29:35 niklas Exp $ */
+/* $OpenBSD: cia_bus_io.c,v 1.5 1996/12/08 00:20:35 niklas Exp $ */
/* $NetBSD: cia_bus_io.c,v 1.5 1996/08/27 16:29:25 cgd Exp $ */
/*
#include <sys/device.h>
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <alpha/pci/ciareg.h>
#include <alpha/pci/ciavar.h>
-/* $OpenBSD: cia_bus_mem.c,v 1.4 1996/11/12 20:29:36 niklas Exp $ */
+/* $OpenBSD: cia_bus_mem.c,v 1.5 1996/12/08 00:20:36 niklas Exp $ */
/* $NetBSD: cia_bus_mem.c,v 1.5 1996/08/27 16:29:26 cgd Exp $ */
/*
#include <sys/device.h>
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <alpha/pci/ciareg.h>
#include <alpha/pci/ciavar.h>
-/* $OpenBSD: ciavar.h,v 1.4 1996/10/30 22:39:58 niklas Exp $ */
-/* $NetBSD: ciavar.h,v 1.4 1996/06/10 00:03:59 cgd Exp $ */
+/* $OpenBSD: ciavar.h,v 1.5 1996/12/08 00:20:37 niklas Exp $ */
+/* $NetBSD: ciavar.h,v 1.5 1996/10/23 04:12:24 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* do their dirty work (and more!).
*/
struct cia_config {
- struct alpha_bus_chipset cc_bc;
+ bus_space_tag_t cc_iot, cc_memt;
struct alpha_pci_chipset cc_pc;
u_int32_t cc_hae_mem;
void cia_init __P((struct cia_config *));
void cia_pci_init __P((pci_chipset_tag_t, void *));
-void cia_bus_mem_init __P((bus_chipset_tag_t bc, void *memv));
-void cia_bus_io_init __P((bus_chipset_tag_t bc, void *iov));
+bus_space_tag_t cia_bus_io_init __P((void *iov));
+bus_space_tag_t cia_bus_mem_init __P((void *memv));
-/* $OpenBSD: lca.c,v 1.5 1996/11/23 21:44:54 kstailey Exp $ */
-/* $NetBSD: lca.c,v 1.10 1996/10/13 03:00:07 christos Exp $ */
+/* $OpenBSD: lca.c,v 1.6 1996/12/08 00:20:37 niklas Exp $ */
+/* $NetBSD: lca.c,v 1.11 1996/10/23 04:12:25 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <dev/pci/pcivar.h>
#include <alpha/pci/lcareg.h>
#include <alpha/pci/lcavar.h>
-#include <alpha/pci/apecs_lca.h>
#if defined(DEC_AXPPCI_33)
#include <alpha/pci/pci_axppci_33.h>
#endif
* Can't set up SGMAP data here; can be called before malloc().
*/
- apecs_lca_bus_io_init(&lcp->lc_bc, lcp);
- apecs_lca_bus_mem_init(&lcp->lc_bc, lcp);
+ lcp->lc_iot = apecs_lca_bus_io_init(lcp);
+ lcp->lc_memt = apecs_lca_bus_mem_init(lcp);
lca_pci_init(&lcp->lc_pc, lcp);
/*
/* REGVAL(LCA_IOC_W_BASE0) = 0;
REGVAL(LCA_IOC_W_BASE1) = 0; */
alpha_mb();
+
+ /* XXX XXX BEGIN XXX XXX */
+ { /* XXX */
+ extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */
+ alpha_XXX_dmamap_or = 0x40000000; /* XXX */
+ } /* XXX */
+ /* XXX XXX END XXX XXX */
}
#ifdef notdef
}
pba.pba_busname = "pci";
- pba.pba_bc = &lcp->lc_bc;
+ pba.pba_iot = lcp->lc_iot;
+ pba.pba_memt = lcp->lc_memt;
pba.pba_pc = &lcp->lc_pc;
pba.pba_bus = 0;
config_found(self, &pba, lcaprint);
-/* $OpenBSD: lcavar.h,v 1.4 1996/10/30 22:40:02 niklas Exp $ */
-/* $NetBSD: lcavar.h,v 1.3 1996/04/12 06:08:35 cgd Exp $ */
+/* $OpenBSD: lcavar.h,v 1.5 1996/12/08 00:20:38 niklas Exp $ */
+/* $NetBSD: lcavar.h,v 1.4 1996/10/23 04:12:26 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* do their dirty work (and more!).
*/
struct lca_config {
- struct alpha_bus_chipset lc_bc;
+ bus_space_tag_t lc_iot, lc_memt;
struct alpha_pci_chipset lc_pc;
};
void lca_init __P((struct lca_config *));
void lca_pci_init __P((pci_chipset_tag_t, void *));
+
+bus_space_tag_t apecs_lca_bus_io_init __P((void *));
+bus_space_tag_t apecs_lca_bus_mem_init __P((void *));
-/* $OpenBSD: pci_2100_a50.c,v 1.8 1996/11/12 20:29:37 niklas Exp $ */
-/* $NetBSD: pci_2100_a50.c,v 1.10 1996/10/13 03:00:09 christos Exp $ */
+/* $OpenBSD: pci_2100_a50.c,v 1.9 1996/12/08 00:20:39 niklas Exp $ */
+/* $NetBSD: pci_2100_a50.c,v 1.11 1996/10/23 04:12:26 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <vm/vm.h>
#include <machine/autoconf.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
pci_2100_a50_pickintr(acp)
struct apecs_config *acp;
{
- bus_chipset_tag_t bc = &acp->ac_bc;
+ bus_space_tag_t iot = acp->ac_iot;
pci_chipset_tag_t pc = &acp->ac_pc;
pcireg_t sioclass;
int sioII;
pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
#if NSIO
- sio_intr_setup(bc);
+ sio_intr_setup(iot);
set_iointr(&sio_iointr);
#else
panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
-/* $OpenBSD: pci_axppci_33.c,v 1.7 1996/11/12 20:29:38 niklas Exp $ */
-/* $NetBSD: pci_axppci_33.c,v 1.8 1996/10/13 03:00:11 christos Exp $ */
+/* $OpenBSD: pci_axppci_33.c,v 1.8 1996/12/08 00:20:40 niklas Exp $ */
+/* $NetBSD: pci_axppci_33.c,v 1.9 1996/10/23 04:12:27 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <vm/vm.h>
#include <machine/autoconf.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/isa/isavar.h>
pci_axppci_33_pickintr(lcp)
struct lca_config *lcp;
{
- bus_chipset_tag_t bc = &lcp->lc_bc;
+ bus_space_tag_t iot = lcp->lc_iot;
pci_chipset_tag_t pc = &lcp->lc_pc;
pcireg_t sioclass;
int sioII;
pc->pc_intr_disestablish = dec_axppci_33_intr_disestablish;
#if NSIO
- sio_intr_setup(bc);
+ sio_intr_setup(iot);
set_iointr(&sio_iointr);
#else
panic("pci_axppci_33_pickintr: no I/O interrupt handler (no sio)");
-/* $OpenBSD: pci_kn20aa.c,v 1.7 1996/10/30 22:40:06 niklas Exp $ */
-/* $NetBSD: pci_kn20aa.c,v 1.18 1996/10/13 03:00:12 christos Exp $ */
+/* $OpenBSD: pci_kn20aa.c,v 1.8 1996/12/08 00:20:41 niklas Exp $ */
+/* $NetBSD: pci_kn20aa.c,v 1.19 1996/10/23 04:12:28 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
struct cia_config *ccp;
{
int i;
- bus_chipset_tag_t bc = &ccp->cc_bc;
+ bus_space_tag_t iot = ccp->cc_iot;
pci_chipset_tag_t pc = &ccp->cc_pc;
for (i = 0; i < KN20AA_MAX_IRQ; i++)
pc->pc_intr_disestablish = dec_kn20aa_intr_disestablish;
#if NSIO
- sio_intr_setup(bc);
+ sio_intr_setup(iot);
#endif
set_iointr(kn20aa_iointr);
-/* $OpenBSD: pci_machdep.c,v 1.5 1996/10/30 22:40:08 niklas Exp $ */
-/* $NetBSD: pci_machdep.c,v 1.5 1996/04/12 06:08:49 cgd Exp $ */
+/* $OpenBSD: pci_machdep.c,v 1.6 1996/12/08 00:20:42 niklas Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.6 1996/10/23 04:12:29 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#endif
void
-pci_display_console(bc, pc, bus, device, function)
- bus_chipset_tag_t bc;
+pci_display_console(iot, memt, pc, bus, device, function)
+ bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
int bus, device, function;
{
pcitag_t tag;
pcireg_t id, class;
int match, nmatch;
- void (*fn) __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int));
+ void (*fn) __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
+ int, int, int));
tag = pci_make_tag(pc, bus, device, function);
id = pci_conf_read(pc, tag, PCI_ID_REG);
#endif
if (fn != NULL)
- (*fn)(bc, pc, bus, device, function);
+ (*fn)(iot, memt, pc, bus, device, function);
else
panic("pci_display_console: unconfigured device at %d/%d/%d",
bus, device, function);
-/* $OpenBSD: pci_machdep.h,v 1.5 1996/10/30 22:40:09 niklas Exp $ */
+/* $OpenBSD: pci_machdep.h,v 1.6 1996/12/08 00:20:43 niklas Exp $ */
/* $NetBSD: pci_machdep.h,v 1.4 1996/04/12 06:08:52 cgd Exp $ */
/*
#ifdef _KERNEL
void pci_display_console
- __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int));
+ __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, int, int, int));
#endif /* _KERNEL */
-/* $OpenBSD: pcivga.c,v 1.8 1996/11/23 21:44:55 kstailey Exp $ */
-/* $NetBSD: pcivga.c,v 1.11 1996/10/13 03:00:13 christos Exp $ */
+/* $OpenBSD: pcivga.c,v 1.9 1996/12/08 00:20:44 niklas Exp $ */
+/* $NetBSD: pcivga.c,v 1.12 1996/10/23 04:12:29 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
NULL, "pcivga", DV_DULL,
};
-void pcivga_getdevconfig __P((bus_chipset_tag_t, pci_chipset_tag_t,
- pcitag_t, struct pcivga_devconfig *dc));
+void pcivga_getdevconfig __P((bus_space_tag_t, bus_space_tag_t,
+ pci_chipset_tag_t, pcitag_t, struct pcivga_devconfig *dc));
struct pcivga_devconfig pcivga_console_dc;
}
void
-pcivga_getdevconfig(bc, pc, tag, dc)
- bus_chipset_tag_t bc;
+pcivga_getdevconfig(iot, memt, pc, tag, dc)
+ bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
pcitag_t tag;
struct pcivga_devconfig *dc;
{
- bus_io_handle_t ioh;
+ bus_space_handle_t ioh;
int cpos;
- dc->dc_bc = bc;
+ dc->dc_iot = iot;
+ dc->dc_memt = memt;
dc->dc_pc = pc;
dc->dc_pcitag = tag;
/* XXX deal with mapping foo */
- if (bus_mem_map(bc, 0xb8000, 0x8000, 0, &dc->dc_memh))
+ if (bus_space_map(memt, 0xb8000, 0x8000, 0, &dc->dc_memh))
panic("pcivga_getdevconfig: couldn't map memory");
- if (bus_io_map(bc, 0x3b0, 0x30, &ioh))
+ if (bus_space_map(iot, 0x3b0, 0x30, 0, &ioh))
panic("pcivga_getdevconfig: couldn't map io");
dc->dc_ioh = ioh;
dc->dc_ccol = dc->dc_crow = 0;
- bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 14);
- cpos = bus_io_read_1(bc, ioh, PCIVGA_6845_DATA) << 8;
- bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 15);
- cpos |= bus_io_read_1(bc, ioh, PCIVGA_6845_DATA);
+ bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 14);
+ cpos = bus_space_read_1(iot, ioh, PCIVGA_6845_DATA) << 8;
+ bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 15);
+ cpos |= bus_space_read_1(iot, ioh, PCIVGA_6845_DATA);
dc->dc_crow = cpos / dc->dc_ncol;
dc->dc_ccol = cpos % dc->dc_ncol;
else {
sc->sc_dc = (struct pcivga_devconfig *)
malloc(sizeof(struct pcivga_devconfig), M_DEVBUF, M_WAITOK);
- pcivga_getdevconfig(pa->pa_bc, pa->pa_pc, pa->pa_tag,
- sc->sc_dc);
+ pcivga_getdevconfig(pa->pa_iot, pa->pa_memt, pa->pa_pc,
+ pa->pa_tag, sc->sc_dc);
}
pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
}
void
-pcivga_console(bc, pc, bus, device, function)
- bus_chipset_tag_t bc;
+pcivga_console(iot, memt, pc, bus, device, function)
+ bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
int bus, device, function;
{
struct pcivga_devconfig *dcp = &pcivga_console_dc;
struct wscons_odev_spec wo;
- pcivga_getdevconfig(bc, pc,
+ pcivga_getdevconfig(iot, memt, pc,
pci_make_tag(pc, bus, device, function), dcp);
wo.wo_ef = &pcivga_emulfuncs;
int on, row, col;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_io_handle_t ioh = dc->dc_ioh;
+ bus_space_tag_t iot = dc->dc_iot;
+ bus_space_handle_t ioh = dc->dc_ioh;
int pos;
#if 0
pos = row * dc->dc_ncol + col;
- bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 14);
- bus_io_write_1(bc, ioh, PCIVGA_6845_DATA, pos >> 8);
- bus_io_write_1(bc, ioh, PCIVGA_6845_ADDR, 15);
- bus_io_write_1(bc, ioh, PCIVGA_6845_DATA, pos);
+ bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 14);
+ bus_space_write_1(iot, ioh, PCIVGA_6845_DATA, pos >> 8);
+ bus_space_write_1(iot, ioh, PCIVGA_6845_ADDR, 15);
+ bus_space_write_1(iot, ioh, PCIVGA_6845_DATA, pos);
}
void
int len;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_mem_handle_t memh = dc->dc_memh;
+ bus_space_tag_t memt = dc->dc_memt;
+ bus_space_handle_t memh = dc->dc_memh;
int i, off;
off = (row * dc->dc_ncol + col) * 2;
for (i = 0; i < len; i++, cp++, off += 2) {
- bus_mem_write_1(bc, memh, off, *cp);
- bus_mem_write_1(bc, memh, off + 1,
+ bus_space_write_1(memt, memh, off, *cp);
+ bus_space_write_1(memt, memh, off + 1,
dc->dc_so ? dc->dc_so_at : dc->dc_at);
}
}
int row, srccol, dstcol, ncols;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_mem_handle_t memh = dc->dc_memh;
- bus_mem_size_t srcoff, srcend, dstoff;
+ bus_space_tag_t memt = dc->dc_memt;
+ bus_space_handle_t memh = dc->dc_memh;
+ bus_size_t srcoff, srcend, dstoff;
/*
* YUCK. Need bus copy functions.
dstoff = (row * dc->dc_ncol + dstcol) * 2;
for (; srcoff < srcend; srcoff += 2, dstoff += 2)
- bus_mem_write_2(bc, memh, dstoff,
- bus_mem_read_2(bc, memh, srcoff));
+ bus_space_write_2(memt, memh, dstoff,
+ bus_space_read_2(memt, memh, srcoff));
}
void
int row, startcol, ncols;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_mem_handle_t memh = dc->dc_memh;
- bus_mem_size_t off, endoff;
+ bus_space_tag_t memt = dc->dc_memt;
+ bus_space_handle_t memh = dc->dc_memh;
+ bus_size_t off, endoff;
u_int16_t val;
/*
val = (dc->dc_at << 8) | ' ';
for (; off < endoff; off += 2)
- bus_mem_write_2(bc, memh, off, val);
+ bus_space_write_2(memt, memh, off, val);
}
void
int srcrow, dstrow, nrows;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_mem_handle_t memh = dc->dc_memh;
- bus_mem_size_t srcoff, srcend, dstoff;
+ bus_space_tag_t memt = dc->dc_memt;
+ bus_space_handle_t memh = dc->dc_memh;
+ bus_size_t srcoff, srcend, dstoff;
/*
* YUCK. Need bus copy functions.
dstoff = (dstrow * dc->dc_ncol + 0) * 2;
for (; srcoff < srcend; srcoff += 2, dstoff += 2)
- bus_mem_write_2(bc, memh, dstoff,
- bus_mem_read_2(bc, memh, srcoff));
+ bus_space_write_2(memt, memh, dstoff,
+ bus_space_read_2(memt, memh, srcoff));
}
void
int startrow, nrows;
{
struct pcivga_devconfig *dc = id;
- bus_chipset_tag_t bc = dc->dc_bc;
- bus_mem_handle_t memh = dc->dc_memh;
- bus_mem_size_t off, endoff;
+ bus_space_tag_t memt = dc->dc_memt;
+ bus_space_handle_t memh = dc->dc_memh;
+ bus_size_t off, endoff;
u_int16_t val;
/*
val = (dc->dc_at << 8) | ' ';
for (; off < endoff; off += 2)
- bus_mem_write_2(bc, memh, off, val);
+ bus_space_write_2(memt, memh, off, val);
}
-/* $OpenBSD: pcivgavar.h,v 1.5 1996/10/30 22:40:11 niklas Exp $ */
-/* $NetBSD: pcivgavar.h,v 1.5 1996/04/12 06:08:58 cgd Exp $ */
+/* $OpenBSD: pcivgavar.h,v 1.6 1996/12/08 00:20:44 niklas Exp $ */
+/* $NetBSD: pcivgavar.h,v 1.6 1996/10/23 04:12:30 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
*/
struct pcivga_devconfig {
- bus_chipset_tag_t dc_bc;
+ bus_space_tag_t dc_iot;
+ bus_space_tag_t dc_memt;
pci_chipset_tag_t dc_pc;
pcitag_t dc_pcitag; /* PCI tag */
- bus_io_handle_t dc_ioh;
- bus_mem_handle_t dc_memh;
+ bus_space_handle_t dc_ioh, dc_memh;
int dc_ncol, dc_nrow; /* screen width & height */
int dc_ccol, dc_crow; /* current cursor position */
(PCI_CLASS(class) == PCI_CLASS_PREHISTORIC && \
PCI_SUBCLASS(class) == PCI_SUBCLASS_PREHISTORIC_VGA)) ? 1 : 0)
-void pcivga_console __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int,
- int));
+void pcivga_console __P((bus_space_tag_t, bus_space_tag_t,
+ pci_chipset_tag_t, int, int, int));
-/* $OpenBSD: pcs_bus_io_common.c,v 1.3 1996/10/30 22:40:12 niklas Exp $ */
-/* $NetBSD: pcs_bus_io_common.c,v 1.8 1996/10/13 03:00:15 christos Exp $ */
+/* $OpenBSD: pcs_bus_io_common.c,v 1.4 1996/12/08 00:20:45 niklas Exp $ */
+/* $NetBSD: pcs_bus_io_common.c,v 1.9 1996/10/23 04:12:31 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#define __C(A,B) __CONCAT(A,B)
#define __S(S) __STRING(S)
-int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *));
-void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t,
- bus_io_size_t));
-int __C(CHIP,_io_subregion) __P((void *, bus_io_handle_t,
- bus_io_size_t, bus_io_size_t, bus_io_handle_t *));
-u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t,
- bus_io_size_t));
-void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int8_t *, bus_io_size_t));
-void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int16_t *, bus_io_size_t));
-void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int32_t *, bus_io_size_t));
-void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int64_t *, bus_io_size_t));
-void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int8_t));
-void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int16_t));
-void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int32_t));
-void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int64_t));
-void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int8_t *, bus_io_size_t));
-void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int16_t *, bus_io_size_t));
-void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int32_t *, bus_io_size_t));
-void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int64_t *, bus_io_size_t));
-
-void
-__C(CHIP,_bus_io_init)(bc, iov)
- bus_chipset_tag_t bc;
+/* mapping/unmapping */
+int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t,
+ bus_size_t));
+int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, bus_space_handle_t *));
+
+/* allocation/deallocation */
+int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t,
+ bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
+ bus_space_handle_t *));
+void __C(CHIP,_io_free) __P((void *, bus_space_handle_t,
+ bus_size_t));
+
+/* read (single) */
+u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t,
+ bus_size_t));
+
+/* read multiple */
+void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* read region */
+void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* write (single) */
+void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t));
+void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t));
+void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t));
+void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t));
+
+/* write multiple */
+void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* write region */
+void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* barrier */
+void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, int));
+
+static struct alpha_bus_space __C(CHIP,_io_space) = {
+ /* cookie */
+ NULL,
+
+ /* mapping/unmapping */
+ __C(CHIP,_io_map),
+ __C(CHIP,_io_unmap),
+ __C(CHIP,_io_subregion),
+
+ /* allocation/deallocation */
+ __C(CHIP,_io_alloc),
+ __C(CHIP,_io_free),
+
+ /* read (single) */
+ __C(CHIP,_io_read_1),
+ __C(CHIP,_io_read_2),
+ __C(CHIP,_io_read_4),
+ __C(CHIP,_io_read_8),
+
+ /* read multi */
+ __C(CHIP,_io_read_multi_1),
+ __C(CHIP,_io_read_multi_2),
+ __C(CHIP,_io_read_multi_4),
+ __C(CHIP,_io_read_multi_8),
+
+ /* read region */
+ __C(CHIP,_io_read_region_1),
+ __C(CHIP,_io_read_region_2),
+ __C(CHIP,_io_read_region_4),
+ __C(CHIP,_io_read_region_8),
+
+ /* write (single) */
+ __C(CHIP,_io_write_1),
+ __C(CHIP,_io_write_2),
+ __C(CHIP,_io_write_4),
+ __C(CHIP,_io_write_8),
+
+ /* write multi */
+ __C(CHIP,_io_write_multi_1),
+ __C(CHIP,_io_write_multi_2),
+ __C(CHIP,_io_write_multi_4),
+ __C(CHIP,_io_write_multi_8),
+
+ /* write region */
+ __C(CHIP,_io_write_region_1),
+ __C(CHIP,_io_write_region_2),
+ __C(CHIP,_io_write_region_4),
+ __C(CHIP,_io_write_region_8),
+
+ /* set multi */
+ /* XXX IMPLEMENT */
+
+ /* set region */
+ /* XXX IMPLEMENT */
+
+ /* copy */
+ /* XXX IMPLEMENT */
+
+ /* barrier */
+ __C(CHIP,_io_barrier),
+};
+
+bus_space_tag_t
+__C(CHIP,_bus_io_init)(iov)
void *iov;
{
+ bus_space_tag_t h = &__C(CHIP,_io_space);;
- bc->bc_i_v = iov;
-
- bc->bc_i_map = __C(CHIP,_io_map);
- bc->bc_i_unmap = __C(CHIP,_io_unmap);
- bc->bc_i_subregion = __C(CHIP,_io_subregion);
-
- bc->bc_ir1 = __C(CHIP,_io_read_1);
- bc->bc_ir2 = __C(CHIP,_io_read_2);
- bc->bc_ir4 = __C(CHIP,_io_read_4);
- bc->bc_ir8 = __C(CHIP,_io_read_8);
-
- bc->bc_irm1 = __C(CHIP,_io_read_multi_1);
- bc->bc_irm2 = __C(CHIP,_io_read_multi_2);
- bc->bc_irm4 = __C(CHIP,_io_read_multi_4);
- bc->bc_irm8 = __C(CHIP,_io_read_multi_8);
-
- bc->bc_iw1 = __C(CHIP,_io_write_1);
- bc->bc_iw2 = __C(CHIP,_io_write_2);
- bc->bc_iw4 = __C(CHIP,_io_write_4);
- bc->bc_iw8 = __C(CHIP,_io_write_8);
-
- bc->bc_iwm1 = __C(CHIP,_io_write_multi_1);
- bc->bc_iwm2 = __C(CHIP,_io_write_multi_2);
- bc->bc_iwm4 = __C(CHIP,_io_write_multi_4);
- bc->bc_iwm8 = __C(CHIP,_io_write_multi_8);
+ h->abs_cookie = iov;
+ return (h);
}
int
-__C(CHIP,_io_map)(v, ioaddr, iosize, iohp)
+__C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp)
void *v;
- bus_io_addr_t ioaddr;
- bus_io_size_t iosize;
- bus_io_handle_t *iohp;
+ bus_addr_t ioaddr;
+ bus_size_t iosize;
+ int cacheable;
+ bus_space_handle_t *iohp;
{
#ifdef CHIP_IO_W1_START
__S(__C(CHIP,_io_map)), CHIP_IO_W2_START(v),
CHIP_IO_W2_END(v)-1);
#endif
- panic("%s: don't know how to map %lx non-cacheable\n",
+ panic("%s: don't know how to map %lx non-cacheable",
__S(__C(CHIP,_io_map)), ioaddr);
}
+ /* XXX XXX XXX XXX XXX XXX */
return (0);
}
void
__C(CHIP,_io_unmap)(v, ioh, iosize)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t iosize;
+ bus_space_handle_t ioh;
+ bus_size_t iosize;
{
/* XXX nothing to do. */
+ /* XXX XXX XXX XXX XXX XXX */
}
int
__C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
void *v;
- bus_io_handle_t ioh, *nioh;
- bus_io_size_t offset, size;
+ bus_space_handle_t ioh, *nioh;
+ bus_size_t offset, size;
{
*nioh = ioh + offset;
return (0);
}
+int
+__C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable,
+ addrp, bshp)
+ void *v;
+ bus_addr_t rstart, rend, *addrp;
+ bus_size_t size, align, boundary;
+ int cacheable;
+ bus_space_handle_t *bshp;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("%s not implemented", __S(__C(CHIP,_io_alloc)));
+}
+
+void
+__C(CHIP,_io_free)(v, bsh, size)
+ void *v;
+ bus_space_handle_t bsh;
+ bus_size_t size;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("%s not implemented", __S(__C(CHIP,_io_free)));
+}
+
u_int8_t
__C(CHIP,_io_read_1)(v, ioh, off)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, val;
register u_int8_t rval;
register int offset;
u_int16_t
__C(CHIP,_io_read_2)(v, ioh, off)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, val;
register u_int16_t rval;
register int offset;
u_int32_t
__C(CHIP,_io_read_4)(v, ioh, off)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, val;
register u_int32_t rval;
register int offset;
u_int64_t
__C(CHIP,_io_read_8)(v, ioh, off)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
{
/* XXX XXX XXX */
- panic("%s not implemented\n", __S(__C(CHIP,_io_read_8)));
+ panic("%s not implemented", __S(__C(CHIP,_io_read_8)));
}
-void
-__C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int8_t *addr;
-{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, val;
- register int offset;
-
- alpha_mb();
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
- val = *port;
- *addr++ = ((val) >> (8 * offset)) & 0xff;
- off++;
- }
+#define CHIP_io_read_multi_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
+ BUS_BARRIER_READ); \
+ *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
+ } \
}
-
-void
-__C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int16_t *addr;
-{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, val;
- register int offset;
-
- alpha_mb();
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
- val = *port;
- *addr++ = ((val) >> (8 * offset)) & 0xffff;
- off++;
- }
-}
-
-void
-__C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int32_t *addr;
-{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, val;
- register int offset;
-
- alpha_mb();
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
- val = *port;
-#if 0
- *addr++ = ((val) >> (8 * offset)) & 0xffffffff;
-#else
- *addr++ = val;
-#endif
- off++;
- }
-}
-
-void
-__C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int64_t *addr;
-{
-
- /* XXX XXX XXX */
- panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8)));
+CHIP_io_read_multi_N(1,u_int8_t)
+CHIP_io_read_multi_N(2,u_int16_t)
+CHIP_io_read_multi_N(4,u_int32_t)
+CHIP_io_read_multi_N(8,u_int64_t)
+
+#define CHIP_io_read_region_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
+ o += sizeof *a; \
+ } \
}
+CHIP_io_read_region_N(1,u_int8_t)
+CHIP_io_read_region_N(2,u_int16_t)
+CHIP_io_read_region_N(4,u_int32_t)
+CHIP_io_read_region_N(8,u_int64_t)
void
__C(CHIP,_io_write_1)(v, ioh, off, val)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
u_int8_t val;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_io_write_2)(v, ioh, off, val)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
u_int16_t val;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_io_write_4)(v, ioh, off, val)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
u_int32_t val;
{
- register bus_io_handle_t tmpioh;
+ register bus_space_handle_t tmpioh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_io_write_8)(v, ioh, off, val)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
+ bus_space_handle_t ioh;
+ bus_size_t off;
u_int64_t val;
{
/* XXX XXX XXX */
- panic("%s not implemented\n", __S(__C(CHIP,_io_write_8)));
+ panic("%s not implemented", __S(__C(CHIP,_io_write_8)));
alpha_mb();
}
-void
-__C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int8_t *addr;
-{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, nval;
- register int offset;
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- nval = (*addr++) << (8 * offset);
- port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
- *port = nval;
- off++;
- }
- alpha_mb();
+#define CHIP_io_write_multi_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
+ __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
+ BUS_BARRIER_WRITE); \
+ } \
}
-
-void
-__C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int16_t *addr;
-{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, nval;
- register int offset;
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- nval = (*addr++) << (8 * offset);
- port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
- *port = nval;
- off++;
- }
- alpha_mb();
+CHIP_io_write_multi_N(1,u_int8_t)
+CHIP_io_write_multi_N(2,u_int16_t)
+CHIP_io_write_multi_N(4,u_int32_t)
+CHIP_io_write_multi_N(8,u_int64_t)
+
+#define CHIP_io_write_region_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
+ o += sizeof *a; \
+ } \
}
+CHIP_io_write_region_N(1,u_int8_t)
+CHIP_io_write_region_N(2,u_int16_t)
+CHIP_io_write_region_N(4,u_int32_t)
+CHIP_io_write_region_N(8,u_int64_t)
void
-__C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count)
+__C(CHIP,_io_barrier)(v, h, o, l, f)
void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int32_t *addr;
+ bus_space_handle_t h;
+ bus_size_t o, l;
+ int f;
{
- register bus_io_handle_t tmpioh;
- register u_int32_t *port, nval;
- register int offset;
-
- while (count--) {
- tmpioh = ioh + off;
- offset = tmpioh & 3;
- nval = (*addr++) /*<< (8 * offset)*/;
- port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
- *port = nval;
- off++;
- }
- alpha_mb();
-}
-void
-__C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int64_t *addr;
-{
-
- /* XXX XXX XXX */
- panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8)));
+ if ((f & BUS_BARRIER_READ) != 0)
+ alpha_mb();
+ else if ((f & BUS_BARRIER_WRITE) != 0)
+ alpha_wmb();
}
-/* $OpenBSD: pcs_bus_mem_common.c,v 1.3 1996/10/30 22:40:13 niklas Exp $ */
-/* $NetBSD: pcs_bus_mem_common.c,v 1.9 1996/10/13 03:00:17 christos Exp $ */
+/* $OpenBSD: pcs_bus_mem_common.c,v 1.4 1996/12/08 00:20:46 niklas Exp $ */
+/* $NetBSD: pcs_bus_mem_common.c,v 1.10 1996/10/23 04:12:32 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#define __C(A,B) __CONCAT(A,B)
#define __S(S) __STRING(S)
-int __C(CHIP,_mem_map) __P((void *, bus_mem_addr_t, bus_mem_size_t,
- int, bus_mem_handle_t *));
-void __C(CHIP,_mem_unmap) __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-int __C(CHIP,_mem_subregion) __P((void *, bus_mem_handle_t,
- bus_mem_size_t, bus_mem_size_t, bus_mem_handle_t *));
-u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-void __C(CHIP,_mem_write_1) __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int8_t));
-void __C(CHIP,_mem_write_2) __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int16_t));
-void __C(CHIP,_mem_write_4) __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int32_t));
-void __C(CHIP,_mem_write_8) __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int64_t));
-
-/* XXX DOES NOT BELONG */
-vm_offset_t __C(CHIP,_XXX_dmamap) __P((void *));
-
-void
-__C(CHIP,_bus_mem_init)(bc, memv)
- bus_chipset_tag_t bc;
- void *memv;
+/* mapping/unmapping */
+int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t,
+ bus_size_t));
+int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, bus_space_handle_t *));
+
+/* allocation/deallocation */
+int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t,
+ bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
+ bus_space_handle_t *));
+void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t,
+ bus_size_t));
+
+/* read (single) */
+u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t,
+ bus_size_t));
+u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t,
+ bus_size_t));
+
+/* read multiple */
+void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* read region */
+void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* write (single) */
+void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t));
+void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t));
+void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t));
+void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t));
+
+/* write multiple */
+void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* write region */
+void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* barrier */
+void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, int));
+
+static struct alpha_bus_space __C(CHIP,_mem_space) = {
+ /* cookie */
+ NULL,
+
+ /* mapping/unmapping */
+ __C(CHIP,_mem_map),
+ __C(CHIP,_mem_unmap),
+ __C(CHIP,_mem_subregion),
+
+ /* allocation/deallocation */
+ __C(CHIP,_mem_alloc),
+ __C(CHIP,_mem_free),
+
+ /* read (single) */
+ __C(CHIP,_mem_read_1),
+ __C(CHIP,_mem_read_2),
+ __C(CHIP,_mem_read_4),
+ __C(CHIP,_mem_read_8),
+
+ /* read multi */
+ __C(CHIP,_mem_read_multi_1),
+ __C(CHIP,_mem_read_multi_2),
+ __C(CHIP,_mem_read_multi_4),
+ __C(CHIP,_mem_read_multi_8),
+
+ /* read region */
+ __C(CHIP,_mem_read_region_1),
+ __C(CHIP,_mem_read_region_2),
+ __C(CHIP,_mem_read_region_4),
+ __C(CHIP,_mem_read_region_8),
+
+ /* write (single) */
+ __C(CHIP,_mem_write_1),
+ __C(CHIP,_mem_write_2),
+ __C(CHIP,_mem_write_4),
+ __C(CHIP,_mem_write_8),
+
+ /* write multi */
+ __C(CHIP,_mem_write_multi_1),
+ __C(CHIP,_mem_write_multi_2),
+ __C(CHIP,_mem_write_multi_4),
+ __C(CHIP,_mem_write_multi_8),
+
+ /* write region */
+ __C(CHIP,_mem_write_region_1),
+ __C(CHIP,_mem_write_region_2),
+ __C(CHIP,_mem_write_region_4),
+ __C(CHIP,_mem_write_region_8),
+
+ /* set multi */
+ /* XXX IMPLEMENT */
+
+ /* set region */
+ /* XXX IMPLEMENT */
+
+ /* copy */
+ /* XXX IMPLEMENT */
+
+ /* barrier */
+ __C(CHIP,_mem_barrier),
+};
+
+bus_space_tag_t
+__C(CHIP,_bus_mem_init)(iov)
+ void *iov;
{
+ bus_space_tag_t h = &__C(CHIP,_mem_space);;
- bc->bc_m_v = memv;
-
- bc->bc_m_map = __C(CHIP,_mem_map);
- bc->bc_m_unmap = __C(CHIP,_mem_unmap);
- bc->bc_m_subregion = __C(CHIP,_mem_subregion);
-
- bc->bc_mr1 = __C(CHIP,_mem_read_1);
- bc->bc_mr2 = __C(CHIP,_mem_read_2);
- bc->bc_mr4 = __C(CHIP,_mem_read_4);
- bc->bc_mr8 = __C(CHIP,_mem_read_8);
-
- bc->bc_mw1 = __C(CHIP,_mem_write_1);
- bc->bc_mw2 = __C(CHIP,_mem_write_2);
- bc->bc_mw4 = __C(CHIP,_mem_write_4);
- bc->bc_mw8 = __C(CHIP,_mem_write_8);
-
- /* XXX DOES NOT BELONG */
- bc->bc_XXX_dmamap = __C(CHIP,_XXX_dmamap);
+ h->abs_cookie = iov;
+ return (h);
}
int
__C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp)
void *v;
- bus_mem_addr_t memaddr;
- bus_mem_size_t memsize;
+ bus_addr_t memaddr;
+ bus_size_t memsize;
int cacheable;
- bus_mem_handle_t *memhp;
+ bus_space_handle_t *memhp;
{
if (cacheable) {
__S(__C(CHIP,_mem_map)), CHIP_D_MEM_W1_START(v),
CHIP_D_MEM_W1_END(v)-1);
#endif
- panic("%s: don't know how to map %lx cacheable\n",
+ panic("%s: don't know how to map %lx cacheable",
__S(__C(CHIP,_mem_map)), memaddr);
}
} else {
__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W3_START(v),
CHIP_S_MEM_W3_END(v)-1);
#endif
- panic("%s: don't know how to map %lx non-cacheable\n",
+ panic("%s: don't know how to map %lx non-cacheable",
__S(__C(CHIP,_mem_map)), memaddr);
}
}
+ /* XXX XXX XXX XXX XXX XXX */
return (0);
}
void
__C(CHIP,_mem_unmap)(v, memh, memsize)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t memsize;
+ bus_space_handle_t memh;
+ bus_size_t memsize;
{
/* XXX nothing to do. */
+ /* XXX XXX XXX XXX XXX XXX */
}
int
__C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh)
void *v;
- bus_mem_handle_t memh, *nmemh;
- bus_mem_size_t offset, size;
+ bus_space_handle_t memh, *nmemh;
+ bus_size_t offset, size;
{
*nmemh = memh + offset;
return (0);
}
+int
+__C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, cacheable,
+ addrp, bshp)
+ void *v;
+ bus_addr_t rstart, rend, *addrp;
+ bus_size_t size, align, boundary;
+ int cacheable;
+ bus_space_handle_t *bshp;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("%s not implemented", __S(__C(CHIP,_mem_alloc)));
+}
+
+void
+__C(CHIP,_mem_free)(v, bsh, size)
+ void *v;
+ bus_space_handle_t bsh;
+ bus_size_t size;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("%s not implemented", __S(__C(CHIP,_mem_free)));
+}
+
u_int8_t
__C(CHIP,_mem_read_1)(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, val;
register u_int8_t rval;
register int offset;
u_int16_t
__C(CHIP,_mem_read_2)(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, val;
register u_int16_t rval;
register int offset;
u_int32_t
__C(CHIP,_mem_read_4)(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, val;
register u_int32_t rval;
register int offset;
u_int64_t
__C(CHIP,_mem_read_8)(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
alpha_mb();
return (*(u_int64_t *)(memh + off));
/* XXX XXX XXX */
- panic("%s not implemented\n", __S(__C(CHIP,_mem_read_8)));
+ panic("%s not implemented", __S(__C(CHIP,_mem_read_8)));
}
+#define CHIP_mem_read_multi_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
+ BUS_BARRIER_READ); \
+ *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
+ } \
+}
+CHIP_mem_read_multi_N(1,u_int8_t)
+CHIP_mem_read_multi_N(2,u_int16_t)
+CHIP_mem_read_multi_N(4,u_int32_t)
+CHIP_mem_read_multi_N(8,u_int64_t)
+
+#define CHIP_mem_read_region_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
+ o += sizeof *a; \
+ } \
+}
+CHIP_mem_read_region_N(1,u_int8_t)
+CHIP_mem_read_region_N(2,u_int16_t)
+CHIP_mem_read_region_N(4,u_int32_t)
+CHIP_mem_read_region_N(8,u_int64_t)
+
void
__C(CHIP,_mem_write_1)(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int8_t val;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_mem_write_2)(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int16_t val;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_mem_write_4)(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int32_t val;
{
- register bus_mem_handle_t tmpmemh;
+ register bus_space_handle_t tmpmemh;
register u_int32_t *port, nval;
register int offset;
void
__C(CHIP,_mem_write_8)(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int64_t val;
{
(*(u_int64_t *)(memh + off)) = val;
else {
/* XXX XXX XXX */
- panic("%s not implemented\n",
+ panic("%s not implemented",
__S(__C(CHIP,_mem_write_8)));
}
alpha_mb();
}
-vm_offset_t
-__C(CHIP,_XXX_dmamap)(addr)
- void *addr;
+#define CHIP_mem_write_multi_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
+ __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
+ BUS_BARRIER_WRITE); \
+ } \
+}
+CHIP_mem_write_multi_N(1,u_int8_t)
+CHIP_mem_write_multi_N(2,u_int16_t)
+CHIP_mem_write_multi_N(4,u_int32_t)
+CHIP_mem_write_multi_N(8,u_int64_t)
+
+#define CHIP_mem_write_region_N(BYTES,TYPE) \
+void \
+__C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
+ o += sizeof *a; \
+ } \
+}
+CHIP_mem_write_region_N(1,u_int8_t)
+CHIP_mem_write_region_N(2,u_int16_t)
+CHIP_mem_write_region_N(4,u_int32_t)
+CHIP_mem_write_region_N(8,u_int64_t)
+
+void
+__C(CHIP,_mem_barrier)(v, h, o, l, f)
+ void *v;
+ bus_space_handle_t h;
+ bus_size_t o, l;
+ int f;
{
- return (vtophys((vm_offset_t)addr) | 0x40000000);
+ if ((f & BUS_BARRIER_READ) != 0)
+ alpha_mb();
+ else if ((f & BUS_BARRIER_WRITE) != 0)
+ alpha_wmb();
}
-/* $OpenBSD: sio.c,v 1.7 1996/11/23 21:44:56 kstailey Exp $ */
-/* $NetBSD: sio.c,v 1.11 1996/10/13 03:00:18 christos Exp $ */
+/* $OpenBSD: sio.c,v 1.8 1996/12/08 00:20:48 niklas Exp $ */
+/* $NetBSD: sio.c,v 1.12 1996/10/23 04:12:33 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <sys/device.h>
#include <machine/intr.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isavar.h>
#include <dev/eisa/eisavar.h>
ec.ec_intr_disestablish = sio_intr_disestablish;
sa.sa_eba.eba_busname = "eisa";
- sa.sa_eba.eba_bc = pa->pa_bc;
+ sa.sa_eba.eba_iot = pa->pa_iot;
+ sa.sa_eba.eba_memt = pa->pa_memt;
sa.sa_eba.eba_ec = &ec;
config_found(self, &sa.sa_eba, sioprint);
}
ic.ic_intr_disestablish = sio_intr_disestablish;
sa.sa_iba.iba_busname = "isa";
- sa.sa_iba.iba_bc = pa->pa_bc;
+ sa.sa_iba.iba_iot = pa->pa_iot;
+ sa.sa_iba.iba_memt = pa->pa_memt;
sa.sa_iba.iba_ic = ⁣
config_found(self, &sa.sa_iba, sioprint);
}
-/* $OpenBSD: sio_pic.c,v 1.7 1996/11/12 20:29:39 niklas Exp $ */
-/* $NetBSD: sio_pic.c,v 1.13 1996/10/13 03:00:20 christos Exp $ */
+/* $OpenBSD: sio_pic.c,v 1.8 1996/12/08 00:20:49 niklas Exp $ */
+/* $NetBSD: sio_pic.c,v 1.14 1996/10/23 04:12:33 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <sys/syslog.h>
#include <machine/intr.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
*/
static void sio_strayintr __P((int));
-bus_chipset_tag_t sio_bc;
-bus_io_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr;
+bus_space_tag_t sio_iot;
+bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr;
/*
* Interrupt handler chains. sio_intr_establish() inserts a handler into
icu = irq / 8;
bit = irq % 8;
- ocw1[0] = bus_io_read_1(sio_bc, sio_ioh_icu1, 1);
- ocw1[1] = bus_io_read_1(sio_bc, sio_ioh_icu2, 1);
- elcr[0] = bus_io_read_1(sio_bc, sio_ioh_elcr, 0); /* XXX */
- elcr[1] = bus_io_read_1(sio_bc, sio_ioh_elcr, 1); /* XXX */
+ ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
+ ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
+ elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */
+ elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */
/*
* interrupt enable: set bit to mask (disable) interrupt.
}
#endif
- bus_io_write_1(sio_bc, sio_ioh_icu1, 1, ocw1[0]);
- bus_io_write_1(sio_bc, sio_ioh_icu2, 1, ocw1[1]);
- bus_io_write_1(sio_bc, sio_ioh_elcr, 0, elcr[0]); /* XXX */
- bus_io_write_1(sio_bc, sio_ioh_elcr, 1, elcr[1]); /* XXX */
+ bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
+ bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
+ bus_space_write_1(sio_iot, sio_ioh_elcr, 0, elcr[0]); /* XXX */
+ bus_space_write_1(sio_iot, sio_ioh_elcr, 1, elcr[1]); /* XXX */
}
void
-sio_intr_setup(bc)
- bus_chipset_tag_t bc;
+sio_intr_setup(iot)
+ bus_space_tag_t iot;
{
int i;
- sio_bc = bc;
+ sio_iot = iot;
- if (bus_io_map(sio_bc, IO_ICU1, IO_ICUSIZE, &sio_ioh_icu1) ||
- bus_io_map(sio_bc, IO_ICU2, IO_ICUSIZE, &sio_ioh_icu2) ||
- bus_io_map(sio_bc, 0x4d0, 2, &sio_ioh_elcr))
+ if (bus_space_map(sio_iot, IO_ICU1, IO_ICUSIZE, 0, &sio_ioh_icu1) ||
+ bus_space_map(sio_iot, IO_ICU2, IO_ICUSIZE, 0, &sio_ioh_icu2) ||
+ bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr))
panic("sio_intr_setup: can't map I/O ports");
#ifdef BROKEN_PROM_CONSOLE
/*
* Remember the initial values, because the prom is stupid.
*/
- initial_ocw1[0] = bus_io_read_1(sio_bc, sio_ioh_icu1, 1);
- initial_ocw1[1] = bus_io_read_1(sio_bc, sio_ioh_icu2, 1);
- initial_elcr[0] = bus_io_read_1(sio_bc, sio_ioh_elcr, 0); /* XXX */
- initial_elcr[1] = bus_io_read_1(sio_bc, sio_ioh_elcr, 1); /* XXX */
+ initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
+ initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
+ initial_elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */
+ initial_elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */
#if 0
printf("initial_ocw1[0] = 0x%x\n", initial_ocw1[0]);
printf("initial_ocw1[1] = 0x%x\n", initial_ocw1[1]);
* by the interrupt handler.
*/
if (irq > 7)
- bus_io_write_1(sio_bc,
+ bus_space_write_1(sio_iot,
sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */
- bus_io_write_1(sio_bc,
+ bus_space_write_1(sio_iot,
sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); /* XXX */
}
-/* $OpenBSD: siovar.h,v 1.4 1996/10/30 22:40:17 niklas Exp $ */
-/* $NetBSD: siovar.h,v 1.4 1996/07/14 04:08:42 cgd Exp $ */
+/* $OpenBSD: siovar.h,v 1.5 1996/12/08 00:20:50 niklas Exp $ */
+/* $NetBSD: siovar.h,v 1.5 1996/10/23 04:12:34 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* rights to redistribute these changes.
*/
-void sio_intr_setup __P((bus_chipset_tag_t));
+void sio_intr_setup __P((bus_space_tag_t));
void sio_iointr __P((void *framep, unsigned long vec));
const char *sio_intr_string __P((void *, int));
-/* $OpenBSD: tga.c,v 1.7 1996/11/23 21:44:56 kstailey Exp $ */
-/* $NetBSD: tga.c,v 1.10 1996/10/13 03:00:22 christos Exp $ */
+/* $OpenBSD: tga.c,v 1.8 1996/12/08 00:20:51 niklas Exp $ */
+/* $NetBSD: tga.c,v 1.11 1996/10/23 04:12:35 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
#include <sys/conf.h>
#include <sys/ioctl.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/pcireg.h>
int tga_identify __P((tga_reg_t *));
const struct tga_conf *tga_getconf __P((int));
-void tga_getdevconfig __P((bus_chipset_tag_t bc, pci_chipset_tag_t pc,
+void tga_getdevconfig __P((bus_space_tag_t memt, pci_chipset_tag_t pc,
pcitag_t tag, struct tga_devconfig *dc));
struct tga_devconfig tga_console_dc;
}
void
-tga_getdevconfig(bc, pc, tag, dc)
- bus_chipset_tag_t bc;
+tga_getdevconfig(memt, pc, tag, dc)
+ bus_space_tag_t memt;
pci_chipset_tag_t pc;
pcitag_t tag;
struct tga_devconfig *dc;
const struct tga_ramdac_conf *tgar;
struct raster *rap;
struct rcons *rcp;
- bus_mem_size_t pcisize;
+ bus_size_t pcisize;
int i, cacheable;
- dc->dc_bc = bc;
+ dc->dc_memt = memt;
dc->dc_pc = pc;
dc->dc_pcitag = tag;
panic("tga_getdevconfig: memory not cacheable?");
/* XXX XXX XXX */
- if (bus_mem_map(bc, dc->dc_pcipaddr, pcisize, 1, &dc->dc_vaddr))
+ if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 1, &dc->dc_vaddr))
return;
dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */
else {
sc->sc_dc = (struct tga_devconfig *)
malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK);
- tga_getdevconfig(pa->pa_bc, pa->pa_pc, pa->pa_tag, sc->sc_dc);
+ tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc);
}
if (sc->sc_dc->dc_vaddr == NULL) {
printf(": couldn't map memory space; punt!\n");
}
void
-tga_console(bc, pc, bus, device, function)
- bus_chipset_tag_t bc;
+tga_console(iot, memt, pc, bus, device, function)
+ bus_space_tag_t iot, memt;
pci_chipset_tag_t pc;
int bus, device, function;
{
struct tga_devconfig *dcp = &tga_console_dc;
struct wscons_odev_spec wo;
- tga_getdevconfig(bc, pc, pci_make_tag(pc, bus, device, function), dcp);
+ tga_getdevconfig(memt, pc, pci_make_tag(pc, bus, device, function), dcp);
/* sanity checks */
if (dcp->dc_vaddr == NULL)
-/* $OpenBSD: tgavar.h,v 1.5 1996/10/30 22:40:22 niklas Exp $ */
-/* $NetBSD: tgavar.h,v 1.5 1996/04/12 06:09:21 cgd Exp $ */
+/* $OpenBSD: tgavar.h,v 1.6 1996/12/08 00:20:52 niklas Exp $ */
+/* $NetBSD: tgavar.h,v 1.6 1996/10/23 04:12:36 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
};
struct tga_devconfig {
- bus_chipset_tag_t dc_bc;
+ bus_space_tag_t dc_memt;
pci_chipset_tag_t dc_pc;
pcitag_t dc_pcitag; /* PCI tag */
- bus_mem_addr_t dc_pcipaddr; /* PCI phys addr. */
+ bus_addr_t dc_pcipaddr; /* PCI phys addr. */
tga_reg_t *dc_regs; /* registers; XXX: need aliases */
((PCI_VENDOR(id) == PCI_VENDOR_DEC && \
PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) ? 10 : 0)
-void tga_console __P((bus_chipset_tag_t, pci_chipset_tag_t, int, int, int));
+void tga_console __P((bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
+ int, int, int));
int tga_identify __P((tga_reg_t *));
const struct tga_conf *tga_getconf __P((int));
-# $OpenBSD: Makefile,v 1.3 1996/10/30 22:40:49 niklas Exp $
-# $NetBSD: Makefile,v 1.1 1995/11/23 02:41:18 cgd Exp $
+# $OpenBSD: Makefile,v 1.4 1996/12/08 00:20:54 niklas Exp $
+# $NetBSD: Makefile,v 1.2 1996/11/06 23:09:13 cgd Exp $
.PATH: ${.CURDIR}/..
-PROG = installboot
-NOMAN =
-BINDIR = /usr/mdec
+PROG= installboot
+BINDIR= /usr/mdec
-CFLAGS += -g
+MAN= installboot.8
+MANSUBDIR=/alpha
+
+CFLAGS+= -g
.include <bsd.prog.mk>
-/* $OpenBSD: cfb.c,v 1.5 1996/11/23 21:44:57 kstailey Exp $ */
+/* $OpenBSD: cfb.c,v 1.6 1996/12/08 00:20:55 niklas Exp $ */
/* $NetBSD: cfb.c,v 1.5 1996/10/13 03:00:27 christos Exp $ */
/*
#include <sys/conf.h>
#include <sys/ioctl.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/tc/tcvar.h>
-/* $OpenBSD: sfb.c,v 1.5 1996/11/23 21:45:01 kstailey Exp $ */
+/* $OpenBSD: sfb.c,v 1.6 1996/12/08 00:20:56 niklas Exp $ */
/* $NetBSD: sfb.c,v 1.5 1996/10/13 03:00:35 christos Exp $ */
/*
#include <sys/conf.h>
#include <sys/ioctl.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/tc/tcvar.h>
+++ /dev/null
-/* $OpenBSD: tc_bus_io.c,v 1.4 1996/11/12 20:29:44 niklas Exp $ */
-/* $NetBSD: tc_bus_io.c,v 1.3 1996/07/09 00:55:31 cgd Exp $ */
-
-/*
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * TurboChannel "bus I/O" functions:
- * These functions make no sense for TC, and just panic.
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/syslog.h>
-#include <sys/device.h>
-#include <vm/vm.h>
-
-#include <machine/bus.old.h>
-#include <dev/tc/tcvar.h>
-
-int tc_io_map __P((void *, bus_io_addr_t, bus_io_size_t,
- bus_io_handle_t *));
-void tc_io_unmap __P((void *, bus_io_handle_t,
- bus_io_size_t));
-int tc_io_subregion __P((void *, bus_io_handle_t, bus_io_size_t,
- bus_io_size_t, bus_io_handle_t *));
-u_int8_t tc_io_read_1 __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int16_t tc_io_read_2 __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int32_t tc_io_read_4 __P((void *, bus_io_handle_t,
- bus_io_size_t));
-u_int64_t tc_io_read_8 __P((void *, bus_io_handle_t,
- bus_io_size_t));
-void tc_io_read_multi_1 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int8_t *, bus_io_size_t));
-void tc_io_read_multi_2 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int16_t *, bus_io_size_t));
-void tc_io_read_multi_4 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int32_t *, bus_io_size_t));
-void tc_io_read_multi_8 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int64_t *, bus_io_size_t));
-void tc_io_write_1 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int8_t));
-void tc_io_write_2 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int16_t));
-void tc_io_write_4 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int32_t));
-void tc_io_write_8 __P((void *, bus_io_handle_t,
- bus_io_size_t, u_int64_t));
-void tc_io_write_multi_1 __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int8_t *, bus_io_size_t));
-void tc_io_write_multi_2 __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int16_t *, bus_io_size_t));
-void tc_io_write_multi_4 __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int32_t *, bus_io_size_t));
-void tc_io_write_multi_8 __P((void *, bus_io_handle_t,
- bus_io_size_t, const u_int64_t *, bus_io_size_t));
-
-void
-tc_bus_io_init(bc, iov)
- bus_chipset_tag_t bc;
- void *iov;
-{
-
- bc->bc_i_v = iov;
-
- bc->bc_i_map = tc_io_map;
- bc->bc_i_unmap = tc_io_unmap;
- bc->bc_i_subregion = tc_io_subregion;
-
- bc->bc_ir1 = tc_io_read_1;
- bc->bc_ir2 = tc_io_read_2;
- bc->bc_ir4 = tc_io_read_4;
- bc->bc_ir8 = tc_io_read_8;
-
- bc->bc_irm1 = tc_io_read_multi_1;
- bc->bc_irm2 = tc_io_read_multi_2;
- bc->bc_irm4 = tc_io_read_multi_4;
- bc->bc_irm8 = tc_io_read_multi_8;
-
- bc->bc_iw1 = tc_io_write_1;
- bc->bc_iw2 = tc_io_write_2;
- bc->bc_iw4 = tc_io_write_4;
- bc->bc_iw8 = tc_io_write_8;
-
- bc->bc_iwm1 = tc_io_write_multi_1;
- bc->bc_iwm2 = tc_io_write_multi_2;
- bc->bc_iwm4 = tc_io_write_multi_4;
- bc->bc_iwm8 = tc_io_write_multi_8;
-}
-
-static const char *tc_bus_io_panicstr = "tc_io_%s nonsensical; unimplemented";
-
-int
-tc_io_map(v, ioaddr, iosize, iohp)
- void *v;
- bus_io_addr_t ioaddr;
- bus_io_size_t iosize;
- bus_io_handle_t *iohp;
-{
-
- panic(tc_bus_io_panicstr, "map");
-}
-
-void
-tc_io_unmap(v, ioh, iosize)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t iosize;
-{
-
- panic(tc_bus_io_panicstr, "unmap");
-}
-
-int
-tc_io_subregion(v, ioh, offset, size, nioh)
- void *v;
- bus_io_handle_t ioh, *nioh;
- bus_io_size_t offset, size;
-{
-
- panic(tc_bus_io_panicstr, "subregion");
-}
-
-u_int8_t
-tc_io_read_1(v, ioh, off)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
-{
-
- panic(tc_bus_io_panicstr, "read_1");
-}
-
-u_int16_t
-tc_io_read_2(v, ioh, off)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
-{
-
- panic(tc_bus_io_panicstr, "read_2");
-}
-
-u_int32_t
-tc_io_read_4(v, ioh, off)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
-{
-
- panic(tc_bus_io_panicstr, "read_4");
-}
-
-u_int64_t
-tc_io_read_8(v, ioh, off)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
-{
-
- panic(tc_bus_io_panicstr, "read_8");
-}
-
-void
-tc_io_read_multi_1(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int8_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "read_multi_1");
-}
-
-void
-tc_io_read_multi_2(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int16_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "read_multi_2");
-}
-
-void
-tc_io_read_multi_4(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int32_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "read_multi_4");
-}
-
-void
-tc_io_read_multi_8(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- u_int64_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "read_multi_8");
-}
-
-void
-tc_io_write_1(v, ioh, off, val)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
- u_int8_t val;
-{
-
- panic(tc_bus_io_panicstr, "write_1");
-}
-
-void
-tc_io_write_2(v, ioh, off, val)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
- u_int16_t val;
-{
-
- panic(tc_bus_io_panicstr, "write_2");
-}
-
-void
-tc_io_write_4(v, ioh, off, val)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
- u_int32_t val;
-{
-
- panic(tc_bus_io_panicstr, "write_4");
-}
-
-void
-tc_io_write_8(v, ioh, off, val)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off;
- u_int64_t val;
-{
-
- panic(tc_bus_io_panicstr, "write_8");
-}
-
-void
-tc_io_write_multi_1(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int8_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "write_multi_1");
-}
-
-void
-tc_io_write_multi_2(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int16_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "write_multi_2");
-}
-
-void
-tc_io_write_multi_4(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int32_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "write_multi_4");
-}
-
-void
-tc_io_write_multi_8(v, ioh, off, addr, count)
- void *v;
- bus_io_handle_t ioh;
- bus_io_size_t off, count;
- const u_int64_t *addr;
-{
-
- panic(tc_bus_io_panicstr, "write_multi_8");
-}
-/* $OpenBSD: tc_bus_mem.c,v 1.4 1996/11/12 20:29:45 niklas Exp $ */
-/* $NetBSD: tc_bus_mem.c,v 1.7 1996/07/09 00:55:33 cgd Exp $ */
+/* $OpenBSD: tc_bus_mem.c,v 1.5 1996/12/08 00:20:58 niklas Exp $ */
+/* $NetBSD: tc_bus_mem.c,v 1.9 1996/10/23 04:12:37 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
#include <sys/device.h>
#include <vm/vm.h>
-#include <machine/bus.old.h>
+#include <machine/bus.h>
#include <dev/tc/tcvar.h>
-int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t,
- int, bus_mem_handle_t *));
-void tc_mem_unmap __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-int tc_mem_subregion __P((void *, bus_mem_handle_t, bus_mem_size_t,
- bus_mem_size_t, bus_mem_handle_t *));
-u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t,
- bus_mem_size_t));
-void tc_mem_write_1 __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int8_t));
-void tc_mem_write_2 __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int16_t));
-void tc_mem_write_4 __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int32_t));
-void tc_mem_write_8 __P((void *, bus_mem_handle_t,
- bus_mem_size_t, u_int64_t));
-
-/* XXX DOES NOT BELONG */
-vm_offset_t tc_XXX_dmamap __P((void *));
-
-void
-tc_bus_mem_init(bc, memv)
- bus_chipset_tag_t bc;
+/* mapping/unmapping */
+int tc_mem_map __P((void *, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *));
+void tc_mem_unmap __P((void *, bus_space_handle_t, bus_size_t));
+int tc_mem_subregion __P((void *, bus_space_handle_t, bus_size_t,
+ bus_size_t, bus_space_handle_t *));
+
+/* allocation/deallocation */
+int tc_mem_alloc __P((void *, bus_addr_t, bus_addr_t, bus_size_t,
+ bus_size_t, bus_addr_t, int, bus_addr_t *,
+ bus_space_handle_t *));
+void tc_mem_free __P((void *, bus_space_handle_t, bus_size_t));
+
+/* read (single) */
+u_int8_t tc_mem_read_1 __P((void *, bus_space_handle_t, bus_size_t));
+u_int16_t tc_mem_read_2 __P((void *, bus_space_handle_t, bus_size_t));
+u_int32_t tc_mem_read_4 __P((void *, bus_space_handle_t, bus_size_t));
+u_int64_t tc_mem_read_8 __P((void *, bus_space_handle_t, bus_size_t));
+
+/* read multiple */
+void tc_mem_read_multi_1 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void tc_mem_read_multi_2 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void tc_mem_read_multi_4 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void tc_mem_read_multi_8 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* read region */
+void tc_mem_read_region_1 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t));
+void tc_mem_read_region_2 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t));
+void tc_mem_read_region_4 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t));
+void tc_mem_read_region_8 __P((void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t));
+
+/* write (single) */
+void tc_mem_write_1 __P((void *, bus_space_handle_t, bus_size_t,
+ u_int8_t));
+void tc_mem_write_2 __P((void *, bus_space_handle_t, bus_size_t,
+ u_int16_t));
+void tc_mem_write_4 __P((void *, bus_space_handle_t, bus_size_t,
+ u_int32_t));
+void tc_mem_write_8 __P((void *, bus_space_handle_t, bus_size_t,
+ u_int64_t));
+
+/* write multiple */
+void tc_mem_write_multi_1 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void tc_mem_write_multi_2 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void tc_mem_write_multi_4 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void tc_mem_write_multi_8 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* write region */
+void tc_mem_write_region_1 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t));
+void tc_mem_write_region_2 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t));
+void tc_mem_write_region_4 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t));
+void tc_mem_write_region_8 __P((void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t));
+
+/* barrier */
+void tc_mem_barrier __P((void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, int));
+
+
+static struct alpha_bus_space tc_mem_space = {
+ /* cookie */
+ NULL,
+
+ /* mapping/unmapping */
+ tc_mem_map,
+ tc_mem_unmap,
+ tc_mem_subregion,
+
+ /* allocation/deallocation */
+ tc_mem_alloc,
+ tc_mem_free,
+
+ /* read (single) */
+ tc_mem_read_1,
+ tc_mem_read_2,
+ tc_mem_read_4,
+ tc_mem_read_8,
+
+ /* read multi */
+ tc_mem_read_multi_1,
+ tc_mem_read_multi_2,
+ tc_mem_read_multi_4,
+ tc_mem_read_multi_8,
+
+ /* read region */
+ tc_mem_read_region_1,
+ tc_mem_read_region_2,
+ tc_mem_read_region_4,
+ tc_mem_read_region_8,
+
+ /* write (single) */
+ tc_mem_write_1,
+ tc_mem_write_2,
+ tc_mem_write_4,
+ tc_mem_write_8,
+
+ /* write multi */
+ tc_mem_write_multi_1,
+ tc_mem_write_multi_2,
+ tc_mem_write_multi_4,
+ tc_mem_write_multi_8,
+
+ /* write region */
+ tc_mem_write_region_1,
+ tc_mem_write_region_2,
+ tc_mem_write_region_4,
+ tc_mem_write_region_8,
+
+ /* set multi */
+ /* XXX IMPLEMENT */
+
+ /* set region */
+ /* XXX IMPLEMENT */
+
+ /* copy */
+ /* XXX IMPLEMENT */
+
+ /* barrier */
+ tc_mem_barrier,
+};
+
+bus_space_tag_t
+tc_bus_mem_init(memv)
void *memv;
{
+ bus_space_tag_t h = &tc_mem_space;
- bc->bc_m_v = memv;
-
- bc->bc_m_map = tc_mem_map;
- bc->bc_m_unmap = tc_mem_unmap;
- bc->bc_m_subregion = tc_mem_subregion;
-
- bc->bc_mr1 = tc_mem_read_1;
- bc->bc_mr2 = tc_mem_read_2;
- bc->bc_mr4 = tc_mem_read_4;
- bc->bc_mr8 = tc_mem_read_8;
-
- bc->bc_mw1 = tc_mem_write_1;
- bc->bc_mw2 = tc_mem_write_2;
- bc->bc_mw4 = tc_mem_write_4;
- bc->bc_mw8 = tc_mem_write_8;
-
- /* XXX DOES NOT BELONG */
- bc->bc_XXX_dmamap = tc_XXX_dmamap;
+ h->abs_cookie = memv;
+ return (h);
}
int
tc_mem_map(v, memaddr, memsize, cacheable, memhp)
void *v;
- bus_mem_addr_t memaddr;
- bus_mem_size_t memsize;
+ bus_addr_t memaddr;
+ bus_size_t memsize;
int cacheable;
- bus_mem_handle_t *memhp;
+ bus_space_handle_t *memhp;
{
if (memaddr & 0x7)
void
tc_mem_unmap(v, memh, memsize)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t memsize;
+ bus_space_handle_t memh;
+ bus_size_t memsize;
{
- /* XXX nothing to do. */
+ /* XXX XX XXX nothing to do. */
}
int
tc_mem_subregion(v, memh, offset, size, nmemh)
void *v;
- bus_mem_handle_t memh, *nmemh;
- bus_mem_size_t offset, size;
+ bus_space_handle_t memh, *nmemh;
+ bus_size_t offset, size;
{
/* Disallow subregioning that would make the handle unaligned. */
return (0);
}
+int
+tc_mem_alloc(v, rstart, rend, size, align, boundary, cacheable, addrp, bshp)
+ void *v;
+ bus_addr_t rstart, rend, *addrp;
+ bus_size_t size, align, boundary;
+ int cacheable;
+ bus_space_handle_t *bshp;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("tc_mem_alloc unimplemented");
+}
+
+void
+tc_mem_free(v, bsh, size)
+ void *v;
+ bus_space_handle_t bsh;
+ bus_size_t size;
+{
+
+ /* XXX XXX XXX XXX XXX XXX */
+ panic("tc_mem_free unimplemented");
+}
+
u_int8_t
tc_mem_read_1(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
volatile u_int8_t *p;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
if ((memh & TC_SPACE_SPARSE) != 0)
panic("tc_mem_read_1 not implemented for sparse space");
u_int16_t
tc_mem_read_2(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
volatile u_int16_t *p;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
if ((memh & TC_SPACE_SPARSE) != 0)
panic("tc_mem_read_2 not implemented for sparse space");
u_int32_t
tc_mem_read_4(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
volatile u_int32_t *p;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
if ((memh & TC_SPACE_SPARSE) != 0)
/* Nothing special to do for 4-byte sparse space accesses */
u_int64_t
tc_mem_read_8(v, memh, off)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
{
volatile u_int64_t *p;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
if ((memh & TC_SPACE_SPARSE) != 0)
panic("tc_mem_read_8 not implemented for sparse space");
return (*p);
}
+
+#define tc_mem_read_multi_N(BYTES,TYPE) \
+void \
+__abs_c(tc_mem_read_multi_,BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ tc_mem_barrier(v, h, o, sizeof *a, BUS_BARRIER_READ); \
+ *a++ = __abs_c(tc_mem_read_,BYTES)(v, h, o); \
+ } \
+}
+tc_mem_read_multi_N(1,u_int8_t)
+tc_mem_read_multi_N(2,u_int16_t)
+tc_mem_read_multi_N(4,u_int32_t)
+tc_mem_read_multi_N(8,u_int64_t)
+
+#define tc_mem_read_region_N(BYTES,TYPE) \
+void \
+__abs_c(tc_mem_read_region_,BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ *a++ = __abs_c(tc_mem_read_,BYTES)(v, h, o); \
+ o += sizeof *a; \
+ } \
+}
+tc_mem_read_region_N(1,u_int8_t)
+tc_mem_read_region_N(2,u_int16_t)
+tc_mem_read_region_N(4,u_int32_t)
+tc_mem_read_region_N(8,u_int64_t)
+
void
tc_mem_write_1(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int8_t val;
{
p = (u_int8_t *)(memh + off);
*p = val;
}
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
}
void
tc_mem_write_2(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int16_t val;
{
p = (u_int16_t *)(memh + off);
*p = val;
}
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
}
void
tc_mem_write_4(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int32_t val;
{
volatile u_int32_t *p;
else
p = (u_int32_t *)(memh + off);
*p = val;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
}
void
tc_mem_write_8(v, memh, off, val)
void *v;
- bus_mem_handle_t memh;
- bus_mem_size_t off;
+ bus_space_handle_t memh;
+ bus_size_t off;
u_int64_t val;
{
volatile u_int64_t *p;
p = (u_int64_t *)(memh + off);
*p = val;
- alpha_mb();
+ alpha_mb(); /* XXX XXX XXX */
+}
+#define tc_mem_write_multi_N(BYTES,TYPE) \
+void \
+__abs_c(tc_mem_write_multi_,BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __abs_c(tc_mem_write_,BYTES)(v, h, o, *a++); \
+ tc_mem_barrier(v, h, o, sizeof *a, BUS_BARRIER_WRITE); \
+ } \
}
+tc_mem_write_multi_N(1,u_int8_t)
+tc_mem_write_multi_N(2,u_int16_t)
+tc_mem_write_multi_N(4,u_int32_t)
+tc_mem_write_multi_N(8,u_int64_t)
+
+#define tc_mem_write_region_N(BYTES,TYPE) \
+void \
+__abs_c(tc_mem_write_region_,BYTES)(v, h, o, a, c) \
+ void *v; \
+ bus_space_handle_t h; \
+ bus_size_t o, c; \
+ const TYPE *a; \
+{ \
+ \
+ while (c-- > 0) { \
+ __abs_c(tc_mem_write_,BYTES)(v, h, o, *a++); \
+ o += sizeof *a; \
+ } \
+}
+tc_mem_write_region_N(1,u_int8_t)
+tc_mem_write_region_N(2,u_int16_t)
+tc_mem_write_region_N(4,u_int32_t)
+tc_mem_write_region_N(8,u_int64_t)
-/* XXX DOES NOT BELONG */
-vm_offset_t
-tc_XXX_dmamap(addr)
- void *addr;
+void
+tc_mem_barrier(v, h, o, l, f)
+ void *v;
+ bus_space_handle_t h;
+ bus_size_t o, l;
+ int f;
{
- return (vtophys((vm_offset_t)addr));
+ if ((f & BUS_BARRIER_READ) != 0)
+ alpha_mb();
+ else if ((f & BUS_BARRIER_WRITE) != 0)
+ alpha_wmb();
}
-/* $OpenBSD: tc_machdep.h,v 1.3 1996/10/30 22:41:23 niklas Exp $ */
-/* $NetBSD: tc_machdep.h,v 1.2 1996/07/09 00:55:35 cgd Exp $ */
+/* $OpenBSD: tc_machdep.h,v 1.4 1996/12/08 00:20:59 niklas Exp $ */
+/* $NetBSD: tc_machdep.h,v 1.3 1996/10/22 21:34:22 cgd Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
#define TC_PHYS_TO_UNCACHED(addr) \
(addr)
-void tc_bus_io_init __P((bus_chipset_tag_t bc, void *iov));;
-void tc_bus_mem_init __P((bus_chipset_tag_t bc, void *memv));;
+bus_space_tag_t tc_bus_mem_init __P((void *memv));;
-/* $OpenBSD: tcasic.c,v 1.5 1996/11/23 21:45:01 kstailey Exp $ */
-/* $NetBSD: tcasic.c,v 1.10 1996/10/13 03:00:39 christos Exp $ */
+/* $OpenBSD: tcasic.c,v 1.6 1996/12/08 00:21:00 niklas Exp $ */
+/* $NetBSD: tcasic.c,v 1.12 1996/10/23 04:12:38 cgd Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
struct tcbus_attach_args tba;
void (*intr_setup) __P((void));
void (*iointr) __P((void *, unsigned long));
- struct alpha_bus_chipset bc;
printf("\n");
tcasicfound = 1;
panic("tcasicattach: bad cputype");
}
- tc_bus_io_init(&bc, NULL);
- tc_bus_mem_init(&bc, NULL);
- tba.tba_bc = &bc;
+ tba.tba_memt = tc_bus_mem_init(NULL);
+
+ /* XXX XXX BEGIN XXX XXX */
+ { /* XXX */
+ extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */
+ alpha_XXX_dmamap_or = 0; /* XXX */
+ } /* XXX */
+ /* XXX XXX END XXX XXX */
(*intr_setup)();
set_iointr(iointr);
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