-/* $OpenBSD: cpu.c,v 1.110 2024/03/16 09:15:04 jsg Exp $ */
+/* $OpenBSD: cpu.c,v 1.111 2024/03/17 13:05:40 kettenis Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
sep = ",";
}
- if (ID_AA64PFR1_SBSS(id) >= ID_AA64PFR1_SBSS_PSTATE) {
- printf("%sSBSS", sep);
+ if (ID_AA64PFR1_SSBS(id) >= ID_AA64PFR1_SSBS_PSTATE) {
+ printf("%sSSBS", sep);
sep = ",";
}
- if (ID_AA64PFR1_SBSS(id) >= ID_AA64PFR1_SBSS_PSTATE_MSR)
+ if (ID_AA64PFR1_SSBS(id) >= ID_AA64PFR1_SSBS_PSTATE_MSR)
printf("+MSR");
if (ID_AA64PFR1_MTE(id) >= ID_AA64PFR1_MTE_IMPL) {
-/* $OpenBSD: machdep.c,v 1.87 2024/03/13 14:57:08 kettenis Exp $ */
+/* $OpenBSD: machdep.c,v 1.88 2024/03/17 13:05:40 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
case CPU_ID_AA64PFR1:
value = 0;
value |= cpu_id_aa64pfr1 & ID_AA64PFR1_BT_MASK;
- value |= cpu_id_aa64pfr1 & ID_AA64PFR1_SBSS_MASK;
+ value |= cpu_id_aa64pfr1 & ID_AA64PFR1_SSBS_MASK;
return sysctl_rdquad(oldp, oldlenp, newp, value);
case CPU_ID_AA64ISAR2:
case CPU_ID_AA64MMFR0:
-/* $OpenBSD: armreg.h,v 1.31 2024/03/05 18:42:20 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.32 2024/03/17 13:05:40 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* Copyright (c) 2015 The FreeBSD Foundation
#define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK)
#define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT)
-#define ID_AA64PFR1_SBSS_SHIFT 4
-#define ID_AA64PFR1_SBSS_MASK (0xfULL << ID_AA64PFR1_SBSS_SHIFT)
-#define ID_AA64PFR1_SBSS(x) ((x) & ID_AA64PFR1_SBSS_MASK)
-#define ID_AA64PFR1_SBSS_NONE (0x0ULL << ID_AA64PFR1_SBSS_SHIFT)
-#define ID_AA64PFR1_SBSS_PSTATE (0x1ULL << ID_AA64PFR1_SBSS_SHIFT)
-#define ID_AA64PFR1_SBSS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SBSS_SHIFT)
+#define ID_AA64PFR1_SSBS_SHIFT 4
+#define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT)
+#define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK)
+#define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT)
+#define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT)
+#define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_MTE_SHIFT 8
#define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK)