Separate out the Access Flag bit from the Access Permission bits in the

armv7 pmap.

ok tom@

diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c
index 57e98ec..07924e6 100644 (file)
--- a/sys/arch/arm/arm/pmap7.c
+++ b/sys/arch/arm/arm/pmap7.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pmap7.c,v 1.38 2016/08/16 10:16:33 kettenis Exp $     */
+/*     $OpenBSD: pmap7.c,v 1.39 2016/08/18 09:28:22 kettenis Exp $     */
 /*     $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $   */
 
 /*
@@ -1136,7 +1136,7 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags)
        }
        ptep = &l2b->l2b_kva[l2pte_index(va)];
        opte = *ptep;
-       npte = pa;
+       npte = pa | L2_V7_AF;
 
        if (opte != 0) {        /* not l2pte_valid!!! MIOD */
                /*
@@ -1430,7 +1430,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot)
        else if (pa & PMAP_NOCACHE)
                cache_mode = L2_V7_S_TEX(1);
 
-       npte = L2_S_PROTO | (pa & PMAP_PA_MASK) |
+       npte = L2_S_PROTO | (pa & PMAP_PA_MASK) | L2_V7_AF |
            L2_S_PROT(PTE_KERNEL, prot) | cache_mode;
        *ptep = npte;
        PTE_SYNC(ptep);
@@ -2072,7 +2072,7 @@ pmap_zero_page_generic(struct vm_page *pg)
         * Hook in the page, zero it, and purge the cache for that
         * zeroed page. Invalidate the TLB as needed.
         */
-       *cdst_pte = L2_S_PROTO | phys |
+       *cdst_pte = L2_S_PROTO | phys | L2_V7_AF |
            L2_S_PROT(PTE_KERNEL, PROT_WRITE) | pte_l2_s_cache_mode;
        PTE_SYNC(cdst_pte);
        cpu_tlb_flushD_SE(cdstp);
@@ -2102,10 +2102,10 @@ pmap_copy_page_generic(struct vm_page *src_pg, struct vm_page *dst_pg)
         * the cache for the appropriate page. Invalidate the TLB
         * as required.
         */
-       *csrc_pte = L2_S_PROTO | src |
+       *csrc_pte = L2_S_PROTO | src | L2_V7_AF |
            L2_S_PROT(PTE_KERNEL, PROT_READ) | pte_l2_s_cache_mode;
        PTE_SYNC(csrc_pte);
-       *cdst_pte = L2_S_PROTO | dst |
+       *cdst_pte = L2_S_PROTO | dst | L2_V7_AF |
            L2_S_PROT(PTE_KERNEL, PROT_WRITE) | pte_l2_s_cache_mode;
        PTE_SYNC(cdst_pte);
        cpu_tlb_flushD_SE(csrcp);
@@ -2156,7 +2156,7 @@ pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap)
        KDASSERT(l2b != NULL);
 
        ptep = &l2b->l2b_kva[l2pte_index(va)];
-       *ptep = L2_S_PROTO | pa | cache_mode |
+       *ptep = L2_S_PROTO | pa | L2_V7_AF | cache_mode |
            L2_S_PROT(PTE_KERNEL, PROT_READ | PROT_WRITE);
        PTE_SYNC(ptep);
        cpu_tlb_flushD_SE(va);
@@ -2743,7 +2743,7 @@ pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache)
                break;
        }
 
-       pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
+       pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | L1_S_V7_AF |
            L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
        PTE_SYNC(&pde[va >> L1_S_SHIFT]);
 }
@@ -2788,12 +2788,12 @@ pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache)
                panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va);
 
 #ifndef ARM32_NEW_VM_LAYOUT
-       pte[(va >> PGSHIFT) & 0x3ff] =
-           L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
+       pte[(va >> PGSHIFT) & 0x3ff] = L2_S_PROTO | pa | L2_V7_AF |
+           L2_S_PROT(PTE_KERNEL, prot) | fl;
        PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]);
 #else
-       pte[l2pte_index(va)] =
-           L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
+       pte[l2pte_index(va)] = L2_S_PROTO | pa | L2_V7_AF |
+           L2_S_PROT(PTE_KERNEL, prot) | fl;
        PTE_SYNC(&pte[l2pte_index(va)]);
 #endif
 }
@@ -2881,8 +2881,8 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size,
                        printf("S");
 #endif
                        pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
-                           L1_S_PROT(PTE_KERNEL, prot) | f1 |
-                           L1_S_DOM(PMAP_DOMAIN_KERNEL);
+                           L1_S_V7_AF | L1_S_PROT(PTE_KERNEL, prot) |
+                           f1 | L1_S_DOM(PMAP_DOMAIN_KERNEL);
                        PTE_SYNC(&pde[va >> L1_S_SHIFT]);
                        va += L1_S_SIZE;
                        pa += L1_S_SIZE;
@@ -2917,12 +2917,12 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size,
                        for (i = 0; i < 16; i++) {
 #ifndef ARM32_NEW_VM_LAYOUT
                                pte[((va >> PGSHIFT) & 0x3f0) + i] =
-                                   L2_L_PROTO | pa |
+                                   L2_L_PROTO | pa | L2_V7_AF |
                                    L2_L_PROT(PTE_KERNEL, prot) | f2l;
                                PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]);
 #else
                                pte[l2pte_index(va) + i] =
-                                   L2_L_PROTO | pa |
+                                   L2_L_PROTO | pa | L2_V7_AF |
                                    L2_L_PROT(PTE_KERNEL, prot) | f2l;
                                PTE_SYNC(&pte[l2pte_index(va) + i]);
 #endif
@@ -2938,12 +2938,12 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size,
                printf("P");
 #endif
 #ifndef ARM32_NEW_VM_LAYOUT
-               pte[(va >> PGSHIFT) & 0x3ff] =
-                   L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
+               pte[(va >> PGSHIFT) & 0x3ff] = L2_S_PROTO | pa | L2_V7_AF |
+                   L2_S_PROT(PTE_KERNEL, prot) | f2s;
                PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]);
 #else
-               pte[l2pte_index(va)] =
-                   L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
+               pte[l2pte_index(va)] = L2_S_PROTO | pa | L2_V7_AF |
+                   L2_S_PROT(PTE_KERNEL, prot) | f2s;
                PTE_SYNC(&pte[l2pte_index(va)]);
 #endif
                va += PAGE_SIZE;

diff --git a/sys/arch/arm/include/pte.h b/sys/arch/arm/include/pte.h
index ba1c736..059e281 100644 (file)
--- a/sys/arch/arm/include/pte.h
+++ b/sys/arch/arm/include/pte.h
@@ -1,4 +1,4 @@
-/*     $OpenBSD: pte.h,v 1.6 2016/08/10 22:28:51 kettenis Exp $        */
+/*     $OpenBSD: pte.h,v 1.7 2016/08/18 09:28:22 kettenis Exp $        */
 /*     $NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $      */
 
 /*
@@ -155,8 +155,8 @@ typedef uint32_t    pt_entry_t;     /* L2 table entry */
 #define        L1_S_V7_SS      0x00040000      /* Supersection */
 #define        L1_S_V7_nG      0x00020000      /* not Global */
 #define        L1_S_V7_S       0x00010000      /* Shareable */
-#define        L1_S_V7_AP(x)   ((((x) & 0x4) << 13) | (((x) & 3) << 10))       /* AP */
-#define        L1_S_V7_AF      L1_S_V7_AP(1)   /* Access Flag */
+#define        L1_S_V7_AP(x)   ((((x) & 0x4) << 13) | (((x) & 0x2) << 10))     /* AP */
+#define        L1_S_V7_AF      0x00000400      /* Access Flag */
 #define        L1_S_V7_IMP     0x00000200      /* implementation defined */
 #define        L1_S_V7_XN      0x00000010      /* eXecute Never */
 
@@ -219,8 +219,8 @@ typedef uint32_t    pt_entry_t;     /* L2 table entry */
 #define        L2_V7_S_TEX_MASK        (0x7 << 6)      /* Type Extension */
 #define        L2_V7_S_XN      0x00000001      /* eXecute Never */
 
-#define        L2_V7_AP(x)     ((((x) & 0x04) << 7) | (((x) & 0x03) << 4))     /* AP */
-#define        L2_V7_AF        L2_V7_AP(1)     /* Access Flag */
+#define        L2_V7_AP(x)     ((((x) & 0x4) << 7) | (((x) & 0x2) << 4))       /* AP */
+#define        L2_V7_AF        0x00000010      /* Access Flag */
 #define        L2_V7_S         0x00000400      /* Sharable */
 #define        L2_V7_nG        0x00000800      /* not Global */
 

diff --git a/sys/arch/armv7/armv7/armv7_start.S b/sys/arch/armv7/armv7/armv7_start.S
index e7d773b..628cda0 100644 (file)
--- a/sys/arch/armv7/armv7/armv7_start.S
+++ b/sys/arch/armv7/armv7/armv7_start.S
@@ -1,4 +1,4 @@
-/*     $OpenBSD: armv7_start.S,v 1.7 2016/07/26 18:09:07 kettenis Exp $        */
+/*     $OpenBSD: armv7_start.S,v 1.8 2016/08/18 09:28:22 kettenis Exp $        */
 /*     $NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */
 
 /*
@@ -179,11 +179,14 @@ Lstart:
 
 mmu_init_table:
        /* map SDRAM VA==PA, WT cacheable */
-       MMU_INIT(0x00000000, 0x00000000, 64, L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW))
+       MMU_INIT(0x00000000, 0x00000000, 64,
+                L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW)|L1_S_V7_AF)
 mmu_init_table2:       
        /* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */
-       MMU_INIT(0xc0000000, 0x00000000, 64, L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW))
-       MMU_INIT(0x00000000, 0x00000000, 1, L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW))
+       MMU_INIT(0xc0000000, 0x00000000, 64,
+                L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW)|L1_S_V7_AF)
+       MMU_INIT(0x00000000, 0x00000000, 1,
+                L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW)|L1_S_V7_AF)
 
        .word 0 /* end of table */