drm/i915: Replace several IS_METEORLAKE with proper IP version checks

From Matt Roper
ec84b2a44b057b2c51ed9f670b92690904e1106c in linux-6.6.y/6.6.26
14128d64090fa88445376cb8ccf91c50c08bd410 in mainline linux

diff --git a/sys/dev/pci/drm/i915/gem/i915_gem_create.c b/sys/dev/pci/drm/i915/gem/i915_gem_create.c
index d24c0ce..19156ba 100644 (file)
--- a/sys/dev/pci/drm/i915/gem/i915_gem_create.c
+++ b/sys/dev/pci/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
        BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
                     offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
 
-       /* Limiting the extension only to Meteor Lake */
-       if (!IS_METEORLAKE(i915))
+       /* Limiting the extension only to Xe_LPG and beyond */
+       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
                return -ENODEV;
 
        if (copy_from_user(&ext, base, sizeof(ext)))

diff --git a/sys/dev/pci/drm/i915/gt/intel_engine_pm.c b/sys/dev/pci/drm/i915/gt/intel_engine_pm.c
index a95615b..5a3a5b2 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_engine_pm.c
+++ b/sys/dev/pci/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *i915 = engine->i915;
 
-       if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+       if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
                intel_uncore_write(engine->gt->uncore,
                                   RC_PSMI_CTRL_GSCCS,
                                   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

diff --git a/sys/dev/pci/drm/i915/gt/intel_mocs.c b/sys/dev/pci/drm/i915/gt/intel_mocs.c
index bf8b42d..07269ff 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_mocs.c
+++ b/sys/dev/pci/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
        memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
        table->unused_entries_index = I915_MOCS_PTE;
-       if (IS_METEORLAKE(i915)) {
+       if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
                table->size = ARRAY_SIZE(mtl_mocs_table);
                table->table = mtl_mocs_table;
                table->n_entries = MTL_NUM_MOCS_ENTRIES;

diff --git a/sys/dev/pci/drm/i915/gt/intel_rc6.c b/sys/dev/pci/drm/i915/gt/intel_rc6.c
index b8c9338..9e113e9 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_rc6.c
+++ b/sys/dev/pci/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
         * temporary wa and should be removed after fixing real cause
         * of forcewake timeouts.
         */
-       if (IS_METEORLAKE(gt->i915))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
                pg_enable =
                        GEN9_MEDIA_PG_ENABLE |
                        GEN11_MEDIA_SAMPLER_PG_ENABLE;

diff --git a/sys/dev/pci/drm/i915/gt/intel_reset.c b/sys/dev/pci/drm/i915/gt/intel_reset.c
index 3990731..eb8c90a 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_reset.c
+++ b/sys/dev/pci/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
 
 static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 {
-       if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+       if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
                return false;
 
        if (!__HAS_ENGINE(engine_mask, GSC0))

diff --git a/sys/dev/pci/drm/i915/gt/intel_rps.c b/sys/dev/pci/drm/i915/gt/intel_rps.c
index 37f70f0..1f90be9 100644 (file)
--- a/sys/dev/pci/drm/i915/gt/intel_rps.c
+++ b/sys/dev/pci/drm/i915/gt/intel_rps.c
@@ -1163,7 +1163,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
 
-       if (IS_METEORLAKE(i915))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
                return mtl_get_freq_caps(rps, caps);
        else
                return __gen6_rps_get_freq_caps(rps, caps);

diff --git a/sys/dev/pci/drm/i915/i915_debugfs.c b/sys/dev/pci/drm/i915/i915_debugfs.c
index 4de44cf..7a90a2e 100644 (file)
--- a/sys/dev/pci/drm/i915/i915_debugfs.c
+++ b/sys/dev/pci/drm/i915/i915_debugfs.c
@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
 {
        struct drm_i915_private *i915 = obj_to_i915(obj);
 
-       if (IS_METEORLAKE(i915)) {
+       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
                switch (obj->pat_index) {
                case 0: return " WB";
                case 1: return " WT";

diff --git a/sys/dev/pci/drm/i915/i915_perf.c b/sys/dev/pci/drm/i915/i915_perf.c
index 92a6050..0a111d1 100644 (file)
--- a/sys/dev/pci/drm/i915/i915_perf.c
+++ b/sys/dev/pci/drm/i915/i915_perf.c
@@ -3285,11 +3285,10 @@ get_sseu_config(struct intel_sseu *out_sseu,
  */
 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 {
-       /*
-        * Wa_18013179988:dg2
-        * Wa_14015846243:mtl
-        */
-       if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
+       struct intel_gt *gt = to_gt(i915);
+
+       /* Wa_18013179988 */
+       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
                intel_wakeref_t wakeref;
                u32 reg, shift;
 
@@ -4607,7 +4606,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
-       if (IS_METEORLAKE(perf->i915))
+       if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
                return reg_in_range_table(addr, mtl_oa_mux_regs);
        else
                return reg_in_range_table(addr, gen12_oa_mux_regs);